JPS6024623B2 - Facsimile line control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a facsimile line control device in which the number of counters for providing write addresses and read addresses for a pair of memories included in a plurality of line corresponding units is reduced.

Plans are underway to reduce fees for recent facsimile lines by using, for example, the configuration shown in FIG. 1, in which long-distance offices are connected using high-speed facsimile dedicated lines.

In Fig. 1, 1 is a facsimile machine, 3 and 13 are the toll office communications office, and 4 and 4M are the line correspondence units on the sending side. If there is any information, it will be output when an instruction is received from the buffer memory 6, which will be described later. Reference numeral 5 denotes a common encoder, which encodes and compresses the image signals inputted from the selected line corresponding section 4i.

A buffer memory (BM) 6 measures whether or not there is an image signal to be transmitted to each line corresponding part 4i via a line (not shown) connected to each of the line corresponding parts 4, to 4n,
The image signals of the line corresponding parts in which the image signals exist are sequentially scanned line by line, and the image signals of each line corresponding part are introduced into the encoder 5. In addition, this buffer memory (BM
) 6 is a function that stores the image information encoded by the encoder 5 in each line corresponding section, and when several lines have been accumulated, adds identification information of the line corresponding section and sends the image information to the receiving side. has. Based on the received identification information, the receiving side buffer memory 16 specifies, through a decoder, the line corresponding section to be received among the line corresponding sections 14, to 14n, for example, the line corresponding section 14, and also specifies the line corresponding section to be received subsequently. It has a function of introducing image information into the decoder 15.

Based on this identification information, the decoder 15 connects the line corresponding parts 14, . . .
Set one of the pair of lines connected to 14n to high level,
A signal obtained by decoding image information is supplied to the other side. Also, at this time, it has a function of sending out a clock in synchronization with the decoded signal. In the system having the above functions, the sending side, that is, the sending side facsimile (FAX-S) 1 passes through the telephone line changeover switch 2 and enters the toll office transit machine 3 for exchange. After one of the line corresponding parts 4, to 4n is selected and code-compressed by the encoder 5, it is stored in a buffer memory (BM) 6, and transferred to the buffer memory (BM) 16 on the receiving side via a high-speed transmission line 10.
After being decoded by the decoder 15 in the opposite direction to the sending side, it is transmitted to the receiving side's toll office exchange 1-3 through one of the predetermined line correspondence sections 4 to 14n and transmitted to the other party's facsimile (FAX-
R) 1 as an image signal. Note that this facsimile (FAX-R) 1 corresponds to one of the line corresponding parts 14, to 14n, and there are other parts n, although not shown.
-There is one facsimile machine. FIG. 2 shows the configuration of a known example of the line corresponding parts 4, to 4n on the transmitting side in this case.

Since these have the same configuration, they will be explained without subscripts. A pair of memories (M
O) 21 and (MI) 23 are provided, and the decoder 1 is connected to the BM16.
By switching the input side switch SI and the output side switch S2, the image signal is supplied to one memory via the switch SI through the AND circuit 25 which decodes the image signal information compressed in step 5 and is controlled by line designation, and is supplied to the other memory. The contents of the memory are sent to the facsimile terminal via switch S2. On the other hand, counters 22 and 24 that provide write addresses to these memories (MO) 21 and (MI) 23 switch sampling clocks using switches S3 and S4, and the decoded image signal information passes through an AND circuit 25 and switch SI to one side. When supplied to one memory, a write address is given by the corresponding counter, and a read clock is given to the other memory by the corresponding counter. Switch S in the diagram
At positions I to S4, the decoder 15 sends a clock to the counter 24 through the AND circuit 26 and switch S4, gives a write address to the memory (MI) 23, and decoders 15
from the memory (M
I) The image signal supplied to 23 is stored. On the other hand, the clock is sent to the counter 22 through the switch S3, a read address is given to the memory (MO) 21, its contents are read out, and the clock is sent to the facsimile terminal via the switch S2. In this case, the decoder 15 performs line designation control on the AND circuits 25 and 26. Although the switches SI to S4 are shown here in the form of ordinary switches, it goes without saying that these can be constructed using logic gates.
These components are mounted on a printed circuit board as an integrated circuit, but miniaturization and simplification have become a problem. In particular, the counters 22 and 24 are made up of a large number of gate circuits and account for a large proportion of the space factor, so if they can be reduced, benefits can be obtained from miniaturization and cost reduction, which can be applied to multiple line support sections. is big. SUMMARY OF THE INVENTION An object of the present invention is to provide an image signal processing device that reduces the number of counters that provide write addresses and read addresses for a pair of memories included in a plurality of line corresponding sections.

In order to achieve the above object, the box signal processing device of the present invention includes a plurality of line corresponding sections and a common decoding section that decodes a received image signal and distributes the decoded image signal to each of the line corresponding sections, By providing a pair of memories in the line corresponding section and switching between them, one memo IJI is storing the image signal from the common decoding section, while the other memory's contents are read out to the facsimile terminal.Facsimile line control In the apparatus, a counter is provided in each of the line corresponding sections to give a readout address of one memo stream for storing image signals from the common decoding section, and a counter is provided in the common decoding section to give a write address of the switched memo stream. This feature is characterized by the provision of a common counter that gives .

The principle and embodiments of the present invention will be explained in detail below.

FIG. 3 is a schematic explanatory diagram of an embodiment of the present invention. Components that are the same as those in FIG. 2 are given the same numbers. A pair of memories (MO) 21 are included in the line corresponding section 14 surrounded by the chain line in the figure.
and (MI) 23 are provided, and by switching the switches SI and S2, the decoded image signal from the common decoding section 15 is stored in the memory on one side via the AND circuit 25 controlled by line designation and the switch SI, and The memory contents of switch S2
As shown in FIG. 2, the information is sent to the facsimile terminal via the .

The difference in the figure is that the memory (MO) 21, (MI)
In order to provide a read address, one common counter 35 is provided in the common decoding unit 15 instead of providing a counter in each line corresponding unit 14. This is because we have established the following. Since reading can be performed at high speed, it is easy to read data from one memory of the line correspondence section 14 while reading from the other memory across a plurality of line correspondence sections 14. By using the above configuration, it is sufficient to reduce the number of counters provided in the line correspondence section 14 by half and add one counter to the common decoding section 15. In the same figure, the decoded image signal from the common decoding section 15 is connected to the AND circuit 25 and the switch S.
When supplied to one memory (MI) 23 via I, the common decoding unit 15 specifies the line corresponding unit 14.
Next, from the counter 35, the AND circuit 33 and the switch S13
The image signal is stored in the memory (MI) 23 via the AND circuit 25, and the image signal is stored in the memory (MI) 23 from the power counter 31 to the switch SII.
The read memory is provided through the memory (MO) 21
The contents are sent to the facsimile terminal via switch S2. This procedure is sequentially transferred from the written memo IJI of the line correspondence units 14, to 14n. For example, if n=10, from the address ADO shown by the solid line in the figure to the switches S12, S
It is specified over the dotted line address AD9 controlled by 14. These designations are performed by line designation control from the common decoder 15. In this way, the read address of the pair of memories in the line correspondence section can be given by a common counter provided for each line correspondence section, and the write address can be given by a common counter provided in the common decoding section. As a result, the number of counters in the line corresponding section is halved, and it is only necessary to add one counter in the common decoding section, thereby realizing a significant reduction in the number of counters. In this case, there is a problem that the speed of writing to the memory is slower than the speed of reading from the memory, but in the case of the present invention, the counter of the line corresponding section that provides the read address to the facsimile terminal is equivalent to the telephone line. It is also conceivable to reduce the difference between the low speed counter and the counter of the common decoding unit that provides the write address by using a high speed counter in accordance with the above-mentioned high speed transmission path.

FIG. 4 is a schematic explanatory diagram of an example of the common decoding section in FIG. 3.

That is, as explained with reference to FIG. 1, a binarized image signal is compressed using a run-length method or the like and stored in a buffer memory (BM) 16 on the receiving side through a high-speed transmission line. This encoded image signal is put into the reception register 42 of the common decoder 15, and the fixed memory (ROM) 41 storing a decoding table is referred to based on the encoded image signal pattern received in the reception register 42. Then, the decoded image signal information is obtained and sent to the plurality of line correspondence units 14, to 14n using the transmission counter 43, and written into the pair of memories mentioned above. That is, the transmission counter 43 corresponds to the counter 35 in FIG. 3, and supplies a write address to a pair of memo files. The transmission counter 43 can share various counters corresponding to each function depending on the configuration of the common decoding section, and for example, a counter for generating a line end signal can be used.

The designation of the plurality of line correspondence units 14, . As explained above, according to the present invention, each line corresponding section is provided with a counter that responds to the image signal from the common decoding section and gives a read address to one of the memories switched to, and the common decoding section A counter is provided for giving a write address to the other memory.

As a result, the number of counters in the line corresponding section is halved, and the counters in the common decoding section can share the decoding counters, which greatly simplifies the configuration and has a significant effect in reducing the size and cost of integrated circuits. 0 Brief Description of the Drawings Fig. 1 is a general explanatory diagram of a facsimile system to which the present invention is applied, Fig. 2 is an explanatory diagram of a conventional example, Fig. 3 is a schematic explanatory diagram of an embodiment of the present invention, and Fig. 4 is a general explanatory diagram of a facsimile system to which the present invention is applied. Third. It is an explanatory diagram of the main parts of the figure, and in the figure, 14, 14, ~ 14M are line corresponding parts, 1
5 is a common code section, 16 is a buffer memory, 21, 23 are memories, 25, 33, 34 are AND circuits, 31, 35 are counters, 41 is a fixed memory, 42 is a reception register, 4
3 is a transmitting unit, and 44 is a line control unit.

Figure 1 Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] 1. Consisting of a plurality of line corresponding sections and a common code section that decodes the received image signal and distributes the decoded image signal to each of the line corresponding sections, and the line corresponding section is provided with a pair of memories for switching. Accordingly, in a facsimile line control device that reads out the contents of the other memory to a facsimile terminal while storing image signals from the common decoding section in one memory, the image signals from the common code section are stored in each line corresponding section. A facsimile machine characterized in that one memory that stores signals is provided with a counter that provides a read address, and the other switched memory of each line corresponding section of the common decoder is provided with a counter that provides a write address. Line control device.