JPS6024507B2 - analog output device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog output device that converts digital output data provided from a host device into analog data and outputs the converted data to a specified output point.

Generally, the analog output device 11 is configured as shown in FIG.
When outputting data to any of the N output points, it outputs digital output data (and address data indicating the data storage destination) to the buffer circuit 14 via the input/output bus 13, and also outputs it to the control unit 15. Start it up. The control unit 15 controls the entire analog output device 11, and first stores the digital output data in the buffer circuit 14 in sequence at the corresponding address positions in the memory 16 indicated by the corresponding address data. The control unit 15 also includes a memory 16.
The digital output data is read and outputted to a digital/analog converter (hereinafter referred to as DAC) 18 via a memory interface 17. The digital output data read from the memory 16 is converted into analog data by the DAC 18 and input to the distributor 19. Distributor 1
9 distributes and outputs this analog data to a designated output circuit among the output circuits 20, to 20N under the control of the control section 15. These output circuits 20, to 20N are composed of a sample/hold circuit and an output buffer circuit (both not shown), and output analog data to corresponding output points. In this example, the output destination of the digital output data (analog conversion data thereof) stored in the memory 6 is uniquely determined by its storage address position. That is, the CPU 12 transfers the address data indicating the address position of the memory 16 corresponding to the output destination of the data (analog conversion data) together with the digital output data to the analog output device 11, so that the data is output via the corresponding output circuit. Analog data is output to a desired output point. By outputting analog data to the output point, for example, the amount of opening and closing of a valve of an external process device is controlled, and the amount of water, etc. is adjusted. In such a conventional analog output device 11, if, for example, the DAC 18 fails, there is a possibility that its output value will be, for example, 1/2 or 1/3 of the true value.

As a result, analog data that does not correspond at all to the digital output data output from the CPU 12 is output to the output point, resulting in the inconvenience that desired control operations etc. cannot be performed correctly. In order to eliminate such inconvenience, DAC18
A possible method is to use a double thread for the subsequent hardware configuration, use one system under normal conditions, and switch to the other system in the event of an abnormality such as a failure. However, this method has problems because the output is interrupted during switching, leading to malfunctions. Furthermore, unlike a digital output system, it is difficult to detect an abnormality in an analog output system, so there is a risk that switching may not always be performed correctly. The present invention has been made in view of the above circumstances, and its purpose is to minimize the influence on the analog output data value in the event of a circuit failure in the analog output system of a digital/analog converter, while having an extremely simple configuration. The object of the present invention is to provide an analog output device that can perform the following functions.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

Note that the same parts as in FIG. 1 are given the same reference numerals and detailed explanations are omitted. In the analog output device 111 shown in FIG. 2, 115 is a control section. The control unit 115 has almost the same function as the control unit 15 shown in FIG.
It has a function of detecting an abnormality according to the comparison result of 50 to 150N and notifying the CPU 12 of the abnormality. 11
8,,1 182 is D similar to DAC1 8 in Figure 1.
AC, and the memory 1 is connected to the memory 1 through the memory interface 17.
6 and converts the commonly given digital output data into analog data.

119, 1192 are distributors similar to the distributor 19 in FIG. .

130,. -130, N, 132, and -130 are sample and hold circuits (hereinafter referred to as SH) for the corresponding distribution outputs from the distributors 119, 1192, respectively.

In this embodiment, when the analog data given from the corresponding DACIs 181, 1182 is for the output point P, the distributors 1 19, . , 1302, and if it is for output point P2, output the data to SH1308, 13022, ...output point PN
If the data is for SH130, N,
1302N. 1401-1
40N is an output circuit provided corresponding to each output point P, to PN.

The output circuits 140 and 140N are adders 141 and 140N, respectively.
141N and 1/2 circuits 1421 to 142N. Adders 141, . . . , 141N are connected to SH130, . ,130a~SH130,N,130
adds two pieces of analog data outputted from each other, and outputs the addition result to the corresponding 1/2 circuits 142, to 142N. The 1/2 circuits 142, ~142N have a function of halving the input analog data and an output buffer function, and halves the addition outputs of the adders 141, ~141N to the corresponding output points P, ~ Output to PN.

150, to 150N are SH130, . ,130
2, ~SH130,N, 2 output from 1302N
This is a comparator that compares analog data.

The comparators 150 and 150N output logic "1" depending on whether or not there is a difference of more than a predetermined value between the two input analog data.
A binary signal of "" or "0" is output to the control section 115. Next, the operation of the configuration shown in FIG. 2 will be explained.

For example, now, the control unit 115 reads out digital output data for the output point P from the memory 16, and outputs the digital output data to the DACI 18, .
1182 is commonly output. DACI 1
8,, 1 1 82 convert this digital output data into analog data V,, V2, respectively, and output it to the corresponding distributors 119, , 1192. Distributor 119,1
192 transmits the analog data V, , V2 to the control unit 11
5 under the control of SH130, . ,1302,
Output to. However, SH130,. , 1302, and the analog data V, , V2 sampled and held are input to the adder 141 of the output circuit 140. The adder 141 adds these analog data V, , V2 to obtain analog data V, V2. This analog data V·10V2 is halved by a 1/2 circuit 142 and output as analog data (V,10V2)/2.
Now, if the analog output circuit such as DACI 18,, 1 182 is normal, the analog data V,, V
2 are the same value, that is, V, = V2 = V, and therefore the analog data (V, 10V) output to the output point P,
2) The value of /2 is (V, 10V2)/2=VT. That is, the correct analog converted value of the digital output data that should be analog-converted and output to the output point P is output to the output point P. On the other hand, one of the analog output system circuits, for example, DACI 1 to 8, fails, and the analog data V, becomes 1/2 of the true value, that is, V, = (1'2) VT.
Assuming that, the value of analog data (V, 10V2)/2 output to output point P is (V, 10V2)/2
= (1/2 + 1) VT/2 = (3/4) VT. As is clear, in the conventional analog output device as shown in FIG. 1, when the analog conversion value becomes the true value 1'2, this erroneous analog conversion value is output as is. However, in this embodiment, even if the purchase price is 1/2 in one system, the erroneous analog conversion value is not output as is as described above, but is corrected to analog output data that is 3/4 of the true value. Therefore, compared to the conventional example, the negative influence on the output point (external process) is alleviated. On the other hand, SH13
0,. , 1302, and the analog data V, , V2 sampled and held are input to the comparator 150.

The comparator 150 compares these analog data V, , V2 to see if there is a difference of more than a predetermined value, and as mentioned above, when the analog data V, becomes the true value 1'2, A binary signal of logic “1” is output to the control unit 115. The control unit 115 detects an abnormality based on a binary signal of logic “1” from the comparator 150, and outputs the signal to the CPU via the input/output path 13.
12 to notify the circuit abnormality of the analog output system. As a result, the CPU 12 performs corresponding abnormality processing, notifies the operator at an appropriate time, and urges the operator to check or replace the circuit of the corresponding analog output system. In the above embodiment, the DACI 18, the distributor 119, and the SH 130
、． ~130,N etc. analog output system and DACI18
Although a case has been described in which a dual system configuration with analog output systems such as the two-way divider 119 and the SH 130 to 1302N is used, a triple system configuration may be used, for example. In this case,
It is necessary to provide a 1/3 circuit in place of the 1/2 circuit in the output circuit, which reduces the input value to 1/3 and outputs it. In an analog output device with a triple system configuration, if an abnormality occurs in one analog output system as described above, the analog converted value will be 1/1/2 of the true value.
2, the analog data output to the output point is (
1'2 1 1) VT/3 = (5/6) VT, 2
In the case of a heavy system configuration, the value becomes even closer to the true value. In other words, the influence on the output value due to abnormalities such as failures in the analog output system is significantly reduced, and correct operation in the external process is guaranteed. As is obvious, it is possible to further configure the analog output system into a quadruple system, a quintuple system, etc., and the configuration will depend on the error tolerance required in the external process, etc. It is a matter of deciding accordingly. As described in detail above, according to the analog output device of the present invention, even if a circuit failure occurs in the analog output system, the influence on the analog output data value can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional analog output device, and FIG. 2 is a block diagram showing an embodiment of the analog output device of the present invention. 11, 111...Analog output device, 12...CPU,
15, 115...control unit, 16...memory, 18,
118,,1182...Digital/analog converter (DA
C), 19, 119,, 1 192...distributor, 21
, ~20N, 140, ~140N output circuit, 141, ~
141N...Adder, 142,~142N...1/Kodanro. Figure 1 Figure 11 Ship

Claims (1)

[Claims]1.
An analog converter is provided corresponding to each of the N output points, and M pieces of analog data output from the corresponding digital/analog converter are added, and this addition result is set as 1/M to the corresponding output point. The N output circuits that output to the N output circuits and the M digital/analog converters are respectively provided, and the analog data converted and output from the corresponding digital/analog converters is commonly specified from the host device. An analog output device characterized by comprising: M distributors that distribute output to the output circuit side and are provided corresponding to the output points of the output circuit. 2. Input analog data common to the M analog data input to the output circuit and compare whether or not there is a difference of more than a predetermined value between these M analog data.
2. The analog output device according to claim 1, wherein the analog output device is provided with two comparison circuits and notifies a host device of an abnormality when a difference of more than a predetermined value occurs.