JPS60244114A - Phase dividing circuit - Google Patents

Abstract

PURPOSE:To obtain signals with multi-division of a phase with a simple constitution by using a pair of analog multipliers and combining the signals of these multipliers to supply these combined signals to plural comparators. CONSTITUTION:Alternating signals Vx and Vy having a 90 deg. difference in phases are applied to input terminals 1 and 2. These input signals are supplied to analog arithmetic circuits 3 and 4 through pairs of differential input terminals IN1<+>, and IN1<->; IN2<+> and IN2<->, IN3<+> and IN3<-> and IN4 <+> and IN4<-> respectively. Then operations are carried out as shown by the equations, and the signals are extracted through output terminals V01<+> and V01<-> as well as V02<+> and V02<->. Here K1 and K2 show the gain respectively. These outputs are supplied in combinations to comparators 5 and 6-8. Then the signals obtained by dividing the phase of the input signal are delivered through terminals O1-O4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a phase splitting circuit that receives two signals output from a rotary encoder, for example, and which have a phase difference of 90 degrees from each other, and obtains a phase split signal. .

(Prior Art) FIG. 5 is a block diagram showing an example of a conventional phase division circuit of this type. This circuit receives signals yx and v with a phase difference of 90'' from a rotary encoder (not shown).
Input terminals 1 and 2 to which y is applied, resistors R1 and R2 connected between these input terminals 1 and 2, and input terminal 2 with a gain of -1
amplifier (resistors R3 and R4 connected between the output terminals of inverter lA3, the connection point of each resistor R1 and R2, and the amplifier A1. A2, comparators C1 to C8, and output terminals 01 to 08 connected to the output terminals of each comparator and sequentially outputting divided pulse signals.

In a conventional circuit with such a connection, a signal S1 obtained on the line connected to the input terminal 1°, a signal S2 obtained on the output terminal of the amplifier A1, a signal S3 obtained on the line connected to the input terminal 2, The signal S4 and the amplifier I! obtained at the output of amplifier A2! ] The signals S5 obtained at the output terminal of the device A6 are signals having a phase shift of 45° from each other, as shown in FIG. 6(a).

The comparator C1 compares the signal S1 with the zero level signal and outputs a rectangular wave signal to the output terminal 01 as shown in (v). Furthermore, the conoparator C2 compares the signal S1 and the signal S2, and outputs a rectangular wave signal as shown in (c) to the output terminal 02. Thereafter, in the same manner, comparator C3 C (g), comparator C4H (e),
Comparator C3fd(+') and comparator C6 are (
comparator C7 is), comparator C8 is (
Signals as shown in Fig. 1 are output to output terminals 03 to o8, respectively.

Therefore, if the rise and fall of the rectangular wave signals obtained from each output terminal 01 to 08 are detected and the pulses shown in (◯) are output, this pulse will be output every 22.5 degrees. This results in a phase-divided signal divided into 16.

Conventional circuits with such a configuration have the disadvantage that a large number of various amplifiers are required, making the overall configuration complex.

(Object of the present invention) The present invention has been made in view of the above-mentioned drawbacks of conventional circuits, and aims to realize a phase division circuit that can obtain multi-divided signals with a simple configuration. .

(Summary of the present invention) A circuit according to the present invention includes two sets of analog multipliers, and two sets of analog multipliers.
and a plurality of comparators inputting a combination of signals from a set of analog multipliers.

(Embodiment) FIG. 1 is a configuration block diagram showing an example of a circuit according to the present invention. In this figure, 1 and 2 are input terminals to which alternating signals vx and vy having a phase difference of 90 degrees are applied, and 6.4 are two sets of differential input terminals INI, respectively.
lNl− and lN2+, lN2, lN3+, l
This is a first and second analog multiplier circuit having a pair of differential output terminals Vo1''+Vo1- and Vo2'', Vo2-.
The analog calculation circuits 6 and 4 perform calculations as expressed by equations (1) to (4) on signals applied to each input terminal, and output the results to each output terminal. In addition, in each formula,
It is assumed that the symbol representing each terminal directly indicates the magnitude of the signal at that point.

Vol =,,i ((INl −INI )X(IN
2-lN2) )XKt "'・'(2)yo2":
= '((lN3 lN3)X(I,N4 1N4
1)XKt"""(3)Vo2- = '((lN
3 lN3 )X(lN4 lN4 ) )XKt ・
``''<4) However, K, ... Gains 5 to 8 are comparators each having a pair of input terminals. Output terminals 01 to 04 of each of these comparators 5 to 8 pass through an edge detection circuit (not shown) and are applied to, for example, a clock input of a counter.

Positive phase input terminal INI of the first analog multiplier 6.

Input signals vx and vy are applied to the input terminals INI and IN2, respectively, and the negative phase input terminals INI and IN2- are grounded, respectively. Further, one positive phase input terminal IN4 of the second analog multiplier 4 is connected to the input signal vX1 and the negative phase input terminal lN.
The input signal vy is applied to 4-.

Further, the other positive phase input terminal IN3 receives the input signal VX.

Signal (VX+VY) obtained by dividing yy with resistors R5 and R6/
2 is applied, and the negative phase input terminal lN3- is grounded.

Here, the alternating human power signals applied to the input terminals 1 and 2 are expressed by equations (5) and (6), respectively, and their waveforms are shown in Figure 2 (a).

■X = bunch ωt ・・・・・・・・・・・・・・・・・・
(5)vY=Yuωt・・・・・・・・・・・・・・・
... (6) Also, 1st. The gain of the second analog multiplier 6 is set to 1.4 and 2 to 2.

In this case, one output terminal Vo of the first analog multiplier 6
l+ and the other output terminal Vol- are determined as shown in equations (7) and (8).

vo1+=knee ωt 1yughx2ωt ・・・−・・・・・・・・・・・・・・・
...(7) Vol = -1(cosωt -5
ln(d t 12 =--il, tn2ωt ・・・・・・・・・・・・
(8) Also, one output terminal Vo2+ and the other output terminal Vo2- of the second analog multiplier 4 are (
9) Equation is as shown in the aO equation.

Vo2"'-(cfMalt-salt)X"""
""",
・・・・・・(9) Vo2=-i Minoh2ωt ・・・・・・−
・・・・・・・・・・・・αO(7) formula ~ocI
The waveforms of each signal expressed by the equations are shown in FIG. 2 (b). As is clear from this waveform diagram, the first. Each signal obtained from the output of the second analog multiplier 6.4 has a period of Y with respect to the input signals vx, vy, respectively,
They are different in phase by 90° from each other.

The comparator 5 inputs the output signals Vo1'' and Vol- from the first analog multiplier 6 and compares both signals. A rectangular wave signal as shown in FIG. 2 (C) whose output is inverted every time sm2ωt is outputted to the output terminal 01.

The comparator 6 inputs the output signal Vo1 from the first analog multiplier 6 and the output signal Vo2 from the second analog multiplier 4, and compares both signals. A rectangular wave signal as shown in FIG.

The comparator outputs the output signal Vo2. from the second analog multiplier 4. Vo2 is input, both signals are compared, and a rectangular wave signal as shown in FIG. .

Similarly, the comparator 8 inputs the output signal vo1 from the first analog multiplier 6 and the output signal Vo2- from the second analog multiplier 4, compares both signals, and calculates 1sin2ωt=-1- The output is inverted every time 2ωt 2 as shown in Fig. 2. A rectangular wave signal is output from the output terminal 04.

Here, each output terminal 01 to 04 of each comparator 5 to 8
As is clear from Figure 2 (c) to (f), the rectangular wave signals from .

'' Therefore, if each signal from the output terminals 01 to 04 is obtained via an edge detection circuit (not shown), the result as shown in FIG. 2 (
As shown in (g), it is possible to obtain a phase-divided signal divided into 16, in which a pulse is output every 22.5 degrees for the phase of the input signals yx and yy.

In the above description, the input signals are 7 and yy are sine waves, but the circuit according to the present invention may also use an alternating signal that is not a sine wave as the input signal.

In this case, the gain of the first and second analog multipliers, 4, needs to be set to a gain other than 1.

Regarding this point, the case where the input signals vx and vy are triangular wave signals having the same period and having a phase difference of 90'' as shown in FIG. 6 will be explained.

In Figure 6, O', 90, 180''', 27
Detection of 0° and 45°, 165', 225',
Detection of 315″' is performed as in the case where the input signals VX and VY are sine waves, as shown in FIG.
This is accomplished by the operation X2 y y2 ==Q. To detect points other than this, first, see Figure 6 (a) Yoshi, 2.
At 2,5°, 2 [12,5°, vx = 5 - VY, and at 1'2.5°, 292.5°, v
x=-icy. Therefore, at each point, (■X 3 V Y) (V ” + B V Yl
20 is established.

That is, (vx2-vy2)-vx-v't=0.

Here, in the circuit of FIG. 1, the second analog multiplier 4
When the gain of
X2-MY2) Get it, Part i 0. ) 7. If the gain of the multiplier 6 is 476, the positive phase output terminal Vo1 has a null value of 2/3 VX-VY.

Comparing these two outputs using comparator 6, we find that
The point where x'-VY2)-2VX・■Y 6, phase 22.5', 112.5°, 20, which corresponds to the point surrounded by 0 in half 6 diagram (o)
2.5°.

Each point of 292.5° can be detected.

From Figure 6, at 67.5° and 247.5°, the value of strange X = vY, and at 15Z5° and 337.5°, y
x=-3VY.

The negative phase output terminal Vo2- is '(''X-v2y)tona;b.

Comparator 8 outputs these two output signals yo1+Vo2
When we detect a point where 3VYl is equal, at that point, 3VYl
(VX-, VY) = 0.

Therefore, in FIG. 6(b), the phases corresponding to the points surrounded by Δ are 67.5°, 247.5°, 157.5',
Each point at an angle of 337.5° can be detected.

As described above, in the circuit of FIG. 1, by setting the gain of the analog multiplier 6 of FIG. 1 to 4/6, the input signal vx
Even if , vy are triangular wave signals, a signal whose phase is divided into 16 can be obtained.

Generalizing the above, 0°, 90°, 180@.

At 270', vx = ot or yy = 0, and at 45°, 165°, 225°, 615°,
vx=±yy holds, and 22.5°, 67.56°, 112.5°, 157.5°, 202.5°, 247.
5″', 292.5°.

At vY 337-5°, (Vxf:A −VY l (
If VX+T-)=0 holds true, by setting the gain of the first analog multiplier 6 to 0, it is possible to obtain divided signals in which the phases of the input signals yx and yy are divided into 16. Note that if vx and yy are sine waves, A=1
+vlar, in the case of hexagonal wave, A=3.

The signal waveform satisfying such conditions is not limited to a sine wave or a triangular wave, but may be a periodic wave signal having a symmetrical waveform with vX as an axis of Oo and MY as an axis of 90'. .

FIG. 4 is a block diagram showing a 44cv embodiment of the present invention. In this embodiment, four analog multipliers 6, 4 and 3a, 4a are used to form a two-stage circuit configuration.

That is, in implementation v1 of FIG. 1, the output signals of the two analog multipliers 6.4 are twice the frequency of the input signals vx, vy and are 90° out of phase with each other. In this embodiment, two analog multipliers 6, 4
The output of yx is applied as a new input signal to the next-stage I analog multipliers 3a and 4a. According to such a configuration, the input signal yx.

For vY, a divided signal can be obtained by dividing the phase by 62.

Similarly, by using analog multipliers in 6 stages, 4 stages, etc., it is also possible to divide the signal into 64, 128, and so on.

(Effects of the Present Invention) As described above, according to the present invention, it is possible to realize a phase division circuit that can obtain a signal obtained by multiply dividing the phase of an input signal with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram showing an example of a circuit according to the present invention, FIG. 2 is an operational waveform diagram thereof, FIG. 6 is an operational waveform diagram when the input signal is a triangular wave signal train, and FIG. 4 is a diagram of the present invention. FIG. 5 is a block diagram showing an example of a conventional circuit, and FIG. 6 is an operating waveform diagram thereof. 1.2...input terminal, 6,4...analog multiplier,
5-8...Comparators, 01-04...Output terminals. Representative Patent Attorney Sanro KimuraFigure 3Figure 4Figure 5

Claims (1)

[Claims] (1) A pair of input terminals to which two alternating human input signals (UX, yy) whose half-cycle waveforms are symmetrical with a 174-cycle axis of symmetry and whose phases differ by 90 degrees from each other are applied; at least two sets of analog multipliers each receiving two alternating human power signals respectively applied to the two alternating human power signals, a composite signal created by a combination of these two alternating human power signals, and a ground signal; a plurality of comparators inputting a combination of output signals of the above, and obtains a signal obtained by dividing the phase of the two alternating human power signals from the output terminal of each of the comparators.