JPS60241142A - Monitor for program running route - Google Patents

Abstract

PURPOSE:To monitor the unrun area of a program by writing the level ''1'' previously to a memory and the level ''0'' to the memory at the rear edge of the execution bus cycle of a microprocessor. CONSTITUTION:A memory 5 is reset and receives an access from a microprocessor mup2 in a running monitor mode of the mup2 by selecting the A side input through multiplexers 4 and 7. Then the contents of a memory corresponding to the address executed by the mup2 are set at ''0''. When the running monitor is through, the multiplexers 4 and 7 select the B side input. Thus the memory contents can be read out by a control circuit 10. The contents of the memory 5 read out in such a way are monitored to confirm the run address (contents: ''0'') and the unrun address (contents: ''1'') of the mup2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a monitor that monitors a program running path in a logic analyzer or the like, and particularly relates to the realization of a monitor that can determine whether or not there are untraveled portions in a program. .

[Conventional technique vF1] Conventionally, logic analyzers have been able to display the analysis results on a display device, and in addition to displaying the state and timing, it has also been possible to display the operating status of the microprocessor (hereinafter referred to as μP). Then, focus on the address information, perform a surge pull, and check the movement of the address information in X-Y.
Specify by axis (for example, divide the address bit into two, and the X-axis is the address axis represented by its upper bits, and the Y-axis is the address axis represented by its lower bits. Neither axis is a time axis.) There is a method of displaying the trace T on the display screen DSP as shown in FIG.

However, in such a method, regarding the path of μP,
Although it had the advantage of being able to recognize patterns, it had the disadvantage that it was extremely difficult to determine whether there were unrun portions of the program.

[Object of the Invention] The object of the present invention is to eliminate such drawbacks, and to provide a program running route monitoring system that can monitor unrun portions of a program with a simple configuration and is expected to improve the efficiency of program debugging. The purpose is to provide a monitor.

[Summary of the Invention] In order to achieve such an object, the present invention includes an address selection means for inputting an address from a microprocessor system under test and a memory read address and selecting one of them; a memory accessed at an address of , and means for writing a "1" level into the memory in advance to set it in a reset state and writing 1101 level into the memory at the trailing edge of an execution bus cycle of the microprocessor of the microprocessor system under test. The present invention is characterized in that a running portion and a non-running portion of the microprocessor can be detected based on the contents of the memory.

[Example] The present invention will be described in detail below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In the figure, 1 is a μP system under test incorporating a microprocessor 2, 3 is an address bus, 4 is an address multiplexer, 5 is a memory,
6 is a gate, 7 is a control signal multiplexer, 8 is a switch, and 10 is a control circuit.

The address multiplexer 4 is an address selection means that takes the address from μP 2 as one input, takes the externally specified read address as the other input, and selects and outputs one of the inputs.

The memory 5 is a memory in which data can be written or read in accordance with the read/write signal WR, and when the write signal instructs to write the WR multiplied signal, the switch 8 applies "" to the address specified by the address multiplexer 4. Data of 1" or "0°" is written, and when the read signal instructs to read the WR multiplied signal, the address specified by the address multiplexer 4 is read out.

The WR multiplier signal is output from the multiplexer 7 for the control signal, and this multiplexer 7 receives the output of the gate 6 that takes the logical sum of the memory read or memory write signals of μP2, or the reset level write signal given from the outside. Select one of them and output it as a WR multiplied signal.

The control circuit 10 outputs control signals for controlling the operations of the multiplexer 4.7 and the switches based on commands from the outside.

The operation in such a configuration will be explained next.

■First, reset memory 5.

Under the control of the control circuit 1'O, the multiplexer 4 is set to select the address of the bus 9, and the multiplexer 7 is set to select the reset level write signal. Signal ゛1 selected by switch 8 to all addresses in
” to reset the memory.

■While the running of μP is being monitored, the memory 5 is accessed by μP2 by selecting A inputs as shown in the diagram at multiplexer 4゜7, and the memory contents corresponding to the address executed by μP2 become '0°゛. .

(2) When the running monitor is finished, the memory contents can be read out by the control circuit 10 by selecting B inputs as shown in the figure at the multiplexer 4.7.

By monitoring the contents of the memory 5 read out in this way, it is possible to determine whether the μP running address (content is “'0”)
) and the unused address (content is 11111).

Also, read memory 1 in a pre-given address range.
By calculating the ratio of the area of ilZ1 "0", the untraveled route portion can be clearly identified.

Also, based on the information of ii 1 u, "0'', only the untraveled route portion can be extracted and clearly displayed.

Note that an address converter may be provided to compress the bit width of the address given by μP2, and its output may be input to the address multiplexer 4.

The address given by μP2 is usually 20 to 24 bits wide, but the address converter converts it to the bit width allowed by the debug program (usually 16 to 20 bits wide).
Compress it into Thereby, the memory 5 can be constructed economically.

[Effects of the Invention] As explained above, according to the present invention, it is possible to easily find unrun portions and running portions of a μP program, and an improvement in program debugging efficiency can be expected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining a conventional trace display. DESCRIPTION OF SYMBOLS 1... μP system under test, 2... Microprocessor, 3... Address bus, 4... Address multiplexer, 5... Memory, 6... Gate, 7...
・Control signal multiplexer, 8...switch, 1o
...Control circuit.

Claims (1)

[Claims] (1) Address selection means that receives an address from the microprocessor system under test and a memory read address and selects one of them, a memory that is accessed by the address from this address selection means, and a means for setting the I II level to a write reset state and writing a ``0'' level to the memory at the trailing edge of an execution bus cycle of the microprocessor of the microprocessor system under test; A program travel route monitoring monitor characterized by being able to detect running portions and non-running portions of a processor. 2. The program execution path monitoring monitor according to claim 1, wherein the address selection means marked # comprises an address converter for compressing addresses from the microprocessor system under test.