JPS60241130A - Microprocessor - Google Patents

Abstract

PURPOSE:To improve the efficiency with execution of a logical operation by using the logical units of each bit and arithmetic operation units of plural bits and setting exclusive data buses to those units respectively. CONSTITUTION:A microprocessor contains the 1st and 2nd data buses 11 and 12. Then a logical unit 13 which executes the logical operations for each bit is connected to the bus 11; while an arithmetic operation unit 14 connected to the bus 12 respectively. In addition, an input/output port 15 and a data memory 16 are connected between both buses 11 and 12 in a common state. A program counter 18 is actuated by the signal of a clock generating circuit 17. Thus the address of a program memory 19 is designated. The output data of the memory 19 is decoded by an instruction decoder 20, and the units 13 and 14 are connected selectively to the buses 11 and 12 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a microprocessor that allows not only logical operations but also mathematical arithmetic operations to be effectively executed by a simple program.

[Background Art of the Invention] For example, in a microprocessor equipped with an 8-bit data bus, in order to execute logical operations between bits, bit shift instructions must be used frequently to proceed with the operations. Therefore, very inefficient arithmetic operations must be performed.

For example, the input boat P1 includes P10 to p17,
The following is a program that uses a Motorola microprocessor MC6801 equipped with P30 to P37 as the output boat P3 to perform a bitwise AND operation on the input boat β10 and pH, and outputs the result to the output boat P32. Become.

L D A A 'PI 0LA ANDA PI 0LA ANDA #804 STAA MEMORY LDAA P3 ANDA #$FB ORA MEMORY STAA P3 Here, the value shown as MEMORY is the MC6 above.
801 represents an arbitrary address of the RAM that can be accessed. In other words, in this example, 10 steps are required to perform a very simple logical operation.

In order to efficiently execute such logical operations on a bit-by-bit basis, for example, the 1PIT microprocessor MC14500 manufactured by Motorola Corporation can be effectively used. However, when such a one-bit microprocessor is used to perform operations on a plurality of bits, such as a counting operation, the efficiency is extremely low. In other words, if a 6-stage counter circuit is to be implemented using such a 1-bit microprocessor, a 9-step program is required for each stage of the counter, and an additional 5 steps are required for the clock. Become. Therefore, a total of 59 steps are required. That is, if each instruction is considered as one word, it will consume 59 words of program memory, and 13 bits will be consumed as data memory.

[Purpose of the Invention] The present invention has been made in view of the above points. For example, it is possible to efficiently execute logical operations in units of bits, and also to effectively execute arithmetic operations using multiple bits. , it is an object of the present invention to provide a microprocessor that can be effectively used in various control devices.

[Summary of the Invention] In other words, the microprocessor according to the present invention mainly includes a logic unit that executes bit-wise logical operations and an arithmetic operation unit 1- that executes multi-bit arithmetic operations.
and a dedicated data bus is set for each of these units.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows its configuration, and this microprocessor is provided with first and second data buses 11 and 12. The first data bus 11 is a data bus with a 1-bit configuration, and a logic unit 13 (Logic Unit-LLJ) that executes logical operations in bit units is connected to the first data bus 11. has been done.

Further, the second data bus 12 is composed of a plurality of bits, for example, 8 bits.
For example, an arithmetic operation unit 14 (,7N/% rlt
hmetic Unit-AU) is connected.

Such first and second data buses 11 and 12
, the input/output h-board 15 is connected and the data memory 16 is connected in a common state.

A program counter 18 is operated by the system clock signal generated by the clock generation circuit 11, and the address of the program memory 19 is designated by the count output of the counter 18. This addressed program memory 19 outputs data corresponding to that address, and this output data is decoded by the instruction decoder 20.

This instruction decoder 20 supplies an instruction output to the first data bus 11 or the second data bus 12, and the instruction decoded by the instruction decoder 20 is a logical operation instruction in bit units. , if the instruction is executable in the logic unit 13, the first data bus 11 is selected and the logic unit 13
, further accesses the input/output board 15 and data memory 16. Then, a predetermined bit-by-bit logical operation is executed.

Further, when the instruction decoded by the instruction decoder 20 is an arithmetic operation instruction for multiple bits (for example, an INCA instruction), the second data bus 1 having a multiple bit configuration is
2 is selected, the arithmetic operation unit 14, the output port 15 and the data memory 16 are accessed.

For example, in the instruction system of the microprocessor MCI4500 mentioned above, if the above-mentioned bit-wise logical operation example is expressed in 10 grams, it will be as follows.

LD PIG AND pH STOP32 In addition, the 8-bit input data of the byte-based input port P1 is regarded as a numerical value, and the data value is incremented by 1 and output to the byte-based output port P3. If the program is programmed using the instruction system of the MC6801, the result will be as follows.

LADD Pi NCA STAA P3 In other words, a logic unit 13 that mainly executes bit-wise logic operations, a logic operation program using the first data bus 11 connected to this unit 13, and a multi-hit configuration program. a fraud calculation unit 14 that mainly executes data calculations, and this unit 14;
The above arithmetic operation program using a second data bus with a multi-bit configuration connected to and set to can be executed within one microprocessor, effectively improving data processing efficiency. It is something that will come to be done.

FIG. 2 is a more detailed block diagram showing the counter circuit in the microprocessor configured as described above. In this case, the internal counter 141, which is part of the arithmetic operation unit 14, is used. be done. In this microprocessor, a data memory 16 composed of RAM,
The result register 21, logic unit 13, input/output board 15, etc. exchange data via a 1-bit data bus 11. In order to roughly execute a group of count-only instructions, the internal counter 141 coupled to the data memory 16 and the result register 21 is connected via a second data bus 12 different from the data bus 11. The exchange of data is carried out via the data bus 12. In particular, between the data memory 1G and the internal counter 141, for example, 8-bit data is exchanged in batches.

Next, to explain the operating state of the above-mentioned count-only instruction group, first, reset data R, 6-bit data D1 to D6, and the immediately preceding clock C' are stored in parallel in the data memory 16, and the result The register 21 stores the clock C.

A) First, as shown in FIG. 3(A), execute a counter load instruction (hereinafter this instruction will be referred to as TMC=Trans
fer Memory to Counter).

When this instruction is executed, the value of the result register 21 is set as the C signal (clock signal) of the internal counter 141, and the 8 bits in the data memory 16 are set as the R signal (reset signal),
The data is loaded into the internal counter 141 as the preset data signal D1 to D6 (preset data signal) and the C signal immediately before the C' multiplied signal).

B) Next, as shown in (Bit) in FIG. 3, a count operation instruction (hereinafter this instruction will be referred to as CN Counting is performed according to the truth table shown in the figure.

C) Count store instruction (hereinafter this instruction will be referred to as TCM =
Transfer C0tlntClr to M
ellOrV). This instruction stores the data in the internal counter 141 in the data memory 16 and result register 21, contrary to the 7MC instruction. In this case, the output of the final stage of the counter 141 is also returned to the result register 21, thereby facilitating cascade connection of the counters.

Here, in the program memory 19, the address is updated for each instruction.

In addition, in the example shown here, the count-dedicated instruction group is TMC,
Although shown as being divided into CNT and TCM instructions, it goes without saying that the above three steps may be executed in one instruction.

The internal counter 141 also does not need to be 6 bits.

Further, in the above embodiment, the first data bus 11 having a 1-bit configuration and the second data bus 12 having a multiple-bit configuration are used.
Although this is shown as one type of data bus configuration, this can be further expanded to a plurality of data bus configurations as is. For example, the first data bus is configured to have a 1-bit configuration so that bit-by-bit logical operations can be executed, and the second data bus is configured to have an 8-bit configuration so that simple integer operations can be executed. And, the third part which is further expanded.
The data bus has a 32-bit configuration so that complex numerical operations can be executed.

[Effects of the Invention] As described above, according to the present invention, for example, a second data bus having a plurality of bits is added to the first data bus having a one-bit configuration.
data buses are set up, and logic units and arithmetic operation units are connected to these data buses, respectively. These units selectively execute 1-bit logical operations, rough counter operations, and arithmetic operations, and these operations can be controlled effectively by a simple program. , which can be easily applied to various control calculation systems.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram illustrating a microprocessor according to an embodiment of the present invention, and FIG. 2 is a more detailed configuration diagram illustrating a case in which the microprocessor shown in the above embodiment executes a counter operation. , (A) to (C) in Figure 3
) are diagrams showing the states of the internal counter and data memory to explain the states of the counter operations, respectively, and FIG. 4 is a diagram similarly showing a truth table. DESCRIPTION OF SYMBOLS 11... First data bus, 12... Second data bus, 13... Logic unit, 14... Arithmetic operation unit, 15... Input/output port, 16... Data memory, 19...Program memory, 20... Instruction decoder. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] A logic unit that mainly performs bit-wise logical operations, a first data bus that is connected to this logic unit, an arithmetic operation unit that mainly performs multi-bit arithmetic operations, and a first data bus that is connected to this logic unit; A microprocessor comprising: a second data bus connected to the second data bus;