JPS6024050A - Manufacture of thin film element - Google Patents

Manufacture of thin film element

Info

Publication number
JPS6024050A
JPS6024050A JP13161583A JP13161583A JPS6024050A JP S6024050 A JPS6024050 A JP S6024050A JP 13161583 A JP13161583 A JP 13161583A JP 13161583 A JP13161583 A JP 13161583A JP S6024050 A JPS6024050 A JP S6024050A
Authority
JP
Japan
Prior art keywords
film
thin film
side wall
aperture
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13161583A
Other languages
Japanese (ja)
Other versions
JPH0454981B2 (en
Inventor
Nobuo Toyokura
豊蔵 信夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13161583A priority Critical patent/JPS6024050A/en
Publication of JPS6024050A publication Critical patent/JPS6024050A/en
Publication of JPH0454981B2 publication Critical patent/JPH0454981B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To obtain the titled element of high reliability with good yield by a method wherein only the side wall surface of a stepwise difference is provided with a film having a smaller specific resistance than that of said element, when the element is formed on a substrate having the stepwise difference and thus made as an IC. CONSTITUTION:An insulation layer 2 is adhered to the surface of the semiconductor substrate 1, an aperture 5 being bored, and a metallic layer 3 of Mo or the like being then adhered to its bottom, side wall, and the surface of the substrate 1 to the same thickness by a pressure reduction CVD method. Next, the layer 6 is etched in a vertical direction by reactive plasma etching using Cl2 gas, thereby making the layer remain only at the side wall of the aperture 5, and removing the other. Thereafter, an SiO thermet film 7 containing Cr the thin film element is evaporated over the entire surface including the aperture 5, and then the film 7 is formed into a required shape by a photo processing method. Next, an electrode 8 contacting the film 2 is mounted on one end of this film 7, and the latter film including the electrode is surrounded with a PSG film 4. In such a manner, the thin film element of uniform electric characteristics is obtained by reduction of the resistance component of the following part without providing the film 2 on the side surface of the aperture 5 with inclination.

Description

【発明の詳細な説明】 (a1発明の技術分野 本発明は、基板上に薄膜から成る回路素子を形成する方
法に係り、とくに段差が存在する基板上に安定でありか
つ所定の電気的特性を有する薄膜素子を形成する方法に
関する。
Detailed Description of the Invention (a1 Technical Field of the Invention) The present invention relates to a method for forming a circuit element made of a thin film on a substrate, and in particular to a method for forming a circuit element made of a thin film on a substrate, in particular a method for forming a circuit element made of a thin film on a substrate having steps, and in particular, a method for forming a circuit element made of a thin film on a substrate with stable and predetermined electrical characteristics. The present invention relates to a method of forming a thin film device having the following.

(bl技術の背景 半導体集積回路における薄膜素子の代表的用例としては
、該半導体集積回路を構成する多数の半導体素子間を所
定の抵抗値で接続するための抵抗素子、あるいは一部の
不要な素子を電気的に切り離すための溶融切断素子が挙
げられる。
(Background of BL technology Typical examples of thin film elements in semiconductor integrated circuits include resistive elements for connecting a large number of semiconductor elements that make up the semiconductor integrated circuit with a predetermined resistance value, or some unnecessary elements. Examples include a fusion cutting element for electrically disconnecting.

(C1従来技術と則題点 半導体集積回路における該薄膜素子の構成概要を第1図
に示す。同図において、多数の回路素子が形成されてい
る基板半導体1上には、例えば二酸化シリコン(Si0
2)から成る絶縁N2が形成されている。該絶縁層2の
一部には開口部(コンタクトホール)が設けられており
、薄膜素子3は該開口部においてその一端が半導体回路
素子の所定の端子と接続され、その他端は絶縁層2の上
を這って、例えば別の開口部(図示省略)に伸びそこで
他の半導体素子の所定の端子に接続されるとか、あるい
は外部引出し用の電極に接続される。通電、該薄膜素子
3が形成されたのち該薄膜素子3および絶縁N2の表面
には保護膜4が設けられる。
(C1 Prior Art and Problems) An outline of the structure of the thin film element in a semiconductor integrated circuit is shown in FIG.
2) is formed. An opening (contact hole) is provided in a part of the insulating layer 2, and one end of the thin film element 3 is connected to a predetermined terminal of the semiconductor circuit element in the opening, and the other end is connected to a predetermined terminal of the semiconductor circuit element in the opening. For example, it extends to another opening (not shown) and is connected there to a predetermined terminal of another semiconductor element, or to an electrode for external extraction. After energization and formation of the thin film element 3, a protective film 4 is provided on the surfaces of the thin film element 3 and the insulation N2.

薄膜素子の従来の一般的な製造方法の概要を、薄膜抵抗
素子を例に採り上げ、再び第1図を利用して説明する。
An overview of the conventional general manufacturing method for thin film elements will be explained using a thin film resistive element as an example, again using FIG. 1.

まず、基板半導体1の上に形成された、例えば二酸化シ
リコン(Si02)から成る絶縁層2を、周知の写真加
工技術を用いて所定のパターンに加工し、この絶縁層2
の表面上の全体に、例えばクロム(Cr)を含有する一
酸化シリコン(SiO)膜(通称サーメツト膜として知
られている)を蒸着し、該サーメツト膜を同様に写真加
工技術を用いて加工して所定パターンの薄膜抵抗素子3
を形成する。
First, an insulating layer 2 made of silicon dioxide (SiO2), for example, formed on a semiconductor substrate 1 is processed into a predetermined pattern using a well-known photo processing technique.
For example, a silicon monoxide (SiO) film containing chromium (Cr) (commonly known as a cermet film) is deposited over the entire surface of the cermet film, and the cermet film is similarly processed using photoprocessing technology. Thin film resistive element 3 with a predetermined pattern
form.

必要に応じて該薄膜抵抗素子3の一端にアルミニウム(
A1)等を蒸着し、これを写真加工等により所定形状に
加工して電極(図示省略)を形成する。
Aluminum (
A1) etc. are deposited and processed into a predetermined shape by photo processing or the like to form electrodes (not shown).

こののち、該薄膜抵抗素子3の表面および絶縁層2の露
出表面全体に、例えばCVD (化学的蒸着)法により
珪りん酸ガラス(PSG )等の膜を形成して薄膜素子
の製造が完了する。
Thereafter, a film of phosphosilicate glass (PSG) or the like is formed on the surface of the thin film resistance element 3 and the entire exposed surface of the insulating layer 2 by, for example, CVD (chemical vapor deposition) to complete the production of the thin film element. .

上記のような製造方法によって形成された薄膜素子にお
いては、絶縁層2の段差部分(該開口部の側壁)におけ
る薄膜の被覆率が低い(すなわち膜厚が小さい)ために
、一般に正常な導通が得られ難いとか、あるいは通電時
における断線が発生しやすい等の問題を生じる。薄膜抵
抗素子の場合にはこの他に、抵抗値が所定値より大きく
なり、かつそのバラツキが増大しやすい等の問題を生じ
る。これらの問題は、薄膜素子を用いた半導体集積回路
の製造時の歩留りのみならず、装置に実装後における信
頼性をも低下させる原因となる。
In the thin film element formed by the above manufacturing method, normal conduction is generally not achieved due to the low coverage (i.e., small film thickness) of the thin film at the stepped portion of the insulating layer 2 (the side wall of the opening). This causes problems such as being difficult to obtain or easily breaking when energized. In addition, in the case of a thin film resistive element, problems arise such that the resistance value becomes larger than a predetermined value and the variation thereof tends to increase. These problems cause not only a decrease in yield during the manufacture of semiconductor integrated circuits using thin film elements, but also a decrease in reliability after mounting on a device.

上記のような問題に対する従来の対策としては、(i>
写真加工技術を用いて絶縁層2に前記開口部を形成する
際に、主にエツチング条件を制御して該開口部の側壁が
傾斜面を成すように絶縁層2をエツチングしたのち薄膜
を蒸着するか、あるいは(ii)被蒸着物を自公転させ
ながら薄膜を蒸着するかの方法によって、該側壁におけ
る被覆率を大きくすることが行われていた。
Conventional countermeasures to the above problems include (i>
When forming the opening in the insulating layer 2 using photo processing technology, the etching conditions are mainly controlled so that the insulating layer 2 is etched so that the side wall of the opening forms an inclined surface, and then a thin film is deposited. Alternatively, (ii) a thin film is deposited while rotating and revolving the deposition target to increase the coverage on the side wall.

しかしながら、半導体集積回路における集積度が高くな
るにしたがって、該開口部の寸法が小さく、例えばその
径は1〜1.5μm程度となっている。これに対して絶
縁層2の膜厚は1μm程度である。このために、上記従
来の方法では充分な効果を得難くなったのである。
However, as the degree of integration in semiconductor integrated circuits increases, the size of the opening becomes smaller, for example, the diameter is about 1 to 1.5 μm. On the other hand, the thickness of the insulating layer 2 is about 1 μm. For this reason, it has become difficult to obtain sufficient effects using the conventional methods described above.

すなわち、開口部における基板半導体1と薄膜素子3と
の確実な接触を保証するためには、該開口底部で一定限
度以上の面積を確保する必要があるが、その上で側壁に
充分な傾斜面を与えようとすると、上記(i)の方法に
よれば該開口部の占める割合が太き(なる。これは、絶
縁層2の表面におj)る薄膜素子およびその他の配線の
形成条件を厳しくし、ひいては基板半導体1に形成され
る半導体素子の集積密度を制約する。言い替えれば、該
側壁に与えることができる傾斜角には限度があることに
なる。また、上記(ii )の方法では、上述のような
絶縁層2の膜厚と開口径の関係においては、側壁に対す
る蒸着物の入射角(該側壁と蒸着物の入射方向とのなす
角)を充分大きくすることができず、開口底部に近い側
壁部分はど被覆率向上の効果が現れ難い。
In other words, in order to ensure reliable contact between the substrate semiconductor 1 and the thin film element 3 at the opening, it is necessary to secure a certain area or more at the bottom of the opening, and on top of that, the sidewalls must have a sufficient slope. When trying to provide a thin film element and other wiring on the surface of the insulating layer 2, the method (i) above increases the proportion of the opening. This further restricts the integration density of semiconductor elements formed on the substrate semiconductor 1. In other words, there is a limit to the angle of inclination that can be given to the side wall. In addition, in the method (ii) above, in the relationship between the film thickness of the insulating layer 2 and the opening diameter as described above, the incident angle of the vapor deposit with respect to the side wall (the angle formed between the side wall and the incident direction of the vapor deposit) is It cannot be made sufficiently large, and the effect of improving the coverage rate is difficult to be seen in the side wall portion near the bottom of the opening.

上記のような理由から、半導体集積回路の高集積化に対
処可能な薄膜素子の製造方法の開発が要望されていた。
For the above-mentioned reasons, there has been a demand for the development of a method for manufacturing thin film elements that can cope with higher integration of semiconductor integrated circuits.

(d1発明の目的 本発明は、所定の特性値を有するとともに高信頼性の薄
膜素子を、実質的に前記絶縁層および開口の寸法にかか
わりな(高歩留りで製造可能とすることを目的とする。
(d1 Purpose of the Invention The present invention aims to make it possible to manufacture a highly reliable thin film element having predetermined characteristic values and with high yield substantially regardless of the dimensions of the insulating layer and the opening. .

(e)発明の構成 本発明は、段差が存在する基板上に薄膜素子を形成する
に際し、該段差の側壁面にのみ該薄膜素子よりも比抵抗
の小さな膜を形成することを特徴とする。
(e) Structure of the Invention The present invention is characterized in that when a thin film element is formed on a substrate having a step, a film having a resistivity smaller than that of the thin film element is formed only on the side wall surface of the step.

(f)発明の実施例 以下に本発明の実施例を図面を参照して説明する。以下
の図面において第1図におけると同じものには同一符号
を付しである。
(f) Embodiments of the Invention Below, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same parts as in FIG. 1 are designated by the same reference numerals.

第2図は、薄膜素子の本発明に係る製造方法の概要を示
す図であって、主要工程段階における該薄・膜素子の断
面構造を模式的に示している。
FIG. 2 is a diagram showing an outline of the method for manufacturing a thin film element according to the present invention, and schematically shows the cross-sectional structure of the thin film element at the main process steps.

まず、従来の方法におけると同様にして基板半導体1の
上に形成された絶縁N2の一部に開口部(コンタクトホ
ール)5を設けたのち、該絶縁層2および、該開口部5
にわたる全面に、例えばモリブデン(Mo)等の金属層
6を形成する(第2図(A))。
First, in the same manner as in the conventional method, an opening (contact hole) 5 is provided in a part of the insulation N2 formed on the substrate semiconductor 1, and then the insulation layer 2 and the opening 5 are formed.
A metal layer 6 of, for example, molybdenum (Mo) is formed over the entire surface (FIG. 2(A)).

この場合、該金属層6を被覆率の高い(いわゆる廻り込
み現象の大きい)方法を用いて形成することが特徴であ
る。その結果、開口部5の側壁面にも絶縁N2の表面お
よび開口部5の底面におけるとほぼ同じ膜厚の金属層6
が被着されることになる。上記の高い被覆率を与える膜
形成方法としては、例えば減圧CVD (化学蒸着)法
が好適であり、金属層6としてMoNPAを形成するた
めには、例えば六塩化モリブデン(MoC16)と水素
の混合ガスを用いればよく、また、例えば六弗化タング
ステン(WF6 )と水素の混合ガスを用いることによ
ってタングステン(W)膜を形成することができる。
In this case, a feature is that the metal layer 6 is formed using a method that provides a high coverage rate (a method that causes a large wrap-around phenomenon). As a result, the metal layer 6 on the side wall surface of the opening 5 has approximately the same thickness as that on the surface of the insulating N2 and the bottom surface of the opening 5.
will be covered. For example, a low pressure CVD (chemical vapor deposition) method is suitable as a film forming method that provides the above-mentioned high coverage.In order to form MoNPA as the metal layer 6, for example, a mixed gas of molybdenum hexachloride (MoC16) and hydrogen is used. Alternatively, a tungsten (W) film can be formed by using, for example, a mixed gas of tungsten hexafluoride (WF6) and hydrogen.

上記のようにして形成された金属N6の表面の全面にわ
たって、その表面に対して垂直方向の選択エツチングを
行う。該選択エツチングの方法としては、例えば該垂直
方向に印加された電界の下での反応性プラズマガスエツ
チングあるいはイオンエツチング等が好適である。前者
においては金属層6が前記MoあるいはWである場合に
は塩素ガスあるいは弗素ガスを、後者においてはアルゴ
ンガスを用いればよい。上記のようにして、ちょうど金
属層6の膜厚に相当するだけ選択エツチングを行い、開
口部5の側壁部のみに金属層6が残留した構造を得る〔
第2図(B)〕。
Selective etching is performed in a direction perpendicular to the entire surface of the metal N6 formed as described above. Suitable selective etching methods include, for example, reactive plasma gas etching or ion etching under an electric field applied in the vertical direction. In the former case, when the metal layer 6 is made of Mo or W, chlorine gas or fluorine gas may be used, and in the latter case, argon gas may be used. In the manner described above, selective etching is performed to exactly correspond to the film thickness of the metal layer 6 to obtain a structure in which the metal layer 6 remains only on the side wall of the opening 5.
Figure 2 (B)].

次に露出した絶縁層2および開口部5の全面にわたって
薄膜素子構成用の膜、例えばクロム(Cr)を含んだ一
酸化珪素(SjO)から成るサーメツト膜7を蒸着によ
り形成する〔第2図(C)〕。
Next, a film for forming a thin film element, for example, a cermet film 7 made of silicon monoxide (SjO) containing chromium (Cr) is formed by vapor deposition over the exposed insulating layer 2 and the entire surface of the opening 5 (see FIG. 2). C)].

以下、従来の方法におけると同様に、写真加工法でサー
メツト膜7を所定パターンに加工し〔第2図(D)) 
、例えば該サーメツト膜7の一端に所定パターンのアル
ミニウム層から成る電極8を形成したのち、最後に絶縁
層2の露出面、サーメツト膜7、電極8の各表面の全面
にわたって、例えば前記PSG等から成る保護膜4を形
成して薄膜抵抗素子が完成する〔第2図(E)〕。
Thereafter, as in the conventional method, the cermet film 7 is processed into a predetermined pattern using a photo processing method [Fig. 2 (D)].
For example, after forming an electrode 8 made of an aluminum layer in a predetermined pattern on one end of the cermet film 7, the exposed surface of the insulating layer 2, the entire surface of the cermet film 7, and the electrode 8 are covered with, for example, PSG or the like. A protective film 4 is formed to complete the thin film resistive element [FIG. 2(E)].

本発明の効果を第3図によって説明する。同図は前記開
口部5における側壁面の傾斜角と薄膜抵抗素子の抵抗値
のバラツキの関係を示す図であって、該バラツキは((
Ra−Rd) /Rd) xlOO(%)で表した値で
ある。ただし、Raは実測値、I?dは設計値である。
The effects of the present invention will be explained with reference to FIG. This figure shows the relationship between the inclination angle of the side wall surface in the opening 5 and the variation in the resistance value of the thin film resistance element, and the variation is ((
Ra-Rd) /Rd) xlOO (%). However, Ra is the actual value, I? d is a design value.

従来の方法による薄膜抵抗素子においては、同図(A)
に示す前記傾斜角θが小さい程、側壁面における被覆率
が高く、該部分の抵抗成分が小さくなる。一方、該傾斜
角θが90度に近づ(と側壁面における被覆率が低くな
り、該部分の抵抗成分が無視し得なくなるとともに該部
分の抵抗値のバラツキが大きくなる。したがって、l従
来の方法による薄膜抵抗素子の場合には、同図(B)に
白丸で示すように、傾斜角θが90度付近から抵抗値の
バラツキが急速に増加する。これに対して、本発明に係
る方法による薄膜抵抗素子の場合には、同図(B)に黒
丸で示すように、傾斜角θが100数十度においても極
めて小さなバラツキを示すに留まる。すなわち、前記側
壁面がオーバーハング状であってもその表面に金属N6
が形成され、該側壁面における抵抗成分の増加を抑える
効果があることを示している。
In the thin film resistor element by the conventional method, the same figure (A)
The smaller the inclination angle θ shown in , the higher the coverage on the side wall surface, and the smaller the resistance component of this portion. On the other hand, as the inclination angle θ approaches 90 degrees (and the coverage rate on the side wall surface decreases, the resistance component of this part cannot be ignored, and the variation in the resistance value of this part becomes large. Therefore, l conventional In the case of the thin film resistive element produced by the method, as shown by the white circles in FIG. In the case of the thin film resistive element according to the invention, as shown by the black circles in FIG. Even if there is metal N6 on the surface
is formed, indicating that there is an effect of suppressing an increase in the resistance component on the side wall surface.

上記のように、本発明に係る製造方法によれば、開口部
における絶縁層の段差部分に傾斜を与えることなぐ該部
分での抵抗成分を減少させ、薄膜素子の電気的特性を均
一化ならびに安定化することが可能となる。したがって
、薄膜抵抗素子の場合には、その抵抗値を絶縁N2の上
に形成されるパターン形状と膜厚によって高精度で制御
できることになり、また、該段差部分の過大抵抗による
発熱に起因する断線等の障害の発生がなくなり、該薄膜
素子を用いる集積回路の長期にわたる安定動作の保証が
可能となる。さらに、従来の方法におけるような薄膜素
子の形成条件による半導体素子の集積度に対する制約を
生じることもない。
As described above, according to the manufacturing method of the present invention, the resistance component in the stepped portion of the insulating layer at the opening is reduced without giving an inclination, and the electrical characteristics of the thin film element are made uniform and stabilized. It becomes possible to convert into Therefore, in the case of a thin film resistance element, its resistance value can be controlled with high precision by the pattern shape and film thickness formed on the insulating N2, and it is also possible to control the resistance value with high precision by controlling the pattern shape and film thickness formed on the insulating N2. This eliminates the occurrence of such troubles, making it possible to guarantee long-term stable operation of integrated circuits using the thin film element. Furthermore, there is no restriction on the degree of integration of semiconductor elements due to the conditions for forming thin film elements, as in conventional methods.

上記の実施例においては、本発明の適用を主として薄膜
抵抗素子を対象として説明したが、溶融切断素子あるい
は導体配線に対しても同様に適用可能であり、これらを
必須とする半導体集積回路の電気的特性の均一化ならび
に安定化に効果があることは明らかである。また、本発
明は、半導体集積回路以外で同様の微細配線構造を有す
る電気回路あるいは回路素子に対しても適用可能である
ことは言・うまでもない。
In the above embodiments, the application of the present invention was mainly explained to thin film resistive elements, but it is also applicable to melt cutting elements or conductive wiring, and is applicable to semiconductor integrated circuits that require these elements. It is clear that this method is effective in uniformizing and stabilizing physical characteristics. It goes without saying that the present invention can also be applied to electric circuits or circuit elements having similar fine wiring structures other than semiconductor integrated circuits.

(g1発明の効果 本発明によれば、高集積度の半導体集積回路において、
高精度の薄膜素子を高歩留りで製造可能とする効果があ
る。
(g1 Effect of the invention According to the invention, in a highly integrated semiconductor integrated circuit,
This has the effect of making it possible to manufacture highly accurate thin film elements with high yield.

【図面の簡単な説明】[Brief explanation of drawings]

れ製造工程の概要を説明するための図、第3図は従来の
方法および本発明に係る方法による薄膜抵抗素子の製造
条件と電気的特性の関係の一例を示す図である。 図において、■は基板半導体、2は絶縁層、3は薄膜素
子、4は保護膜、5は開口部、6は金属層、7はサーメ
ソ1」臭、8匙は電極である。
FIG. 3 is a diagram for explaining an overview of the manufacturing process, and is a diagram showing an example of the relationship between manufacturing conditions and electrical characteristics of thin film resistive elements by a conventional method and a method according to the present invention. In the figure, ■ is the substrate semiconductor, 2 is the insulating layer, 3 is the thin film element, 4 is the protective film, 5 is the opening, 6 is the metal layer, 7 is thermestic odor, and 8 spoons are the electrodes.

Claims (1)

【特許請求の範囲】[Claims] 段差が存在する基板上に薄膜素子を形成するに際し、該
段差の側壁面にのみ該薄膜素子よりも比抵抗の小さな膜
を形成することを特徴とする薄膜素子の製造方法。
A method for manufacturing a thin film element, which comprises forming a thin film element on a substrate having a step, and forming a film having a resistivity smaller than that of the thin film element only on the side wall surface of the step.
JP13161583A 1983-07-19 1983-07-19 Manufacture of thin film element Granted JPS6024050A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13161583A JPS6024050A (en) 1983-07-19 1983-07-19 Manufacture of thin film element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13161583A JPS6024050A (en) 1983-07-19 1983-07-19 Manufacture of thin film element

Publications (2)

Publication Number Publication Date
JPS6024050A true JPS6024050A (en) 1985-02-06
JPH0454981B2 JPH0454981B2 (en) 1992-09-01

Family

ID=15062201

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13161583A Granted JPS6024050A (en) 1983-07-19 1983-07-19 Manufacture of thin film element

Country Status (1)

Country Link
JP (1) JPS6024050A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146051A (en) * 1984-08-10 1986-03-06 Sony Corp Wiring method
JPS6362355A (en) * 1986-09-03 1988-03-18 Nec Corp Semiconductor device and manufacture thereof
US5387311A (en) * 1993-02-16 1995-02-07 Vlsi Technology, Inc. Method for manufacturing anti-fuse structures
JP2005268749A (en) * 2004-02-19 2005-09-29 Ricoh Co Ltd Semiconductor device
JP2011009775A (en) * 2004-02-19 2011-01-13 Ricoh Co Ltd Method of manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5582458A (en) * 1978-12-18 1980-06-21 Toshiba Corp Preparation of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5582458A (en) * 1978-12-18 1980-06-21 Toshiba Corp Preparation of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6146051A (en) * 1984-08-10 1986-03-06 Sony Corp Wiring method
JPS6362355A (en) * 1986-09-03 1988-03-18 Nec Corp Semiconductor device and manufacture thereof
US5387311A (en) * 1993-02-16 1995-02-07 Vlsi Technology, Inc. Method for manufacturing anti-fuse structures
JP2005268749A (en) * 2004-02-19 2005-09-29 Ricoh Co Ltd Semiconductor device
JP2011009775A (en) * 2004-02-19 2011-01-13 Ricoh Co Ltd Method of manufacturing semiconductor device
US7999352B2 (en) 2004-02-19 2011-08-16 Ricoh Company, Ltd. Semiconductor device

Also Published As

Publication number Publication date
JPH0454981B2 (en) 1992-09-01

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