JPS60233951A - Multiplex converting circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by applying time division processing to plural low speed data signals to write or read them and allowing a couple of RAMs to act as plural frame converting circuit to decrease the number of the RAMs and peripheral circuits. CONSTITUTION:A couple of the RAMs 12, 13 are high-speed RAMs having a storage capacity storing information for one frame's share of multiplexed signals. One bit of the low-speed data signal is divided into (n), which is switched to n sets of signal lines CH1-CHn by a selector 11 and the information of each signal line is stored in each area of the RAMs divided into (n) in a way of time division. Thus, the number of RAMs peripheral circuits such as selectors is less and the power consumption is reduced.

Description

[Detailed Description of the Invention] [Technical Field] The present invention converts a plurality of continuous data signals into high-speed time division multiplexed signals using a multiplex conversion circuit, particularly a pair of random access memories (hereinafter abbreviated as RAM). , or a multiplex conversion circuit that converts a high-speed time division multiplexed signal into a plurality of continuous data signals.

[Prior art]

Conventionally, multiple continuous low-speed data signals are time-division multiplexed to convert them into high-speed data signals, and conversely, they are converted to time-division multiplexed signals, and vice versa. A multiplex conversion circuit that separates a signal into a plurality of continuous low-speed data signals includes a burst conversion circuit that uses a pair of RAMs to write data at low speed and read data at high speed to convert continuous data signals into burst signals, or a high-speed conversion circuit that converts continuous data signals into burst signals. It is constructed using multiple burst inverse conversion circuits (burst conversion circuits and burst inversion circuits are collectively referred to as 7-rem conversion circuits) that convert burst signals into continuous data signals by writing and reading at low speed. ing. This conventional method has the disadvantage that the number of RAMs and its peripheral circuits used increases in proportion to the number of low-speed data signals to be multiplexed (number of multiplexes), which will be described in detail later, and power consumption also increases. .

[Purpose of the invention]

An object of the present invention is to time-divisionally process a plurality of low-speed side data signals and write or read them so that a pair of RAMs can perform the functions of a plurality of 7V-mem conversion circuits, thereby eliminating the drawbacks of the conventional method described above. An object of the present invention is to provide a multiple conversion circuit.

[Structure of the invention]

The multiplex conversion circuit of the present invention includes a pair of random access memories, and a primary side selector that sequentially switches n low-speed side data signal lines (n is a positive integer) and connects them to one of the pair of random access memories. , a secondary side selector that switches and connects one high-speed side data signal line to the other of the pair of random access memories, and a primary side address counter that controls the secondary side selector and the pair of random access memories; a secondary side address counter that controls the pair of random access memories; and a secondary side address counter that controls the pair of random access memories so that the pair of random access memories alternately repeats writing and reading at regular intervals and operates complementary to each other. and an address selector for switching between the secondary side address counter and the n low-speed side data signal lines to sequentially access addresses in each of the n-divided areas of the random access memory within one bit period of the low-speed side data signal. The high-speed data signal line is configured to successively access each address in each area of the random access memory.

〔Example〕

Next, the present invention will be described in detail with reference to the drawings.

Before describing embodiments of the present invention, a conventional multiplex conversion circuit will be briefly described with reference to FIG. In FIG. 1, a low-speed side data signal line 101 is controlled by a primary side selector 1 controlled by a frame synchronization signal 102.
2 and 3, and is sequentially written to each address of R, AM2 or Fi3 for each frame by the primary address counter 4 operating at the clock frequency of the low-speed data. The secondary selector 5 connects the high-speed data signal line 103 to the RAM on the opposite side of the primary selector 1, and the written information is sent to the secondary side address counter 6 as a time-division multiplexed signal approximately one times that of the low-speed side. is read out at a clock frequency of
The signal is converted into a burst signal of about 17 n for one frame period. The address selector 7 is a selector that performs switching between the RAMs 2 and 3 and each address counter, and switching between writing and reading.

In order to multiplex n channels, n frame conversion circuits (8-1, 8-2, . . . ) with a similar configuration are required.
. . 8-n), the start times of the respective secondary side address counters are set so that the respective burst signals do not overlap, and the respective outputs are combined by the combining circuit 9 to obtain a time division multiplexed signal. That is, there is a drawback that the number of peripheral circuits such as R, -AM and selectors increases in proportion to the number of channels to be multiplexed, and power consumption also increases.

FIG. 2 is a block diagram of an embodiment of the present invention, in which a pair of RAMs 12, 13 . n low-speed side data signal lines CHI, CH2,...CHn fRA
It is composed of a primary side selector 11 connected to M12, 13, a negative side address counter 14, a secondary side selector 15, a secondary side address counter 16, and an address selector 17. Figures 3 (a) and (b) are time charts for explaining the operation of Hiro 2. (a) is on the - next side (b)
indicates the secondary side. In Figure 2, R, AM12 and L
Reference numeral 3 denotes a high-speed RAM having a storage capacity capable of storing information for one frame of the multiplexed signal, and as shown in FIG.
. . . tl is divided into n, and the selector 11 switches each signal line to n signal lines CHI, CH2, . It is configured to be stored in For this reason, −
The next side address color/receiver 14 is configured to change the lower bits at a slower clock frequency, and change a specific upper bit by cycling from 1 to n at a clock frequency n times higher, and this upper bit change. Correspondingly, the input direction of the primary side selector 11 is switched between channels 1 to n. The secondary side address counter 16 is configured to change the lower bits with the clock of the high speed side data signal, and conversely, the above-mentioned upper bits are changed from l to n by dividing one frame period into n. Therefore, Fig. 3(b)
As shown in , the information of each channel becomes a burst signal, and the burst signal of each channel (CHI, CH2, . . . song CHn) is T1. T2. . . . They are arranged sequentially within the time Tn, and a time division multiplexed signal is obtained.

Although this circuit has a larger RAM storage capacity than the conventional circuit shown in FIG. 1, it has only a pair of RAM peripheral circuits, such as a selector, and has the effect of reducing power consumption.

The above explanation deals with multiplexing low-speed signals (signal transmission directions are shown by solid arrows in Figures 1 and 2), but if reading is reversed to writing, the same configuration can be achieved. A multiplex converter circuit that separates each channel signal from a time-division multiplexed signal (the signal transmission direction is indicated by a broken line arrow) can be configured. In addition, in the explanation of the above embodiment, the case where n channels of high-speed side data signals are arranged in one frame period as shown in FIG. 3(b) was explained, but depending on the memory capacity of the RAM, one frame period Instead, it is also possible to partially multiplex the circuit by placing it in half the period, for example, and use two such multiplex conversion circuits, and switch between R and AM 12 and 13 not every 17 frames but every multiple frames. It's okay. Note that 1 bit 6 is shown in Figure 3 for ease of understanding.
2 is a diagram in which an l frame is divided into n equal parts, but the division need not necessarily be equal, and it goes without saying that synchronization and monitoring control signals can be inserted and extracted. Furthermore, it is not necessary for each address counter to designate addresses in an orderly manner; if addresses are designated randomly in a predetermined order, a multiplex conversion circuit with a secret function can be constructed.

〔Effect of the invention〕

As explained in detail above, according to the multiplex conversion circuit of the present invention, 1. Using a pair of RAMs, it is possible to configure a multiplex conversion circuit that multiplexes n continuous data signals into a time division multiplexed signal, or conversely separates n continuous data signals from a time division multiplexed signal. This has the effect of reducing the number of RAMs and their peripheral circuits and reducing power consumption.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional multiplex conversion circuit, Figure 2 is a block diagram of an embodiment of the present invention, and Figures 3 (a) and (b).
2 is a time chart on the low speed side and the cylinder speed side in FIG. 2. 1, 5.7.11.15.17・Old・・Selector, 2゜3.12,13・・・・Random access memory (
RAM), 4, 6, 14.16...address counter, 8-1.8-2. ~g -n...Frame conversion circuit, 9...Composition circuit. Battle 1 Betsujo 2nd class 3rd class (Pano Cb)

Claims (1)

[Claims] a pair of random access memories; a primary selector that sequentially switches n (n is a negative integer) low-speed data signal lines to connect them to one of the pair of random access memories; and one high-speed data signal line. a secondary selector that switches and connects the line to the other of the pair of random access memories; a primary address counter that controls the secondary selector and the pair of random access memories; a secondary side address selector to control, and the secondary side address counter and the secondary side address counter so that the pair of random access memories operate complementary to each other by repeating writing and continuous writing alternately at regular intervals. and an address selector for switching between the n low-speed side data signal lines, and the n low-speed side data signal lines sequentially access addresses in each of the n divided areas of the random access memory within the λ bit period of the low-speed side data signal, and the high-speed side data A multiple conversion circuit characterized in that a signal line is configured to successively access each address in each of the areas of the random access memory.