JPS60233838A - Semiconductor ic device - Google Patents
Semiconductor ic deviceInfo
- Publication number
- JPS60233838A JPS60233838A JP59087782A JP8778284A JPS60233838A JP S60233838 A JPS60233838 A JP S60233838A JP 59087782 A JP59087782 A JP 59087782A JP 8778284 A JP8778284 A JP 8778284A JP S60233838 A JPS60233838 A JP S60233838A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- unit cell
- well
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims description 23
- 239000012535 impurity Substances 0.000 claims description 8
- 230000000295 complement effect Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 abstract description 8
- 239000000872 buffer Substances 0.000 abstract description 2
- 238000003491 array Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体集積回路装置、特にマスタヌライス方式
によるマスタチップとして用いられる半導体集積回路装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device used as a master chip according to a master nulling method.
少量多品糧の集積回路を効率よく開発するために、拡散
工程までは各品種に共通なマスクパターンを設計し共通
プロセスでメＪ造しておき、西−線パターンのみを各品
種ごとに設計製造するマスタスライス方式は、従来から
広く採用されている。従来の相補型ＭＯ８ＦＥＴ を用
いたマスタスライス方式によるマスタチップの上面図を
第１図に示す。In order to efficiently develop integrated circuits for small quantities and many products, a mask pattern common to each product is designed and fabricated using a common process up to the diffusion process, and only the west line pattern is designed for each product. The master slice method for manufacturing has been widely adopted. FIG. 1 shows a top view of a master chip using a master slice method using conventional complementary MO8FETs.
パッド、入力保砕回路等で構成される入出力回路１の集
合である入出力回路列２がチップの周囲に配される。ま
た、相補型ＭＯ８ＦＢＴによって構成される単位セル３
を並べた単位セル列４がチップ中央部の単位セル集合体
領域５に配される。各単位セル列４の間には配線領域６
が設けられる。第１図のマスタチップを切断輻Ｘ−Ｘで
切断した断面の一部分を第２図に示す。ここでｖＩ域巳
およびｂは第１１’、２１の領域＆およびｂに対応する
。Ｎ型基板７上に設けられたＰ＋拡散領域８はＰチャネ
ルＭＯ８ＦＥＴ を構成する。このＦＥＴのソース、ゲ
ート、ドレインは第２図で紙面に垂直な方向に並んでい
るため、図にはソースまたはドレインの一方＋
のみしか表わされてい表い。Ｎ 拡散領域９およびＰ型
ウェル１．０１ｄＮチャネルＭＯ日ＦＩＴ ｌ構成する
。このＰＥＴも図ではソースまたはドレインの一方のみ
しか表わされていない。これら２つのＮＥＴＫよって相
補型ＭＯ８ＦＥＴが構成されることになる。Ｎ型基板７
上には絶縁層１１が形成され、これに−１７タ？トホー
ルが開けられてアルミニウムの重接１２および１３が形
成される。奄′＠１．１２には電源ｖＤＤが接続され、
電極１３は接地される。電極１２の下にｔＩｉＮ＋拡散
領域１４が、イ嘩１３の下にはＰ＋拡散領域１５がそれ
ぞれガードリングとして設けられる。第３図は第１図の
部分拡大図である。図中の２分よびＮはそれぞれＰチャ
ネルＭＯ８ＦＥＴ を構成するＰ型飴域およびＮチャネ
ルＭＯ８１＋’ＢＴ を構成するＮ型領域を示す。以上
のような構成のマスタチップの電位セル列４と配線領域
６に配線パターンが形成され、各品種ごとのチップが得
られる。An input/output circuit array 2, which is a set of input/output circuits 1 including pads, input protection circuits, etc., is arranged around the chip. In addition, unit cell 3 constituted by complementary MO8FBT
A unit cell row 4 in which . A wiring area 6 is provided between each unit cell column 4.
is provided. FIG. 2 shows a portion of the cross section of the master chip shown in FIG. 1 taken along the cutting radius X--X. Here, vI region and b correspond to the 11', 21st region & and b. P+ diffusion region 8 provided on N type substrate 7 constitutes a P channel MO8FET. Since the source, gate, and drain of this FET are arranged in a direction perpendicular to the plane of the paper in FIG. 2, only one of the source and drain is shown in the figure. N diffusion region 9 and P type well 1.01dN channel MO day FIT l constitute. This PET also shows only one of the source and drain in the figure. These two NETKs constitute a complementary MO8FET. N-type substrate 7
An insulating layer 11 is formed on top, and -17 ta? Holes are drilled to form aluminum welds 12 and 13. Power supply vDD is connected to 奄′@1.12,
Electrode 13 is grounded. A tIiN+ diffusion region 14 is provided under the electrode 12, and a P+ diffusion region 15 is provided below the insulator 13 as a guard ring. FIG. 3 is a partially enlarged view of FIG. 1. 2 and N in the figure indicate the P-type region constituting the P-channel MO8FET and the N-type region constituting the N-channel MO81+'BT, respectively. A wiring pattern is formed in the potential cell array 4 and the wiring area 6 of the master chip configured as described above, and chips for each type are obtained.
上述した従来の半導体集積回路装置においては、電極１
２および１３を多数のＦＥＴが共用しておシ、多数のゲ
ート類が同時スイッチングした場合等に、瞬時に大電流
が流れ、電源ｖＤＤや接地点の電位に揺らぎが生じ内部
雑音が発生する。また、インパクトイオン化現象により
、ホットエレクトロンや基板電流が１０（ＬＳＩ）内に
生じる。これら′眠源ラインの内部雑音や基板電流等は
ラッチアップの原因となる。In the conventional semiconductor integrated circuit device described above, the electrode 1
When 2 and 13 are shared by a large number of FETs and a large number of gates switch simultaneously, a large current flows instantaneously, causing fluctuations in the potential of the power supply vDD and the ground point, causing internal noise. Furthermore, due to the impact ionization phenomenon, hot electrons and substrate current are generated within the LSI. Internal noise and substrate current in these 'sleep source lines' cause latch-up.
即ち、相補型ＭＯ３ＦＥＴ 内に形成される寄生トラン
ジスタが、内部雑音や基板電流等によってターンオンし
、工０ （７Ｊ Ｓ ｘ ）の誤動作やｒＪｌ壊ｆ引起
す現象が生ずる（例えば電子通毎学会論文誌Ｊ６１（１
９７８）Ｐ、 １０６）。In other words, the parasitic transistor formed in the complementary MO3FET is turned on due to internal noise, substrate current, etc., resulting in malfunction of 0 (7J S x ) and failure of rJ1 (e.g., J61(1
978) P, 106).
そこで本発明は、ラッチアップ現象の生ずることのない
マスタスライス方式のマスタチップとして用いられる半
導体集積回路装置を提供することを目的とする。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device that is used as a master chip in a master slice method and is free from latch-up phenomena.
本発明の％νシば、相補型ＭＯ８ＦＥＴ 金柑いたマス
タスライス方式による半導体集積回路装置において、隣
接する単位セル列の囲いあう末子領域が同じ導電型の素
子領域となるように各単位セル列を配置し、各単位セル
列間の配線領域のうち、Ｐチャネル光子領域か向いあう
配線領域にはＮ 不純物拡散を行い、Ｎチャネル朱子領
域が向いあう配線領域にはＰ 不純物拡散およびＰウェ
ル形成と行Ｉｎ、Ｎ 不純物拡散１鍔に雷神を接続し、
Ｐ１不純物拡散層を接＃紐に接続するようにして、電源
および接地線の電位の揺らぎを減少させ、また、インパ
クトイオン化現象により生ずるポットエレクトロン、基
板電流の影響を減少させることにより、ラッチアップ現
脈が生じないようにした点にある。According to the present invention, in a semiconductor integrated circuit device using a complementary MO8FET master slicing method, each unit cell row is arranged such that the terminal regions of adjacent unit cell rows are element regions of the same conductivity type. Of the wiring regions between each unit cell column, N impurity diffusion is performed in the wiring region facing the P channel photon region, and P impurity diffusion and P well formation are performed in the wiring region facing the N channel satin region. In, N Impurity diffusion 1 Connect the thunder god to the tsuba,
By connecting the P1 impurity diffusion layer to the connecting cord, the fluctuations in the potential of the power supply and ground lines are reduced, and the effects of pot electrons and substrate current caused by the impact ionization phenomenon are reduced, thereby preventing latch-up. The reason is that the pulse is not generated.
以下本発明を図示する実施例に基づいて詳述する。第４
圀は本発明に係る半導体集積回路装置の上面図で、第１
図と同一構成要素につめては同一符号を角し説明を省略
する。単位セル列４′および４５ＮチヤネルとＰチャネ
ルの構成が互いに入れかわった形の単位セルの集合で、
この関係は第４図の部分拡大図である第６図を参照する
ことによってより明確化する。ＮチャネルとＰチャネル
トが入れかわることによって電４；ｙ １２および１３
の位買関係も逆転する。第４図に示すように単位セル列
４１および４＋１は交互に配せられる。従って号りあう
単位セルｈ（１においては、同じ導’ｆ％、’型の表子
領域が向いあうことになる。囲いあうＰ型の勢子領域に
侠掟れた配猾領域６９および回いあうＮ型の米子領域に
挾−！、わ、た配線領域６１には、それぞれ異なった層
が基板内に形成される。これらの層は、第４図のマスタ
チップを切断線Ｙ −Ｙで切断した部分断面（図である
第５１シ）に示されている。即ち、配線類１或６’［相
当する基板内にＦｉＮ＋拡散層１４１が形成され、第２
図でのＮ４−拡散層１４と同様の機能を有するとともに
、隣りあう′電標ｖＤＤ用の′電極１２を互いに接続す
る歓能全果たす。一方、配線領域６１１に相当する基板
内にはＰウェル僧１σおよび？拡散Ｉ＠１５１が形成さ
れる。Ｐウェル４１０’は第２図でのＰウェル層１０と
１司枦の１幾能を有するとともに、隋りあうＮ＋拡散層
９を互いに接続する機能を果たし、１＋
た、Ｐ 拡散＋１１５−は第２図でのＰ 拡散層１５と
同様のや能を有するとともに、１１４りあう接地用電極
１３を互いに接続する機能を果たす。The present invention will be described in detail below based on illustrated embodiments. Fourth
1 is a top view of a semiconductor integrated circuit device according to the present invention;
Components that are the same as those in the figures are denoted by the same reference numerals and their explanations will be omitted. Unit cell rows 4' and 45 are a set of unit cells in which the N channel and P channel configurations are interchanged,
This relationship will be made clearer by referring to FIG. 6, which is a partially enlarged view of FIG. 4. By swapping the N channel and P channel, electric 4;y 12 and 13
The buying and selling relationship will also be reversed. As shown in FIG. 4, unit cell rows 41 and 4+1 are arranged alternately. Therefore, in the unit cell h (1), the front regions of the same conductive 'f%, ' type face each other. Different layers are formed in the substrate in each of the interconnection areas 61 that meet the N-type Yonago area.These layers are formed by cutting the master chip along the cutting line Y-Y in This is shown in a partial cross section (No. 51 in the figure). That is, the wiring type 1 or 6' [the FiN+ diffusion layer 141 is formed in the corresponding substrate, and the second
It has the same function as the N4-diffusion layer 14 in the figure, and also serves the function of connecting the adjacent electrodes 12 for the electrodes vDD to each other. On the other hand, inside the substrate corresponding to the wiring region 611 are P wells 1σ and ? Diffusion I@151 is formed. The P-well 410' has the same function as the P-well layer 10 in FIG. It has the same function as the P diffusion layer 15 in FIG.
上述のように本実施例でＵ、＊＋Ｘりあう電極１２が互
いに接続され、寸た隣りあう電極１３が互いに接続され
るため、一方の電極に瞬時に大電流が流れた場合にも他
方の電極がこれを緩衝し、電源■ゆや接地点の電位の揺
らぎによる内部雑音を従来より少なくすることができる
。一方、インパクトイオン化現象については、Ｐウェル
１０“、Ｎ＋拡散領域１４１、およびＰ十拡散頒域１５
′が、従来の各領域に比べて広くなるため、基板電流等
の影響を少なくすることができる。As described above, in this embodiment, the electrodes 12 that are opposite each other by U and *+X are connected to each other, and the electrodes 13 that are directly adjacent to each other are connected to each other, so even if a large current flows instantaneously to one electrode, the other electrode's The electrode buffers this, making it possible to reduce internal noise caused by fluctuations in potential at the power source and ground point compared to conventional devices. On the other hand, regarding the impact ionization phenomenon, P well 10'', N+ diffusion region 141, and P10 diffusion region 15
' is wider than each conventional area, so the influence of substrate current etc. can be reduced.
なお、このマスタチップに各品種に応じた配線パターン
をバターニングした後、配線領域の未使用部分を利用し
て該配線領域をはさむ両電惨どうじを互いに接続するよ
う配線することにより、電源ラインを安定化させること
もできる。In addition, after patterning the wiring pattern according to each product type on this master chip, the power supply line can be connected by using the unused part of the wiring area to connect the two electrical channels that sandwich the wiring area. It can also be stabilized.
以上のとおり、本発明によれば、電源ラインの内部雑音
やインパクトイオン化現象による基板電流等の影響を少
なくできるため、これらを原因とするラッチアップ現象
が起こりにくい半導体集積回路装置を提供することがで
きる。As described above, according to the present invention, it is possible to reduce the effects of internal noise in the power supply line and substrate current caused by impact ionization, and therefore it is possible to provide a semiconductor integrated circuit device in which the latch-up phenomenon caused by these factors is less likely to occur. can.
第１図は従来の相補型ＭＯ８ＦＥＴ を用いたマスタヌ
ライス方式による半導体集積回路装置の上面図、第２図
は第１図に示す半導体集積回路装置の切断線Ｘ−Ｘによ
る部分断面図、第８図は第１図に示す半導体集積回路装
置の上面図の部分拡大図、第４図は本発明に係る半導体
集積回路装置の上面図、第５図は第４図に示す半導体集
積回路装置の切断線ｘ−ｙによる部分断面図、第６図は
第４図に示す半導体集積回路装置の上面図の部分拡大図
である。
ｌ・・・入出力回路、２・・・入出力回路列、３・・・
単位セル、４・・・単位セル列、５・・・単位セル集合
体領域、６・・・配線領域、７・・・Ｎ型基板、８・・
・Ｐ＋拡散領域、９・・・Ｎ 拡散領域、１０・・・Ｐ
型ウェル、１１・・・絶縁層、１２・・・電源用電極、
１３・・・接地用電極、１４・・・Ｎ＋拡散領域、１５
・・・Ｐ＋拡散領域。
出願人代理人 猪 股 清
′＄ １ 図
第２図FIG. 1 is a top view of a semiconductor integrated circuit device using a conventional master-nullice method using complementary MO8FETs, FIG. 2 is a partial cross-sectional view of the semiconductor integrated circuit device shown in FIG. 1 along cutting line X-X, and FIG. is a partial enlarged view of the top view of the semiconductor integrated circuit device shown in FIG. 1, FIG. 4 is a top view of the semiconductor integrated circuit device according to the present invention, and FIG. 5 is a cutting line of the semiconductor integrated circuit device shown in FIG. 4. FIG. 6 is a partially enlarged top view of the semiconductor integrated circuit device shown in FIG. 4; l...input/output circuit, 2...input/output circuit row, 3...
Unit cell, 4... Unit cell row, 5... Unit cell assembly area, 6... Wiring area, 7... N-type substrate, 8...
・P+diffusion area, 9...N diffusion area, 10...P
mold well, 11... insulating layer, 12... power supply electrode,
13...Grounding electrode, 14...N+ diffusion region, 15
...P+ diffusion region. Applicant's agent Kiyoshi Inomata'$ 1 Figure 2
Claims (1)
いに平行になるように配された複数の単位セル列と、 この複数の単位セル列の相互間に設けられた１ｉ敬の配
線領域と、 を有する半導体集積回路装置であって、前記単位セル列
が、ＰチャネルＭＯ８ＦＥＴおよびＮチャネルＭＯ８Ｆ
ＦｉＴ よりなる相補型ＭＯ８ＦＥＴと、電源用電極と
、接地用１！極と、で構成される単位セルを、同じ導電
型のＭＯ８ＦＦｊＴが同じ側を向くように複数直線状に
並べたものである半導体集積回路装置において、 隣り合う２つの華位セル列の、配線領域をはさんで向き
合うそれぞれの側が、同じ導電型のＭＯＳＦＥＴ とな
るように前記単位セル列を配し、前記配線領域のうち、
ＰチャネルＭＯ８？ＥＴにはさまれた部分に対応する前
記Ｎ型半導体基板の■（分にＮ＋不純物拡散層を設け、
前記配＃ｊ領域のうち、ＮチャネルＭＯＦ３ＮＥＴには
さまれた部分に対応する前記Ｎ型半導体基＋ 板の部分ＫＰ 不純物拡散層およびＰウェル層を設け、 前記Ｎ＋不純物拡散層を前記寛ω用電極に接＋ 続し、前記Ｐ 不純物拡散層を前記接地用電極Ｋｌ＆続
したことを特徴とする半導体集積回路装置。[Claims] 1. An N-type semiconductor substrate, □ a plurality of unit cell rows formed on the N-type semiconductor substrate and arranged parallel to each other on the surface of the substrate, and the plurality of unit cell rows. A semiconductor integrated circuit device having a wiring area of 1 i x 1 provided between
Complementary MO8FET consisting of FiT, power supply electrode, and grounding 1! In a semiconductor integrated circuit device in which a plurality of unit cells consisting of poles and are arranged in a straight line so that MO8FFjTs of the same conductivity type face the same side, the wiring area of two adjacent cell rows The unit cell rows are arranged so that MOSFETs of the same conductivity type are on each side facing each other across the wiring area.
P channel MO8? An N+ impurity diffusion layer is provided in the part (■) of the N-type semiconductor substrate corresponding to the part sandwiched between the ETs,
A portion KP of the N-type semiconductor substrate corresponding to a portion sandwiched between the N-channel MOF3NETs in the wiring #j region, an impurity diffusion layer and a P well layer are provided, and the N+ impurity diffusion layer is used for the wide A semiconductor integrated circuit device, characterized in that the P impurity diffusion layer is connected to the grounding electrode Kl.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59087782A JPS60233838A (en) | 1984-05-02 | 1984-05-02 | Semiconductor ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59087782A JPS60233838A (en) | 1984-05-02 | 1984-05-02 | Semiconductor ic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60233838A true JPS60233838A (en) | 1985-11-20 |
Family
ID=13924546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59087782A Pending JPS60233838A (en) | 1984-05-02 | 1984-05-02 | Semiconductor ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60233838A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4928164A (en) * | 1985-11-19 | 1990-05-22 | Fujitsu Limited | Integrated circuit device having a chip |
| US5444288A (en) * | 1992-02-27 | 1995-08-22 | U.S. Philips Corporation | CMOS integrated circuit having improved power-supply filtering |
-
1984
- 1984-05-02 JP JP59087782A patent/JPS60233838A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4928164A (en) * | 1985-11-19 | 1990-05-22 | Fujitsu Limited | Integrated circuit device having a chip |
| US5444288A (en) * | 1992-02-27 | 1995-08-22 | U.S. Philips Corporation | CMOS integrated circuit having improved power-supply filtering |
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