JPS60232747A - Demodulating circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of a demodulation error at the increase of a transmission speed by testing the comparison between the preceding and succeeding signals of a receiving signal divided in each two bits at the rise and fall of a clock without using a delay circuit. CONSTITUTION:An receiving signal 11a is inputted to a receiving signal input terminal 11 of a demodulating circuit, a ''0'' signal 11a at each rise of a clock input 14a is detected by the 1st FF13, and at the detection, a Q' output 13a is turned to ''1'' only for the succeeding one period. The OR of the output 13a and the signal 11a is found out by an OR circuit 12 and its outputs 12a is applied to the data input of the 2nd FF15. A NOR output 16a corresponding to the clock input 14a is inputted from a NOR circuit 16 to the clock terminal of the FF15, the level of the output 12a of the circuit 12 is detected at the rise of the NOR output 16a and a Q output 15 from the FF15 is outputted to a demodulating signal output terminal 17 as a demodulated output. Thus, the generation of a demodulation error at the increase of the transmission speed is prevented without using a delay circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention sets one of logic 1 and 0 of an original signal to be transmitted to 10 or 01, and alternately sets the other to 11 or 00.
This invention relates to a demodulation circuit for a transmission system that converts the converted data into output.

[Background of the invention]

Conventionally, this type of demodulation circuit divides the received signal into 2-bit units, and the two bits are at the same level (i.e., 11
There are systems that detect whether the level is 0 or 00) or a different level (i.e. 1O or 01). FIG. 1 shows an example of this conventional demodulation circuit, in which a received signal 1a applied to an input terminal 1 is divided into two parts, one of which is directly input to an exclusive OR circuit 2, and the other is input to a delay circuit 3. Thereafter, it becomes an output 3a delayed by 1 bit and is also applied to the exclusive OR circuit 2. The output 2a of the exclusive OR circuit 2 is added as one input to the flip-flow circuit 4, and the clock input 5a applied from the clock input terminal 5 is added as the other input, and its Q output 4a is output as a demodulated signal. It is sent from terminal 6.

FIG. 2 shows the time chart, and an exclusive OR output 2a is obtained as a demodulated output from the received signal 1a and its 1-bit delayed signal 3a with respect to the original signal A. However, in this method, as mentioned above, the received signal is divided into two bits each, and in order to compare the levels of the first and second bits, the first beat is delayed by one bit and compared with the second bit. do. For this reason, it is necessary to use a 1-bit delay circuit, but as communication speeds increase, the demodulated output drops to zero at the change point of the received signal due to deviations in delay time settings, waveform deterioration in the delay circuit, etc. , waveform 2F1! is shown in the same figure. As shown above, the occurrence of waveform distortion is unavoidable. Therefore, demodulation errors tend to occur due to timing jitter, etc., and the transmission speed cannot be increased.

[Purpose of the invention]

The present invention solves the above-mentioned drawbacks.The present invention is designed to solve the above-mentioned drawbacks by checking the comparison of the before and after beeps/) of the received signal divided into 2 bits at the rising and falling points of the clock. The present invention has been made to provide a demodulation device that can perform the demodulation without using a demodulation error even when the transmission speed is increased. Hereinafter, the present invention will be explained in detail with reference to Examples.

[Embodiment of the Invention] FIG. 3 shows a circuit configuration diagram of an embodiment of the invention, in which the terminal 11
The received signal 11a input from the first flip-flop 12 is added as one input to the OR circuit 12, and then branched to the first flip-flop 13 as a data input. The clock input 14a is connected to the first flip-flop 13 from the terminal 14.
is added, its mutual output 13a is added as the other input of the OR circuit 12, and the output 12a of the OR circuit 12 is added as the data input of the second flip-flop 15.

On the other hand, the clock input 14a branches to the logical NOT circuit 16.
and its output 16a is input to the second flip-flop 1
5 as a clock input, and its Q output 15a is sent out from an output terminal 17 as a demodulated signal.

Next, details of the operation will be explained with reference to FIG. 3 and FIG. 4 showing a time chart thereof.

First, the first flip-flop 13 detects that the level of the received signal 11a (that is, the level of the next bit after dividing the received signal into 2 bits) at each rising point of the clock 14a is O, and this is detected. When this occurs, the available output 13a becomes l for the next one period. Next, the logical sum circuit 12 calculates the logical sum of the received signal 11a and the output 13a of the first flip-flop, and outputs the output 12a.
is applied to the second flip-flop 15 as a data input. On the other hand, the logic NOT output 16a of the clock input 14a obtained by the logic NOT circuit 16 is added to the second flip-flop 15 as a clock input, and the data input, that is, the level of the output 12a of the OR circuit at the time of its rise is detected. . Therefore, the Q output 15a becomes a demodulated output and is output from the output terminal 17.

That is, in the present invention, the received signal is divided into two as in the conventional case.
Before the received signal separated into bits.

Rather than directly comparing subsequent bits, the level of the previous bit of every two bits of the received signal is checked at the rising edge of the clock and stored in the first flip-flop 13, and then the level of the previous bit is checked by the second flip-flop 15. The purpose is achieved without using a delay circuit by checking the level of the next bit at the rising edge of the clock logic negation signal 16a, that is, the falling edge of the clock 14a. Therefore, the circuit configuration becomes simpler than the conventional case where a delay circuit is used, and the possibility of waveform deterioration due to the delay circuit is eliminated. That is, when calculating the logical sum of the first flip-flop output 13a and the received signal 11a, the two waveforms overlap as shown in the time chart of FIG. The OR circuit output 12a never drops to zero, and even if the transmission speed is increased, there is no risk of demodulation errors occurring.

〔Effect of the invention〕

As explained above, according to the present invention, it is not necessary to manipulate the waveform of the received signal by a delay circuit, and the timing setting range is not narrowed due to waveform deterioration, and the timing setting range can be set wider than before. Even if the transmission speed increases, the received signal can be demodulated without the risk of demodulation errors, and it is highly effective as a demodulation circuit for this type of communication system that requires high-speed transmission.

[Brief explanation of the drawing]

1 and 2 are a block diagram and a time chart showing a conventional demodulation circuit in this type of communication system, and FIGS. 3 and 4 are a block diagram and a time chart showing a circuit according to an embodiment of the present invention. . 11... Received signal input terminal, lla... Received signal,
12...OR circuit, 12a...OR output, 13
...first flip-flop, 13a...Q output,
14... Clock input terminal, 14a... Clock input, 15... Second flip-flop, 15a...
Q output, 16...Logic inversion circuit, 16a...Logic inversion output, 17...Demodulated signal output terminal. talent f talent 2 mouth-

Claims (1)

[Claims] In a communication system demodulation circuit that converts one of the logic l and 0 of the original signal to lO or 01 and the other to 11.00 and transmits it, when the received signal is divided into 2 bits and the destination bit is 0. is a circuit that keeps the output at 1 for the next cycle,
A demodulation circuit comprising: a circuit for calculating the logical sum of the circuit output and the received signal; and a circuit for detecting 1.0 of a bit after the output of the logical sum circuit.