JPS60231319A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60231319A JPS60231319A JP59086633A JP8663384A JPS60231319A JP S60231319 A JPS60231319 A JP S60231319A JP 59086633 A JP59086633 A JP 59086633A JP 8663384 A JP8663384 A JP 8663384A JP S60231319 A JPS60231319 A JP S60231319A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- region
- semiconductor
- silicon layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02683—Continuous wave laser beam
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02598—Microstructure monocrystalline
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02691—Scanning of a beam
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法に係り、特に非晶質の絶
縁物基体上に、半導体装置を形成するための単結晶半導
体層を形成する工程を含む半導体装置の製造方法の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular to forming a single crystal semiconductor layer for forming a semiconductor device on an amorphous insulating substrate. The present invention relates to an improvement in a method for manufacturing a semiconductor device including a manufacturing process.
Ｔｂｌ 技術の背景
近時、分離耐圧が高く且つ寄生容量が小さい利点を持つ
誘電体（絶縁層）分離構造の半導体集積回路装置（ＩＣ
）が提供されている。又半導体ＩＣの高集積化を図るた
めに、半導体ＩＣ上に絶縁膜を介して更に半導体ＩＣを
積層する三次元ＩＣが注目され始めている。Tbl Technology background In recent years, semiconductor integrated circuit devices (ICs) with dielectric (insulating layer) isolation structures have been developed which have the advantages of high isolation voltage and low parasitic capacitance.
) are provided. Furthermore, in order to achieve higher integration of semiconductor ICs, three-dimensional ICs in which semiconductor ICs are further stacked on top of semiconductor ICs with an insulating film interposed therebetween are beginning to attract attention.
（Ｃ） 従来技術と問題点
上記誘電体分離構造及び三次元構造の半導体ＩＣにおい
ては、非晶質の絶縁物基体即ち絶縁膜上に単結晶半導体
島状領域が設けられ、この単結晶半導体島状領域上に半
導体装置が形成される。(C) Prior Art and Problems In the semiconductor ICs with the dielectric isolation structure and the three-dimensional structure described above, a single crystal semiconductor island-like region is provided on an amorphous insulator substrate, that is, an insulating film, and this single crystal semiconductor island A semiconductor device is formed on the shaped region.
上記単結晶半導体島状領域は絶縁股上に成長せしめられ
た多結晶半導体層を単結晶化することによって形成され
、この際用いられるのが、レーザ。The single-crystal semiconductor island region is formed by single-crystallizing a polycrystalline semiconductor layer grown on an insulating layer, and a laser is used at this time.
電子線、熱線等のエネルギー線照射による単結晶化技術
である。This is a single crystallization technology that uses energy rays such as electron beams and heat rays.
この単結晶化技術において重要なのは形成された単結晶
島状領域が結晶粒界を持たない完全な単結晶層よりなる
ことであり、其の為には多結晶半導体島状領域をエネル
ギー線照射によって加熱溶融し再結晶させる際の冷却が
、溶融された半導体層の一個所からその周囲に向かって
順次なされて行くことである。What is important in this single crystallization technology is that the formed single crystal island region consists of a complete single crystal layer without grain boundaries, and for this purpose, the polycrystalline semiconductor island region is irradiated with energy rays. Cooling during heating and melting and recrystallization is performed sequentially from one location to the periphery of the molten semiconductor layer.
初期の単結晶化技術においては、多結晶半導体層に直に
エネルギー線を照射する方法が用いられていた。即ち例
えば多結晶シリコン層に対して吸収効率の高いアルゴン
（Ａｒ）レーザ・ビームで該多結晶シリコン層上を走査
し、該多結晶シリコン層を順次溶融し再結晶させていた
が、この方法においては溶融されたシリコン層の冷却が
その周囲からも多くなされるので、生成された単結晶シ
リコン層の周辺部に結晶粒界が多発し、半導体装置を形
成することが可能な領域が極めて狭く制限されるという
問題があった。In early single crystallization technology, a method was used in which a polycrystalline semiconductor layer was directly irradiated with energy rays. That is, for example, an argon (Ar) laser beam, which has a high absorption efficiency for a polycrystalline silicon layer, is scanned over the polycrystalline silicon layer to sequentially melt and recrystallize the polycrystalline silicon layer. Since the molten silicon layer is cooled mostly from its surroundings, many grain boundaries occur in the periphery of the generated single-crystal silicon layer, which limits the area in which semiconductor devices can be formed to be extremely narrow. There was a problem with being exposed.
そこで上記問題を解消するべく提供されたのが傍熱型レ
ーザ・ヒーティング（Ｉｎｄｉｒｅｃｔ Ｌａ５ｅｒ
Ｈｅａｔｉｎｇ）法等と呼ぶ間接加熱の方法である。Therefore, indirect laser heating (Indirect La5er) was provided to solve the above problem.
This is an indirect heating method called a heating method or the like.
第１図は従来の傍熱型レーザ・ヒーティング法による単
結晶シリコン島状領域の形成方法を示す模式断面図であ
る。FIG. 1 is a schematic cross-sectional view showing a method of forming a single crystal silicon island region by a conventional indirect laser heating method.
この図に示すように従来は、
０．５〜１ 〔μｍ〕程度の厚さを有する非晶質の絶縁
物基体例えば二酸化シリコン（ＳｉＯ□）絶縁膜基体１
上に、単結晶化しようとする４０００〜５０００ （人
〕程度の厚さ、所望の幅及び長さを有する多結晶シリコ
ン島状領域２を形成し、
該多結晶シリコン島状領域の表面に、例えば窒化シリコ
ン（ＳｉｉＮｔ）膜とＳｉｎ、膜との積層構造よりなる
分離用絶縁膜（セパレーション・キャップと称する）３
を形成し、
該Ｓｉｎｇ絶縁膜基体１上にレーザ吸収層として、前記
多結晶シリコン島状領域２を覆う厚さ２０００〜２５０
０ Ｃ人〕程度の多結晶シリコン層４を形成し、
該多結晶シリコン層４における前記多結晶シリコン島状
ｗ４域２の上部領域を該多結晶シリコン島状領域２の幅
よりも大きいビーム・スポット径を有する所望強度のＡ
ｒレーザ・ビームＬで走査して該多結晶シリコン層４を
高温に加熱し、該高温に加熱された多結晶シリコン層４
を熱源にして該多結晶シリコン島状領域２を間接的に加
熱溶融して単結晶化し、
しかる後図示しないが多結晶シリコン層４及び分離用絶
縁膜３を除去して、該絶縁膜１上に単結晶シリコン島状
領域を形成していた。As shown in this figure, conventionally, an amorphous insulating substrate, for example, silicon dioxide (SiO□) insulating film substrate 1 having a thickness of about 0.5 to 1 μm is used.
A polycrystalline silicon island region 2 having a thickness of about 4,000 to 5,000 micrometers and a desired width and length is formed on the surface of the polycrystalline silicon island region 2 to be monocrystallized. For example, an isolation insulating film (referred to as a separation cap) 3 consisting of a laminated structure of a silicon nitride (SiiNt) film and a Sin film.
A laser absorption layer with a thickness of 2000 to 250 nm is formed on the Sing insulating film substrate 1 to cover the polycrystalline silicon island region 2.
A polycrystalline silicon layer 4 having a thickness of about 0 C) is formed, and the upper region of the polycrystalline silicon island region W4 2 in the polycrystalline silicon layer 4 is exposed to a beam larger than the width of the polycrystalline silicon island region 2. A of desired intensity with spot diameter
r The polycrystalline silicon layer 4 is heated to a high temperature by scanning with a laser beam L, and the polycrystalline silicon layer 4 heated to the high temperature is
The polycrystalline silicon island region 2 is indirectly heated and melted using a heat source to form a single crystal, and then, although not shown, the polycrystalline silicon layer 4 and isolation insulating film 3 are removed, and the polycrystalline silicon layer 4 and the isolation insulating film 3 are removed. Single-crystal silicon island-like regions were formed.
かかる傍熱型レーザ・ヒーティング法においては、溶融
されたシリコン島状領域の上部及び側面が加熱源となっ
た多結晶シリコン層４で覆われていることによって、該
シリコン島状領域２の冷却がその中心近傍から優先して
行われるので、周辺部から発生する結晶粒界をなくして
良質の単結晶シリコン島状領域が形成される。In this indirect laser heating method, the top and side surfaces of the melted silicon island region are covered with a polycrystalline silicon layer 4 that serves as a heating source, thereby cooling the silicon island region 2. Since this is performed preferentially starting from the vicinity of the center, grain boundaries generated from the periphery are eliminated, and a high-quality single-crystal silicon island region is formed.
然しなから上記従来方法においては、単結晶化しようと
する多結晶シリコン島状領域２が、レーザ・ビームの吸
収効率が悪いために高温に加熱されない絶縁膜４上に直
に載設されているために、冷却が他部より比較的速く行
われる該島状領域の下面の周辺部５に、溶融されたシリ
コン島状領域が再結晶する際の核が発生し勝ちであり、
そのため一基板上の完全な単結晶シリコン島状領域の形
成歩留りが８０〜１００ Ｃ％〕の範囲でばらつくとい
う問題があった。However, in the conventional method described above, the polycrystalline silicon island region 2 to be made into a single crystal is placed directly on the insulating film 4 which is not heated to a high temperature due to poor laser beam absorption efficiency. Therefore, nuclei are likely to occur when the molten silicon island region recrystallizes in the peripheral region 5 of the lower surface of the island region where cooling is performed relatively faster than other regions.
Therefore, there is a problem in that the yield of forming complete single-crystal silicon island regions on one substrate varies within a range of 80 to 100 C%.
（（１） 発明の目的
本発明は上記傍熱型レーザ・ヒーティング法等の間接加
熱方式の単結晶化技術において、完全な単結晶半導体島
状領域の形成歩留りのばらつきをさらに減少せしめる目
的でなされたものである（ｅｌ 発明の構成
上記本発明の目的は、絶縁物基体上に熱伝導体として寄
与する第１の層を設け、該第１の層上に単結晶化しよう
とする半導体島状領域を形成し、次いで該半導体島状領
域の上表面及び側面を覆いエネルギー線吸収体として寄
与する第２の層を形成し、該第２の層上からエネルギー
線を照射して該半導体島状領域を単結晶化する工程を含
む本発明による半導体装置の製造方法によって達成され
る。((1) Purpose of the Invention The purpose of the present invention is to further reduce variations in the formation yield of perfect single crystal semiconductor island regions in indirect heating single crystallization technology such as the indirect laser heating method described above. The object of the present invention is to provide a first layer that serves as a thermal conductor on an insulating substrate, and to form a semiconductor island to be single crystallized on the first layer. A second layer is formed to cover the upper surface and side surfaces of the semiconductor island-like region and serve as an energy ray absorber, and energy rays are irradiated from above the second layer to form a semiconductor island. This is achieved by the method of manufacturing a semiconductor device according to the present invention, which includes the step of single-crystallizing a shaped region.
即ち本発明においては、単結晶化しようとする半導体島
状領域と該島状領域が載設される絶縁物基体との間に熱
転ＮＮを介在せしめ、該半導体島状領域と該熱伝導層を
覆うエネルギー線吸収層に発生した熱が、該熱伝導層を
介して該半導体島状領域の下部からも供給されるように
することによって、間接的に加熱溶融された該半導体島
状領域が冷却単結晶化される際の結晶核が、該半導体島
状領域の中心近傍のみに発生するようにしたものである
。That is, in the present invention, a heat transfer NN is interposed between the semiconductor island region to be single crystallized and the insulator substrate on which the island region is mounted, and the semiconductor island region and the thermally conductive layer are The heat generated in the energy ray absorbing layer covering the semiconductor island region is also supplied from the lower part of the semiconductor island region through the heat conductive layer, so that the semiconductor island region that is indirectly heated and melted is heated and melted. Crystal nuclei during cooling single crystallization are generated only near the center of the semiconductor island region.
かくて単結晶半導体島状領域周辺部から結晶粒界が発生
することが防止され、完全な単結晶半導体島状領域の形
成歩留りのばらつきが殆ど無くなる。In this way, the generation of crystal grain boundaries from the peripheral portion of the single crystal semiconductor island region is prevented, and there is almost no variation in the formation yield of complete single crystal semiconductor island regions.
ｆｆ） 発明の実施例
以下本発明の要旨を、単結晶シリコン島状領域を形成す
る際の実施例について、図を参照して具体的に説明する
。ff) Embodiments of the Invention Below, the gist of the present invention will be specifically explained with reference to the drawings, with regard to embodiments for forming single-crystal silicon island regions.
第２図（ａ）〜（ｅ）は一実施例の工程断面図、第３図
は他の一実施例の工程断面図である。FIGS. 2(a) to 2(e) are process sectional views of one embodiment, and FIG. 3 is a process sectional view of another embodiment.
第２図（ａｌ参照
第１の実施例においては、図示しないシリコン基板面等
に通常の方法で形成された０、５〜１〔μｍ〕程度の厚
さの例えば５ｉ０２絶縁膜基体１１上に、通常の減圧化
学気相成長法で熱伝導層として機能する例えば厚さ５０
０〜１０００ （人〕程度の第１の多結晶シリコン層１
２を形成し、次いで同じく減圧化学気相成長法により該
第１の多結晶シリコン層１２上に第１の絶縁膜として機
能し、且つ熱の伝導率が比較的大きい１００ （人〕程
度の窒化シリコン膜１３を形成し、次いで同じく減圧化
学気相成長法により該窒化シリコン膜１３上に例えば厚
さ４０００〜５０００ （人〕程度の第２の多結晶シリ
コン層を形成し、次いで通常ドライ・エツチング手段に
より該第２の多結晶シリコン層のパターンニングを行っ
て、単結晶化しようとする例えば幅２０ （μｍ〕長さ
６０ （μｍ〕程度の多結晶シリコン島状領域１４を形
成する。In the first embodiment, for example, a 5i02 insulating film substrate 11 having a thickness of about 0.5 to 1 [μm] is formed on a silicon substrate (not shown) by a conventional method. For example, the thickness of
First polycrystalline silicon layer 1 of about 0 to 1000 (people)
2 is formed on the first polycrystalline silicon layer 12 by the same low-pressure chemical vapor deposition method, and then a nitrided film of about 100 (layers), which functions as a first insulating film and has a relatively high thermal conductivity, is formed on the first polycrystalline silicon layer 12 by the same low-pressure chemical vapor deposition method. A silicon film 13 is formed, and then a second polycrystalline silicon layer with a thickness of, for example, about 4,000 to 5,000 people is formed on the silicon nitride film 13 by the same low-pressure chemical vapor deposition method, and then usually dry etched. The second polycrystalline silicon layer is patterned by a method to form a polycrystalline silicon island region 14 having a width of about 20 (μm) and a length of about 60 (μm), which is to be made into a single crystal.
第２図（ｂ）参照
次いで熱酸化法により、該多結晶シリコン島状領域１４
の表面に分離用絶縁膜（セパレーション・キャップ）と
して機能する厚さ例えば３５０〜４００〔人〕程度のＳ
ｉＱ、膜１５を形成し、次いで所定の選択エツチング手
段により表出している窒化シリコン膜１３を除去する。Referring to FIG. 2(b), the polycrystalline silicon island region 14 is then heated by a thermal oxidation method.
A layer of S with a thickness of, for example, about 350 to 400 [people], which functions as an isolation insulating film (separation cap) on the surface of
iQ, the film 15 is formed, and then the exposed silicon nitride film 13 is removed by a predetermined selective etching means.
第２図（Ｃ）参照
次いで前記同様減圧化学気相成長法により該多結晶シリ
コン島状領域１４が配設されている第１の多結晶シリコ
ン層１２上に、Ａｒレーザ吸収層として機能する厚さ例
えば２０００〜２５００ （人〕程度の第３の多結晶シ
リコン層１６を形成する。Referring to FIG. 2(C), the first polycrystalline silicon layer 12 on which the polycrystalline silicon island-like region 14 is formed is then deposited to a thickness that functions as an Ar laser absorption layer by low-pressure chemical vapor deposition in the same manner as described above. For example, the third polycrystalline silicon layer 16 is formed to have a thickness of about 2,000 to 2,500 people.
第２図（ｄ）参照
次いで該第３の多結晶シリコン層１６上に図示しない反
射防止膜を形成した後、該第３の多結晶シリコン層１６
における該多結晶シリコン島状領域１４の上部領域を、
該多結晶シリコン島状領域１４の幅よりも大きなビーム
・スポット径例えば５０〔μｍ〕程度のビーム・スポッ
ト径を有し１０ （Ｗ）程度の出力を有するＡｒレーザ
・ビームＬで、該多結晶シリコン島状領域１４の長さ方
向に順次走査する。Referring to FIG. 2(d), after forming an antireflection film (not shown) on the third polycrystalline silicon layer 16, the third polycrystalline silicon layer 16 is
The upper region of the polycrystalline silicon island region 14 in
An Ar laser beam L having a beam spot diameter larger than the width of the polycrystalline silicon island region 14, for example, about 50 [μm] and an output of about 10 (W), is used to remove the polycrystalline silicon. The silicon island region 14 is sequentially scanned in the length direction.
（走査速度は１０ ［ｃｍ／５ｅｃ）程度）上記構造に
おいては、シリコン島状領域１４の上部及び側面がレー
ザ吸収層である第３の多結晶シリコン層１６に覆われ且
つ下部に熱伝導率の大きい第１の多結晶シリコン層１２
が配設されているので、上記レーザ・ビーム照射によっ
て溶融されたシリコン島状領域１４は該島状領域を包む
これら給熱部から離れた中心部近傍から周辺部に向かっ
て順次冷却され単結晶化されて行く。かくして結晶粒界
が存在しない完全な単結晶島状領域２４が形成される。(Scanning speed is approximately 10 cm/5 ec) In the above structure, the upper and side surfaces of the silicon island region 14 are covered with the third polycrystalline silicon layer 16 which is a laser absorption layer, and the lower part is covered with a layer having thermal conductivity. Large first polycrystalline silicon layer 12
, the silicon island-like region 14 melted by the laser beam irradiation is sequentially cooled from the vicinity of the center away from the heat supply parts surrounding the island-like region toward the periphery to form a single crystal. becoming more and more In this way, a complete single-crystal island region 24 without grain boundaries is formed.
なお該実施例において完全な単結晶島状領域の形成歩留
りの変動は、−基板当たり９５〜１００〔％〕の範囲に
抑えられた。In this example, the variation in the formation yield of complete single-crystal island regions was suppressed to a range of 95 to 100% per -substrate.
第２図Ｔｅｌ参照
次いで通常のドライ・エツチング手段により図示しない
反射防止膜、第３の多結晶シリコン層１６及び５ｉＱ２
膜（分離用絶縁膜）１５を除去し、次いで単結晶島状領
域２４の周囲に表出している第１の多結晶シリコン層１
２を除去し、ＳｉＯ□絶縁膜基体１１上に窒化シリコン
絶縁膜１３及び第１の多結晶シリコン層１２を下部に有
する単結晶シリコン島状領域２４を形成する。Referring to FIG. 2, an anti-reflection film (not shown), third polycrystalline silicon layer 16 and 5iQ2 are then etched by ordinary dry etching means.
The film (isolation insulating film) 15 is removed, and then the first polycrystalline silicon layer 1 exposed around the single crystal island region 24 is removed.
2 is removed, and a single-crystal silicon island region 24 having a silicon nitride insulating film 13 and a first polycrystalline silicon layer 12 underneath is formed on the SiO□ insulating film substrate 11.
以後図示しないが、このようにして−Ｓｉｎ。Although not shown hereafter, in this way -Sin.
絶縁膜基体１１上に多数個形成された単結晶シリコン島
状領域２４に通常の方法で半導体装置が形成される。Semiconductor devices are formed on a large number of single crystal silicon island regions 24 formed on the insulating film base 11 by a conventional method.
第３図は第２の実施例における単結晶化に際しての構造
を示したものである。同図において１１はＳｉＯ□絶縁
膜基体、１２は厚さ５００〔人〕程度の第１の多結晶シ
リコン層、１４は単結晶化される厚さ４０００〜５００
０ （人〕１幅２０（、ｃａｍ）、長さ６０〔μｍ〕程
度の多結晶シリコン島状領域、１６は第３の多結晶シリ
コン層、２１は厚さ３００〔人〕程度の第１のＳｉＯ２
絶縁膜、２２は厚さ３５０〜４００〔人〕程度の第２の
Ｓｉｎ、絶縁膜、２３は厚さ８００〔人〕程度の窒化シ
リコン膜、ＬはＡｒレーザ・ビームを表している。FIG. 3 shows the structure upon single crystallization in the second embodiment. In the same figure, 11 is a SiO□ insulating film substrate, 12 is a first polycrystalline silicon layer with a thickness of about 500 [people], and 14 is a polycrystalline silicon layer with a thickness of 4000 to 500 cm, which is made into a single crystal.
0 (person) 1 a polycrystalline silicon island-like region with a width of 20 (cam) and a length of about 60 [μm], 16 a third polycrystalline silicon layer, and 21 a first polycrystalline silicon layer with a thickness of about 300 [cam]. SiO2
22 is a second Si insulating film with a thickness of about 350 to 400 [people], 23 is a silicon nitride film with a thickness of about 800 [people], and L represents an Ar laser beam.
なおここで第１の多結晶シリコン層１２は前記実施例開
襟熱伝導層として機能し、第１．第２のＳｉＱ、絶縁膜
２１．２２は分離絶縁層及び保温層として機能し、窒化
シリコン膜２３は第３の多結晶シリコン層の剥離防止層
として機能し、第３の多結晶シリコン層１６は前記実施
例同様レーザ吸収層として機能する。かかる構造におい
ても、溶融したシリコン島状領域１４は、周囲が保温層
として機能する第１．第２のＳｉｎ、絶縁膜２１．２２
を介して第１の多結晶シリコン層１２．第３の多結晶シ
リコン層１６等よりなる給熱層によって囲まれているの
で、冷却は該シリコン島状領域１４の中心部近傍から始
まり、該中心部近傍を核にして周辺部に向かって単結晶
層が成長する。従って結晶粒界のない完全な単結晶シリ
コン島状領域が形成される。Note that here, the first polycrystalline silicon layer 12 functions as the open-necked heat conductive layer in the embodiment described above, and the first polycrystalline silicon layer 12 functions as the open-necked heat conductive layer in the embodiment described above. The second SiQ and insulating films 21 and 22 function as an isolation insulating layer and a heat insulation layer, the silicon nitride film 23 functions as a peeling prevention layer for the third polycrystalline silicon layer, and the third polycrystalline silicon layer 16 As in the previous embodiment, it functions as a laser absorption layer. In this structure as well, the molten silicon island region 14 is surrounded by a first layer that functions as a heat insulating layer. Second Sin, insulating film 21.22
via the first polycrystalline silicon layer 12. Since it is surrounded by a heat supply layer made of the third polycrystalline silicon layer 16 and the like, cooling starts near the center of the silicon island region 14 and continues toward the periphery with the center near the core as a core. A crystal layer grows. Therefore, a complete single-crystal silicon island region without grain boundaries is formed.
なお上記実施例においては、シリコンよりなるエネルギ
ー線吸収層と該シリコン層に高効率で吸収されるＡｒレ
ーザとの組合せでシリコン島状領域の加熱を行ったが、
該エネルギー線吸収層とエネルギー線との組合せは上記
実施例に限られるものではない。但し吸収効率は出来る
だけ高い事が望ましい。In the above example, the silicon island region was heated using a combination of an energy ray absorption layer made of silicon and an Ar laser that is absorbed by the silicon layer with high efficiency.
The combination of the energy ray absorbing layer and energy rays is not limited to the above embodiments. However, it is desirable that the absorption efficiency be as high as possible.
又エネルギー線にはレーザ以外に、電子線、熱線等も用
いられる。In addition to lasers, electron beams, heat rays, etc. can also be used as energy beams.
なお又本発明は、絶縁物基体上にシリコン以外の半導体
単結晶島状領域を形成する際にも適用され１す
る。Furthermore, the present invention can also be applied to the formation of single crystal island regions of semiconductors other than silicon on an insulating substrate.
（ｇ） 発明の詳細
な説明したように本発明によれば、絶縁物基体上に、周
辺部に結晶粒界が形成されない完全な単結晶半導体島状
領域を極めて変動の少ない高歩留りで形成できる。(g) Detailed Description of the Invention According to the present invention, a perfect single-crystal semiconductor island region in which no crystal grain boundaries are formed in the periphery can be formed on an insulating substrate at a high yield with extremely little fluctuation. .
従って本発明は、誘電体分離構造あるいは三次元構造の
半導体集積回路装置を製造する際に有効である。Therefore, the present invention is effective when manufacturing a semiconductor integrated circuit device having a dielectric isolation structure or a three-dimensional structure.
第１図は従来の単結晶島状領域形成方法を示す模式断面
図、第２図は本発明の方法における一実施例の工程断面
図で、第３図は同じく他の一実施例の工程断面図である
。
図において、１１は５ｉｎ２絶縁膜基体、１２は第１の
多結晶シリコン層、１３は窒化シリコン膜、１４ば多結
晶シリコン島状領域、１５は５ｉＱｚ膜、１６は第３の
多結晶シリコン層、ＬはＡｒレーザ・ビームをしめす。
煽弁理士松岡宏四部
２
第 １ 園
第２ 図FIG. 1 is a schematic cross-sectional view showing a conventional method for forming single-crystal island regions, FIG. 2 is a process cross-sectional view of one embodiment of the method of the present invention, and FIG. 3 is a process cross-section of another embodiment. It is a diagram. In the figure, 11 is a 5in2 insulating film base, 12 is a first polycrystalline silicon layer, 13 is a silicon nitride film, 14 is a polycrystalline silicon island region, 15 is a 5iQz film, 16 is a third polycrystalline silicon layer, L indicates an Ar laser beam. Instigated Patent Attorney Hiroshi Matsuoka Part 2 1st Garden 2nd Diagram
Claims (1)
、該第１の層上に単結晶化しようとする半導体島状領域
を形成し、次いで該半導体島状領域の上表面及び側面を
覆いエネルギー線吸収体として寄与する第２の層を形成
し、該第２の層上がらエネルギー線を照射して該半導体
島状領域を単結晶化する工程を有することを特徴とする
半導体装置の製造方法。A first layer serving as a heat conductor is provided on an insulating substrate, a semiconductor island region to be monocrystalized is formed on the first layer, and then the upper surface and side surfaces of the semiconductor island region are formed. A semiconductor device comprising the steps of: forming a second layer that covers and serves as an energy ray absorber; and irradiating the second layer with energy rays to single-crystallize the semiconductor island region. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59086633A JPH0670964B2 (en) | 1984-04-28 | 1984-04-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59086633A JPH0670964B2 (en) | 1984-04-28 | 1984-04-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60231319A true JPS60231319A (en) | 1985-11-16 |
| JPH0670964B2 JPH0670964B2 (en) | 1994-09-07 |
Family
ID=13892425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59086633A Expired - Lifetime JPH0670964B2 (en) | 1984-04-28 | 1984-04-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0670964B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264072A (en) * | 1985-12-04 | 1993-11-23 | Fujitsu Limited | Method for recrystallizing conductive films by an indirect-heating with a thermal-conduction-controlling layer |
-
1984
- 1984-04-28 JP JP59086633A patent/JPH0670964B2/en not_active Expired - Lifetime
Non-Patent Citations (1)
| Title |
|---|
| APPL PHYS LETT=1984 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264072A (en) * | 1985-12-04 | 1993-11-23 | Fujitsu Limited | Method for recrystallizing conductive films by an indirect-heating with a thermal-conduction-controlling layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0670964B2 (en) | 1994-09-07 |
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