JPS60229530A - Clock stop protecting circuit - Google Patents

Abstract

PURPOSE:To evade a trouble due to a clock stop by inputting an oscillation output to a dynamic logical circuit which uses an MOS-Tr in case of the clock stop as a substitute for a clock. CONSTITUTION:A detecting circuit 1 detects the stop of the clock to be inputted to the logical circuit from whether the clock appears at an input terminal 5 or not. A time constant circuit 2 receives the output of the detecting circuit 1 and detects an elapse of constant time after the clock stops. A switching circuit 3 inputs the clock from the terminal 5 and the output of an oscillation circuit 4 and either of said two signals is selected according to the output state of the time constant circuit 2 and outputted to a terminal 6. This selection is so made that the clock when the clock is inputted or the output of the oscillation circuit 4 when the clock stops is selected. Further, the oscillation circuit 4 outputs a signal of frequency higher than a necessary frequency for holding data by the logical circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a clock stop protection circuit that protects a dynamic logic circuit using MO3+- transistors when the clock is stopped.

[Prior art]

In dynamic logic circuits using MOS transistors, there is a period of time during which information is retained in the form of charges stored on the circuit, and this time is sufficiently longer than the period during which information is lost or errors occur due to discharge of the charges. It has to be a short time. Therefore, dynamic logic circuits must always be given new information in the form of charges within a certain period of time, and a clock must always be supplied to them.

Now, assuming that the clock has stopped for some reason,
In addition to information loss or errors, the discharge of stored charge causes the potential of the circuit in which it was stored to change between logical "1" and "0" levels, that is, power supply voltage and ground. There is a possibility that the voltage will be at an intermediate level between the two voltages.

When the potential of a certain circuit reaches such an intermediate level state,
Undesirable conditions may occur in circuit elements connected to the circuit. For example, in a logic circuit using complementary MOS transistors, when the gate input potential becomes an intermediate potential between the power supply voltage and the ground voltage, the P channel and N
Circulation current flows between the power supply and ground through one transistor of the channel, significantly increasing the current consumption of the circuit, and in some cases, there is a risk that the circuit elements may deteriorate due to heat generation.

[Summary of the invention]

The present invention has been made in view of the above problems, and in a dynamic logic circuit using MOS transistors, when the clock is stopped, an oscillation output is input instead of the clock, thereby eliminating the inconvenience caused by the clock stopping. The purpose of this invention is to provide a two-protection circuit that can avoid clock stoppage.

[Embodiments of the invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

1 and 2 illustrate a clock stop protection circuit according to one embodiment of the present invention. In Figure 1, l is MO3+-
This detection circuit detects that the clock to be input to the dynamic logic circuit using transistors has stopped, and detects the presence or absence of the clock applied to the clock input terminal 5. 2 is a time constant circuit which receives the output of the detection circuit 1 and detects that a certain period of time has elapsed after the clock has stopped.

Reference numeral 3 denotes a switching circuit, which uses the clock input to the clock application terminal 5 and the output of the oscillation circuit 4, and selects one of the two input signals depending on the output state of the time constant circuit 2. Select and output to output terminal 6. In this selection, if the clock is being input, the clock is used as iM fR, and if the clock is stopped, the output of the oscillation circuit 4 is used as iM fR. It is also assumed that the oscillation circuit 4 outputs a signal with a frequency higher than the frequency required for data retention in the logic circuit.

FIG. 2 shows a more specific configuration of the above circuit. In the figure, 5 is a clock application terminal, 7 is a delay circuit, and 8 is an exclusive OR circuit. A detection circuit 1 is configured. 9. 10 is an inverter circuit using complementary transistors, which constitutes a time constant circuit 2 together with a capacitor 11 and an inverter 12. 13
．． 14,15°16 are inverters and NAND circuits,
These constitute the switching circuit 3. 17.1B, 19.2
0 is an inverter, and these constitute an output circuit 21.

Output circuit 21. NAND circuits 15, 16. and inverters 22 and 23 are connected in odd number stages to form a ring oscillator 24. Note that if the number of stages of the ring oscillator 24 is an odd number, an additional inverter may be added between the inverters 22 and 23 in order to adjust the oscillation frequency.

Next, the operation will be explained.

In this circuit, when a clock is applied to the clock application terminal 5, one input of the exclusive OR circuit 8 is delayed for a certain period of time by the delay circuit 7, so that the two inputs of the exclusive OR circuit 8 are are not the same, so the circuit 8 will output pulses continuously. The clock goes to (t11), and the terminal 5 goes to “I(” level
``I-1'') or ``■,'' level (hereinafter referred to as ``I7'')
”), both inputs of the exclusive OR circuit 8 become the same level, and the output of the circuit 8 becomes “I
, becomes ゛.

Now, in the inverter circuit, if the current drive capability of the P-channel transistor 9 is made sufficiently smaller than the current drive capability of the N-channel transistor 10, the current drive capability of the P-channel transistor 9 can be made sufficiently smaller than the current drive capability of the N-channel transistor 10. While the clock is applied to the application terminal 5, the capacitor 1
The terminal voltage of 1 is "1." When the clock stops and the output of the exclusive OR circuit 8 becomes "L", the terminal voltage of the capacitor 11 rises with a time constant determined by the output voltage of the P-channel transistor and the capacitance of the capacitor 11. When this voltage exceeds the threshold voltage of the inverter 12, the output of the inverter 12 becomes "L".

Since the output of the inverter 12 is "H" while the clock is being applied, the clock is output to the output terminal 6 through the NAND circuits 14 and 15 and the inverters 17 to 20. On the other hand, when the clock stops and rises, the potential of the exclusive OR circuit 8 becomes "I", the terminal voltage of the capacitor 11 rises to 1-, and the output of the inverter 12 becomes "1".
,', the output of the inverter 13 becomes "II". Then, the ring oscillator 24 mentioned above starts oscillating, and its output is output to the output terminal 6 instead of the clock.

In this circuit as described above, the output of the oscillation circuit 24 is output when the clock stops, so the MOS
) In a dynamic logic circuit using transistors,
There is no problem of increased current consumption due to the circuit potential being at an intermediate level as in the prior art, and the reliability of the circuit is ensured.

It should be noted that the present invention is not limited to the second embodiment,
Various modifications and changes are possible; for example, the specific configuration of each circuit 1 to 4 may be different from the one described in the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, in a dynamic logic circuit using MOS transistors, when a clock stops, it is detected and an oscillation output is provided after a certain period of time. This has the effect of preventing inconveniences such as deterioration of elements due to heat generation.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of a clock stop protection circuit according to an embodiment of the present invention, and FIG. 2 is a detailed diagram of the circuit. In the figure, 1 is a clock stop detection circuit, 2 is a time constant circuit, 3 is a switching circuit, 4 is an oscillation circuit, 5 is a clock input terminal, 21 is an output circuit, and 24 is a ring oscillator. Note that the same reference numerals in FIG. 11 indicate the same or equivalent parts. Agent Masuo Oiwa Procedural Amendment (Voluntary) 1. Indication of the case: Japanese Patent Application No. 59-86824 2, Name of the invention: Clock stop protection circuit 3, Person making the amendment: Representative Hitoshi Katayama, Department within Mitsubishi Electric Corporation, 5? 1Ii Correct Detailed Description of the Invention Column 6 of the Specification in Subject, Contents of Correction (1) Correct "UP Channel Transistor 9" to "P Channel Transistor 1O" in the 6th to 7th lines of page 6 of the specification. (2) On page 6, lines 7-8, [N-channel transistor IOJ is corrected to "N-channel transistor 9J."

Claims (1)

[Claims] In a dynamic logic circuit using +llMOS transistors, a clock (41+h detection circuit) that detects that a clock to be input to the logic circuit has stopped;
A time constant circuit that detects that a certain period of time has passed since the detection circuit detects the stop of the clock I, and an oscillation circuit that generates a frequency signal higher than the frequency required for data retention in the logic circuit, and A clock stop protection circuit comprising: a switching circuit that outputs the output of the oscillation circuit to the dynamic logic circuit when receiving the clock and the output of the time constant circuit. (2) The clock stop protection circuit according to claim 1, wherein the oscillation circuit is a ring oscillator including an output circuit that inputs the output of the switching circuit to the dynamic logic circuit.