JPS60229371A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60229371A JPS60229371A JP8564084A JP8564084A JPS60229371A JP S60229371 A JPS60229371 A JP S60229371A JP 8564084 A JP8564084 A JP 8564084A JP 8564084 A JP8564084 A JP 8564084A JP S60229371 A JPS60229371 A JP S60229371A
- Authority
- JP
- Japan
- Prior art keywords
- low resistance
- layer
- resistance layer
- bevel groove
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 230000001154 acute effect Effects 0.000 claims abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 9
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
Abstract
Description
【発明の詳細な説明】 〔発明の術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Field of invention] The present invention relates to a semiconductor device.
従来、逆導通サイリスタ、非対称サイリスタ等に使用さ
れる所謂メサ形の半導体装置として第１図に示す構造の
ものが使用されている。図中１は、タングステンなどか
らなる裏面電極である。裏面電極１上には、アルミニウ
ム層２を介して低抵抗層３が形成されている。低抵抗層
３上には、異なるＳ電型の半導体層４が？！数層積層さ
れている。2. Description of the Related Art Conventionally, a so-called mesa-shaped semiconductor device used for reverse conduction thyristors, asymmetric thyristors, etc., has a structure shown in FIG. 1. In the figure, 1 is a back electrode made of tungsten or the like. A low resistance layer 3 is formed on the back electrode 1 with an aluminum layer 2 interposed therebetween. On the low resistance layer 3 is a semiconductor layer 4 of a different S type? ! Laminated in several layers.
最上層の半導体層４上にはアルミニウム等からなる表面
電極５が形成されている。また、この半導体層４０表面
の周辺領域には、アルミニウム層２に達する深さでベベ
ル溝６が形成されている。A surface electrode 5 made of aluminum or the like is formed on the uppermost semiconductor layer 4. Furthermore, in the peripheral region of the surface of this semiconductor layer 40, a bevel groove 6 is formed with a depth that reaches the aluminum layer 2.
而して、ベベル溝６の形成は、サンドブラスト法により
アルミナ粉等を半導体１１４に吹付けることにより行わ
れている。このため、ベベル溝６の開口部の縁の部分７
は、鋭角にならずに湾曲面になっている。その結果、裏
面電極１と表面電極５電流が発生する。このため、素子
特性が悪くなる問題があった。The bevel groove 6 is formed by spraying alumina powder or the like onto the semiconductor 114 using a sandblasting method. Therefore, the edge portion 7 of the opening of the bevel groove 6
is a curved surface without an acute angle. As a result, currents are generated between the back electrode 1 and the front electrode 5. For this reason, there was a problem that the device characteristics deteriorated.
（発明の目的）
本発明は、かかるる点に鑑でなされたものであり、漏れ
電流の発生を抑制して、素子特性の向上を達成した半導
体装置を提供することをその目的とするものである。(Object of the Invention) The present invention has been made in consideration of the above points, and an object of the present invention is to provide a semiconductor device that suppresses the occurrence of leakage current and improves element characteristics. be.
（発明の概要）
本発明は、半導体層の周辺領域に開口部の縁の部分が鋭
角をなし、がっ、その主面から裏面側の低抵抗層の近傍
に到達する深さでベベル溝を形成したことにより、漏れ
電流の発生を抑制して、素子特性の向上を達成した半導
体装１である。(Summary of the Invention) The present invention provides a semiconductor layer with a beveled groove formed in the peripheral region of the semiconductor layer, in which the edge portion of the opening has an acute angle, and the depth reaches from the main surface to the vicinity of the low resistance layer on the back surface side. By forming the semiconductor device 1, the occurrence of leakage current is suppressed and device characteristics are improved.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第３図は、本発明の一実施例の概略構成を示す断面図で
ある。図中１１は、タングステンなどからなる裏面電極
である。裏面電極１１上には、アルミニウム層１２を介
して低抵抗層１３が形成されている。低抵抗層１３上に
は、異なる導電型の半導体層１４が複数層積層されてい
る。最上層の半導体層１４上にはアルミニウム等からな
る表面電極１５が形成されている。また、この半導体層
１４の表面の周辺領域には、低抵抗層１３の上方１０μ
の位置に達する深さよりも浅い深さでベベル溝１６が形
成されている。ベベル溝１６内には、エンキャップ樹脂
を充填して保護１１１７が形成されている。ここで、ベ
ベル溝１６の深さを低抵抗層１３の上方１０μの位置に
達する深さよりも浅い深さとしたのは、ベベル溝１６は
、漏れ電流の発生を抑制する作用を発揮するものであり
、ベベル溝１６が１０μよりも近い距離で低抵抗層１３
に達する深さを有しても下記表から明らかなように、漏
れ電流の発生を十分に抑制できないからである。FIG. 3 is a sectional view showing a schematic configuration of an embodiment of the present invention. In the figure, 11 is a back electrode made of tungsten or the like. A low resistance layer 13 is formed on the back electrode 11 with an aluminum layer 12 interposed therebetween. A plurality of semiconductor layers 14 of different conductivity types are laminated on the low resistance layer 13. A surface electrode 15 made of aluminum or the like is formed on the uppermost semiconductor layer 14 . Further, in the peripheral region of the surface of this semiconductor layer 14, 10 μm above the low resistance layer 13 is provided.
The bevel groove 16 is formed at a depth shallower than the depth reaching the position. A protection 1117 is formed in the bevel groove 16 by filling it with encap resin. Here, the depth of the bevel groove 16 is set to be shallower than the depth reaching the position 10 μ above the low resistance layer 13 because the bevel groove 16 exerts the effect of suppressing the generation of leakage current. , when the bevel groove 16 is closer than 10μ to the low resistance layer 13
This is because, as is clear from the table below, even if the depth reaches , the occurrence of leakage current cannot be sufficiently suppressed.
表
このように構成された半導体装置２０によれば、最上層
の半導体層１４の表面の周辺領域に、低抵抗１１１３の
上方１０μの位置に達する深さよりも浅い深さでベベル
１ｌ１１６が形成されている。しかも、ベベル溝１６の
開口部の縁の部分１８は、尖鋭な鋭角になっている。こ
のため、表面電極１５と裏面電極１１間の所謂カソード
とアノード間に順方向電圧を印加すると、第２図に特性
線■にて示す如く、個れ電流の値を小さくすることがで
きる。その結果、素子特性の向上を達成できる。According to the semiconductor device 20 configured as described above, the bevel 1116 is formed in the peripheral region of the surface of the uppermost semiconductor layer 14 at a depth shallower than the depth reaching the position 10 μ above the low resistance 1113. There is. Moreover, the edge portion 18 of the opening of the bevel groove 16 has a sharp acute angle. Therefore, when a forward voltage is applied between the so-called cathode and anode between the front electrode 15 and the back electrode 11, the value of the individual current can be reduced, as shown by the characteristic line 2 in FIG. As a result, improvement in device characteristics can be achieved.
なお、ベベル溝１６の形成は、例えば次のようにして行
なう。先ず、第４図（Ａ）に示す如く、裏面電極１１上
にアルミニウム層１２を介して低抵抗層１３、半導体層
１４、表面電極１５を順次積層したちを容易する。次い
で、同図（Ｂ）に示す如く、低抵抗層１３及び半導体層
１４の周側面にノズル２１からアルミナ粉等を吹付けて
サンドブラスト法により傾斜面２２に加工する。次いで
、同図（Ｃ）に示す如く、裏面電極１１等を一体に回転
させながら、最上層の半導体層１４の表面の周辺領域に
、ブレード刃２３による加工を施し、低抵抗層１３の上
方１０μの位置に達する深さよりも浅い深さでベベル溝
１６を形成する。このようにして形成されたベベル溝１
６は、その開口部の縁の部分１８を尖鋭な鋭角にしてい
る。然る後、ベベル溝１６の内壁面に形成された破砕層
をフッ酸と硝酸からなる混酸で除去し、ベベル１１１６
内にエンキャップ樹脂を充填して保！！１１１７を形成
し、半導体装置２０を得る。Note that the bevel groove 16 is formed, for example, as follows. First, as shown in FIG. 4A, the low resistance layer 13, the semiconductor layer 14, and the front electrode 15 are sequentially laminated on the back electrode 11 with the aluminum layer 12 interposed therebetween. Next, as shown in FIG. 2B, alumina powder or the like is sprayed from a nozzle 21 onto the peripheral surfaces of the low resistance layer 13 and the semiconductor layer 14 to form an inclined surface 22 by sandblasting. Next, as shown in FIG. 2C, while rotating the back electrode 11 and the like, the peripheral region of the surface of the uppermost semiconductor layer 14 is processed with the blade 23, 10μ above the low resistance layer 13. The bevel groove 16 is formed at a depth shallower than the depth reaching the position. Bevel groove 1 formed in this way
6, the edge portion 18 of the opening has a sharp acute angle. After that, the fractured layer formed on the inner wall surface of the bevel groove 16 is removed with a mixed acid consisting of hydrofluoric acid and nitric acid, and the bevel 1116 is removed.
Fill the inside with encap resin to protect it! ! 1117 is formed to obtain the semiconductor device 20.
以上説明した如く、本発明に係る半導体装置によれば、
漏れ電流の発生を抑Ｍ して、素子特性を向上させるこ
とができるものである。As explained above, according to the semiconductor device according to the present invention,
It is possible to suppress the occurrence of leakage current and improve device characteristics.
第１図は、従来のメサ形半導体装置の概略構成を示す説
明図、第２図は、漏れ電流と印加電圧との関係を示す説
明図、第３図は、本発明の一実施例の概略構成を示す断
面図、第４図（Ａ＞乃至同図（Ｃ）は、同実施例の半導
体装置の特進方法を工程順に示す説明図である。
１１・・・層面ｆｆｉ極、１２・・・アルミニウム層、
１３・・・低抵抗層、１４・・・半導体層、１５・・・
表面電極、１６・・・ベベル溝、１７・・・保護膜、２
０−・・半導体装置、２１・・・ノズル、２２・・・傾
斜面、２３・・・ブレード刃。
５曵
第２図
第３図FIG. 1 is an explanatory diagram showing the schematic configuration of a conventional mesa-type semiconductor device, FIG. 2 is an explanatory diagram showing the relationship between leakage current and applied voltage, and FIG. 3 is a schematic diagram of an embodiment of the present invention. 4(A> to 4(C), which are cross-sectional views showing the structure, are explanatory diagrams showing the special advancement method of the semiconductor device of the same embodiment in the order of steps. 11... Layer surface ffi pole, 12... aluminum layer,
13...Low resistance layer, 14...Semiconductor layer, 15...
Surface electrode, 16... Bevel groove, 17... Protective film, 2
0--Semiconductor device, 21--Nozzle, 22--Slanted surface, 23--Blade blade. 5. Figure 2 Figure 3
Claims (1)
、該低抵抗層上に所定導電型で複数層積層された半導体
層と、最上層の該半導体層の主面の周辺領域に、開口部
の縁の部分が鋭角をなし、かつ、前記低抵抗層の上方１
０μの位置にまで達する深さより浅い深さで形成された
ベベル溝とを具備することを特徴とする半導体装置。A back electrode formed on the back side of a low resistance layer of a predetermined conductivity type, a plurality of semiconductor layers of a predetermined conductivity type stacked on the low resistance layer, and a peripheral region of the main surface of the uppermost semiconductor layer. , an edge portion of the opening forms an acute angle, and an upper part of the low resistance layer
1. A semiconductor device comprising: a bevel groove formed at a depth shallower than the depth reaching the 0μ position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8564084A JPS60229371A (en) | 1984-04-27 | 1984-04-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8564084A JPS60229371A (en) | 1984-04-27 | 1984-04-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60229371A true JPS60229371A (en) | 1985-11-14 |
Family
ID=13864420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8564084A Pending JPS60229371A (en) | 1984-04-27 | 1984-04-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60229371A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6831338B1 (en) | 1998-10-19 | 2004-12-14 | Stmicroelectronics S.A. | Power component bearing interconnections |
-
1984
- 1984-04-27 JP JP8564084A patent/JPS60229371A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6831338B1 (en) | 1998-10-19 | 2004-12-14 | Stmicroelectronics S.A. | Power component bearing interconnections |
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