JPS60226162A - Semicomductor device - Google Patents
Semicomductor deviceInfo
- Publication number
- JPS60226162A JPS60226162A JP59083113A JP8311384A JPS60226162A JP S60226162 A JPS60226162 A JP S60226162A JP 59083113 A JP59083113 A JP 59083113A JP 8311384 A JP8311384 A JP 8311384A JP S60226162 A JPS60226162 A JP S60226162A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- collector
- contact
- emitter region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 description 5
- 230000002950 deficient Effects 0.000 description 4
- 241000894006 Bacteria Species 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置、特にバイポーラ系の半導体チップ
にチェック用トランジスタを含む半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device including a check transistor in a bipolar semiconductor chip.
（従来技術）
従来、マスタスイライス方式による半導体装置の製造は
、拡散工程まで製品を作っておき、その後、配線工程の
メタライズを実施し配線工程の変更のみで多品種の半導
体装置が短納期で製造できるという所に特色がある。ま
た、拡散工程でのウェーハの良否を決める基準としては
、ウェーッ・内、及びチップ内に内部トランジスタと同
一形状のチェック用トランジスターを形成しておき、該
チェ、り用トランジスタの電気的特性をチェックし拡散
工程におけるウェーッ・の良否の判足を実施している。(Prior art) Conventionally, in the manufacture of semiconductor devices using the master slicing method, products are manufactured up to the diffusion process, and then metallization is performed in the wiring process, and a wide variety of semiconductor devices can be manufactured in a short period of time simply by changing the wiring process. It is unique in that it can be manufactured. In addition, as a criterion for determining the quality of the wafer in the diffusion process, a check transistor with the same shape as the internal transistor is formed inside the wafer and inside the chip, and the electrical characteristics of the check transistor are checked. We are conducting tests to determine the quality of wetness in the diffusion process.
第１図は従来の半導体チップの一例の平面図である。FIG. 1 is a plan view of an example of a conventional semiconductor chip.
半導体チップ１には、縦向きのトランジスタ２、横向き
のトランジスタ３が多数混在して形成され、チップの隅
にチェ、り用トランジスタ４が設けられている。A semiconductor chip 1 is formed with a large number of vertically oriented transistors 2 and horizontally oriented transistors 3, and a check transistor 4 is provided at a corner of the chip.
一般に、半導体チップ上に配置されたトランジスタは電
気的特性、パターン形状の規格化から同一形状のトラン
ジスタを配置するが、その方向に関しては、同一方向に
揃えるということは、ノくり−ンの制約から困難でアリ
、一般には、第１図に示すように、半導体チップ１上に
は同一形状のトランジスタでも縦向きのトランジスタ２
や、該トランジスタ２を９０度回転させた横向きのトラ
ンジスタ３が混存しているパターン構成になっている。In general, transistors arranged on a semiconductor chip are arranged in the same shape due to the standardization of electrical characteristics and pattern shape, but regarding the direction, it is difficult to align them in the same direction due to the constraints of the circuit. Although it is difficult, in general, as shown in FIG.
It has a pattern configuration in which transistors 3 and 3 which are oriented horizontally by rotating the transistor 2 by 90 degrees coexist.
チェック用トランジスタ４も同゛−形状で縦向きまたは
横向きで作られる。第１図には縦向きの場合を示した。The check transistor 4 also has the same shape and can be made vertically or horizontally. Figure 1 shows the vertical orientation.
第２図（ａ）、 ｔｂ）は第１図に示す縦向きトランジ
スタの平面図及びＡ−Ａ’断面図である。2(a) and 2(tb) are a plan view and a cross-sectional view taken along the line AA' of the vertically oriented transistor shown in FIG. 1.
半導体チップ１にコレクタ領域１８が設けられ、これに
接してベース領域８が設けられ、ベース領域８内にエミ
ッタ領域９が設けられ、エミッタ領域９を間にしてベー
スコンタクト１１が取出され、また高濃度コレクタ領域
６からコレクタコンタクト１０が取出される。尚、５は
酸化膜である。A collector region 18 is provided in the semiconductor chip 1, a base region 8 is provided in contact with the collector region 18, an emitter region 9 is provided within the base region 8, a base contact 11 is taken out with the emitter region 9 in between, and a base region 8 is provided in contact with the collector region 18. A collector contact 10 is taken out from the concentrated collector region 6. Note that 5 is an oxide film.
第３図（ａ）、 （ｂｌは第１図に示す横向きトランジ
スタの平面図及びＢ−Ｂ’断面図である。FIG. 3(a), (bl is a plan view and a BB' cross-sectional view of the horizontal transistor shown in FIG. 1.
半導体チップ１にコレクタ領域１８、ベース領域１４、
エミッタ領域１６が設けられ、ベース領域１４円に高濃
度ベース領域１２が設けられ、ベースコンタクト１５が
取出される。コレクタ領域１８にも高濃度コレクタ領域
１３が設けられ、コレクタコンタクト１７が取出される
。The semiconductor chip 1 includes a collector region 18, a base region 14,
An emitter region 16 is provided, a highly doped base region 12 is provided in the base region 14, and a base contact 15 is taken out. High concentration collector region 13 is also provided in collector region 18, and collector contact 17 is taken out.
このような構造の半導体チップの製造工程において、エ
ミッタ領域のパターンずれが横方向に発生した場合に、
チェック用トランジスタ４及び縦向きトランジスタ２で
は、第２図ｆａｌｌ （ｂ）から判るように、エミッタ
領域９が酸化膜５と接触してしまう。しかし、トランジ
スタ特性としては、はとんど変動せず問題となる範囲で
はない。又、チェック用トランジスタ４のような縦向き
トランジスタの場合、半導体チップ１縦方向にエミッタ
領域のパターンずれが発生した場合には、ベース抵抗を
下げる為に拡散された高濃度ベース領域７とエミ、りｌ
領域９が接触してしまい、トランジスター特性のｈＰＢ
、ＢＶＩＣＢＯ等の低下をもたらしてしまう。In the manufacturing process of a semiconductor chip with such a structure, if a pattern shift in the emitter region occurs in the lateral direction,
In the check transistor 4 and the vertical transistor 2, the emitter region 9 comes into contact with the oxide film 5, as can be seen from FIG. 2, fall (b). However, the transistor characteristics hardly change and are not in a problematic range. In addition, in the case of a vertically oriented transistor such as the check transistor 4, if a pattern misalignment of the emitter region occurs in the vertical direction of the semiconductor chip 1, the emitter region and the highly doped base region 7 diffused to lower the base resistance, Ri l
Region 9 is in contact and hPB of transistor characteristics
, BVICBO, etc.
以上、チェック用トランジスタのような縦向きトランジ
スターの場合のパターンずれ方向とトランジスタ特性の
変動について述べてきたが、半導体チップにおいてのト
ランジスタ配置は縦向きトランジスタ２．横開きトラン
ジスタ３の両方が配置されておシ、半導体チップにおい
て、横方向にエミ、り領域のパターンずれが発生した場
合の該半導体チ、グ内における縦向きトランジスタのパ
ターンずれの方向はエミッタ領域９が酸化膜５に接触す
る方向である。この時に、横向きトランジスタ３のパタ
ーンずれ方向はエミッタ領域１６が高濃度のベース領域
１２と接触する方向である。Above, we have discussed the direction of pattern deviation and fluctuations in transistor characteristics in the case of vertically oriented transistors such as check transistors. Both of the horizontally open transistors 3 are arranged in the semiconductor chip, and when a pattern shift occurs in the emitter region in the horizontal direction, the direction of the pattern shift of the vertical transistor in the semiconductor chip is in the emitter region. 9 is the direction in which the oxide film 5 is contacted. At this time, the pattern shift direction of the lateral transistor 3 is the direction in which the emitter region 16 comes into contact with the heavily doped base region 12.
この場合に、チェ、り用トランジスタ４はトランジスタ
特性の変動はほとんど問題となる範囲ではない為に、拡
散工程でのウェーハの良否の判定では良品となってしま
う。しかし、実際には、半導体チップ１には横開きのト
ランジスタ３も配置されている為に、横方向にパターン
ずれが発生した場合、横向きトランジスタ３のエミッタ
ー領域１６が高濃度のベース領域１２と接触してしまい
、トランジスタ特性のｈＦＥ、ＢＶＩＢＯ等の低下が起
カ、不良品となってしまう。In this case, since the variation in the transistor characteristics of the checking transistor 4 is within a range that hardly poses a problem, the wafer is determined to be a good product in the determination of the quality of the wafer in the diffusion process. However, in reality, since the semiconductor chip 1 also includes a laterally open transistor 3, if a pattern shift occurs in the lateral direction, the emitter region 16 of the lateral transistor 3 will come into contact with the highly doped base region 12. This causes a decrease in transistor characteristics such as hFE and BVIBO, resulting in a defective product.
以上の様に、横方向にパターンずれが発生し半導体チッ
プ１円の横向きトランジスタ３に特性変動が発生し不良
となっても、縦向きトランジスタであるチェック用トラ
ンジスタは良品となってしまい、半導体ウェーハとして
は不良品であるにもかかわらず、良品ウェーハと判定さ
れてしまい、拡散工程におけるパターンずれによる特性
変動を縦向きのチェ１．り用トランジスタ４のみでは完
全にチェックできないという欠点があった。As described above, even if pattern deviation occurs in the horizontal direction and characteristics change in the horizontal transistor 3 of one semiconductor chip and it becomes defective, the check transistor, which is a vertical transistor, becomes a good product, and the semiconductor wafer Although it is a defective wafer, it is determined to be a good wafer, and the characteristic fluctuations due to pattern deviation in the diffusion process are examined by vertically oriented check 1. There is a drawback that it cannot be completely checked using only the switching transistor 4.
（発明の目的）
本発明の目的は、上記欠点を除去し、半導体装置の製造
工程において、半導体装置の特性を不良にするようなパ
ターンずれが半導体チップのどの方向に起っても検出で
きるようなチェック用トランジスタを備えた半導体装置
を提供することにある。(Objective of the Invention) An object of the present invention is to eliminate the above-mentioned drawbacks and to enable detection of pattern deviations in any direction of a semiconductor chip that may cause defective characteristics of the semiconductor device during the manufacturing process of the semiconductor device. An object of the present invention is to provide a semiconductor device equipped with a check transistor.
（発明の構成）
本発明の半導体装置は、半導体チップに設けられたコレ
クタ領域と、該コレクタ領域に接して設けられた低濃度
のベース領域と、該ベース領域内に設けられたエミッタ
領域と、該エミッタ領域の周囲を囲む高濃度のベース領
域とから成るチェック用トランジスタを含んで構成され
る。(Structure of the Invention) A semiconductor device of the present invention includes a collector region provided on a semiconductor chip, a low concentration base region provided in contact with the collector region, and an emitter region provided within the base region. The semiconductor device includes a check transistor including a highly doped base region surrounding the emitter region.
（実施例） 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.
第４図ｆａ）〜（Ｃ）は本発明の一実施例の平面図、Ｃ
−Ｃ′断面図、Ｄ−Ｄ’断面図である。Figures 4 fa) to (C) are plan views of an embodiment of the present invention, C
-C' sectional view and DD' sectional view.
半導体チップ１９にコレクタ領域２７を設け、これに接
する低濃度のベース領域２５を設け、ベース領域２５内
にエミ、り領域２６を設ける。コレクタ領域２７に高濃
度コレクタ領域２０を設け、コレクタコンタクト２２を
取出す。A collector region 27 is provided in the semiconductor chip 19, a low concentration base region 25 is provided in contact with the collector region 27, and an emitter region 26 is provided within the base region 25. A highly concentrated collector region 20 is provided in the collector region 27, and a collector contact 22 is taken out.
この発明では、エミッタ２６の周囲を高濃度のベース領
域２１で囲むようにしたことに特長がある。この高濃度
ベース領域からベースコンタクト２３を取出す。尚２４
は酸化膜である。The present invention is characterized in that the emitter 26 is surrounded by the highly doped base region 21. A base contact 23 is taken out from this high concentration base region. Sho 24
is an oxide film.
このように構成されたチェック用トランジスタは、エミ
、り領域２６の周囲ヲ嵩濃度のベース領域２１が囲んで
いるので、半４本装置の製造工程において、エミッタ領
域２６のパターンずれが横方向に発生した場合、エミッ
タ領域２６と高濃度のベース領域２１とが触接してしま
い、トランジスタの特性変動が起る。又、縦方向にエミ
ッタ領域２６のパターンずれが発生しても横方向と同じ
様にエミッタ領域２６と、高濃度のベース領域２１とが
接触しトランジスタの特性変動が起る。従って、パター
ンずれがどの方向に発生しても、このチェック用トラン
ジスタ構造にて、完全に他のトランジスタの特性変動を
チェックすることが出来る。In the check transistor configured in this way, the emitter region 26 is surrounded by the base region 21 with a high concentration, so that the pattern deviation of the emitter region 26 in the lateral direction occurs in the manufacturing process of the half-four device. If this occurs, the emitter region 26 and the heavily doped base region 21 will come into contact with each other, causing variations in the characteristics of the transistor. Furthermore, even if a pattern shift occurs in the emitter region 26 in the vertical direction, the emitter region 26 and the heavily doped base region 21 come into contact with each other in the same way as in the horizontal direction, causing a change in the characteristics of the transistor. Therefore, no matter in which direction pattern misalignment occurs, variations in characteristics of other transistors can be completely checked using this checking transistor structure.
（発明の効果）
以上詳細に説明したように、本発明は、チェック用トラ
ンジスタのエミッタ領域の周囲を高濃度のベース領域で
囲むようにしたので半導体チップのどの方向にエミ、り
領域のパターンずれが起っても不良を検出できるという
チェック用トランジスタを備えた半導体装置を得ること
ができるという効果がある。(Effects of the Invention) As described in detail above, the present invention is characterized in that the emitter region of the check transistor is surrounded by a highly doped base region, so that the pattern shift of the emitter region in any direction of the semiconductor chip is avoided. This has the advantage that it is possible to obtain a semiconductor device equipped with a check transistor that can detect a defect even if this occurs.
第１図は従来の半導体チップの一例の平面図、第２図ｆ
ａｎ、 （ｂｌは第１図に示す縦向きトランジスタの平
面図及び断面図、第３図（ａｌ、 （ｂ）は第１図に示
す横向きトランジスタの平面図及び断面図、第４図ｆａ
）〜（Ｃ）は本発明の一実施例の平面図、Ｃ−Ｃ’断面
図、Ｄ −Ｄ’断面図である。
１・・・・・半導体チップ、２・・・・・・縦向きトラ
ンジスタ、３・・・・・・横向きトランジスタ、４・・
・チェック用トランジスタ、５・・・・・酸化膜、６・
・ 高濃度コレクタ領域、７・・・・・・菌濃度ベース
領域、８・ ・ベース領域、９・・・・・エミッタ領域
、１０・・・・コレクタコンタクト、１１・・・・・ベ
ースコンタクト、１２・・・・・高濃度ベース領域、１
３・・・・・高濃度コレクタ領域、１４・・・・・ペー
ス領ｔ１５・・・ベースコンタクト、１６・・・・エミ
ッタ領域、１７・・・ コレクタコンタクト、１８・・
・・・コレクタ領域、１９・・・・・半導体チップ、２
０・・・・・高濃度コレクタ領域、２１・・・・・・高
濃度ベース領域、２２・・・・・・コレクタコンタクト
、２３・・・・・ベースコンタクト、２４・・ 酸化膜
、２５・・・・・ベース領域、２６・・・・・エミッタ
領域、２７・・・・・コレクタ領域。
乃２閉 列３閃Figure 1 is a plan view of an example of a conventional semiconductor chip, Figure 2 f
an, (bl is a plan view and cross-sectional view of the vertical transistor shown in FIG. 1, FIG. 3 (al), (b) is a plan view and cross-sectional view of the horizontal transistor shown in FIG. 1, and FIG. 4 fa
) to (C) are a plan view, a CC' cross-sectional view, and a D-D' cross-sectional view of one embodiment of the present invention. 1... Semiconductor chip, 2... Vertical transistor, 3... Horizontal transistor, 4...
・Check transistor, 5...Oxide film, 6.
- High concentration collector region, 7... Bacteria concentration base region, 8... Base region, 9... Emitter region, 10... Collector contact, 11... Base contact, 12...High concentration base region, 1
3... High concentration collector region, 14... Pace region t15... Base contact, 16... Emitter region, 17... Collector contact, 18...
... Collector region, 19 ... Semiconductor chip, 2
0... High concentration collector region, 21... High concentration base region, 22... Collector contact, 23... Base contact, 24... Oxide film, 25... ... base region, 26 ... emitter region, 27 ... collector region. No 2 closed row 3 flash
Claims (1)
領域に接して設けられた低濃度のベース領域と、該ベー
ス領域内に設けられたエミッタ領域と、該エミッタ領域
の周囲を囲む高濃度のベース領域とから成るチェック用
トランジスタを含むこと全特徴とする半導体装置。A collector region provided on a semiconductor chip, a lightly doped base region provided in contact with the collector region, an emitter region provided within the base region, and a highly doped base region surrounding the emitter region. A semiconductor device characterized in that it includes a check transistor consisting of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59083113A JPS60226162A (en) | 1984-04-25 | 1984-04-25 | Semicomductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59083113A JPS60226162A (en) | 1984-04-25 | 1984-04-25 | Semicomductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60226162A true JPS60226162A (en) | 1985-11-11 |
Family
ID=13793144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59083113A Pending JPS60226162A (en) | 1984-04-25 | 1984-04-25 | Semicomductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60226162A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744855A (en) * | 1994-12-02 | 1998-04-28 | Mitsubishi Denki Kabushiki Kaisha | Single-poly-type bipolar transistor |
-
1984
- 1984-04-25 JP JP59083113A patent/JPS60226162A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5744855A (en) * | 1994-12-02 | 1998-04-28 | Mitsubishi Denki Kabushiki Kaisha | Single-poly-type bipolar transistor |
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