JPS60225832A - Dynamic type flat light emitting strobe device - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by generating a light emission stop signal and a light emission restart signal repeatedly and repeating the impulsive light emission of a flash discharge tube. CONSTITUTION:A main switching element connected in series with the flash discharge tube 14 is opened on the basis of the light emission stop signal generated when the charging voltage of a main capacitor 3 attains to a specific level. The main switching element is closed on the basis of the light emission restart signal generated accompanying the light emission stop signal. Those light emission stop signal and restart signal are generated repeatedly to emit impulsive light repeatedly by the discharge tube 14 during the shutter exposing operation of a camera. Further, variation in the light intensity of the discharge tube 14 is detected as variation in the voltage of the main capacitor 3, so there is no evil influence of a high-voltage light emission trigger.

Description

Detailed Description of the Invention (Technical Field) The present invention relates to a strobe device for taking strobe photography in synchronization with a shutter release. A dynamic flat light-emitting strobe device is used so that the intensity of the flash is substantially constant.

(Prior art) Generally, the number of flashes in a strobe device! The luminescence intensity of the tube is peak-like and rapidly increases from the time when luminescence starts, and one luminescence ends in an extremely short period of several milliseconds (see characteristic S in FIG. 1).

Therefore, in a camera employing a focal plane shutter, there is a problem that the strobe may emit synchronized light at a high shutter speed that is longer than the strobe synchronization time, and normal strobe photography cannot be performed. That is, at high shutter speeds that are faster than the strobe synchronization speed, the focal plane shutter does not fully open, and the slit formed by the leading and trailing curtains runs in front of the film surface.

No matter at what point the strobe device was used to emit flash light, only a portion of the film surface was exposed to the strobe light, making it impossible to take photographs with uniform exposure.

Therefore, in order to solve the above-mentioned problems, we developed a 72-t light emitting device (hereinafter referred to as "a 72-t light emitting device") that continues to emit flash light at a substantially constant intensity while the slit runs in front of the film surface. This is called a static type flat light emitting strobe device) which has already been provided (see characteristic S1 in FIG. 1). This static type flat light emitting strobe device has a series circuit of a flash discharge tube, an inductor, and a switching element on both ends of a main capacitor in which light emitting energy is stored, as described in, for example, Japanese Patent Application Laid-Open No. 55-129327. The basic circuit configuration is that a diode is connected in parallel to a series circuit formed by a flash discharge tube and an inductor. Then, the amount of light emitted from the flash discharge tube is monitored, and when the amount of light emitted from the flash discharge tube falls below a predetermined value, the switching element is turned on,
On the other hand, when the amount of light exceeds a predetermined value, the switching element is turned off to emit 7-rat light with a substantially constant light intensity. In this case, the photometer detection is carried out by making an aperture in a part of the reflector to irradiate the light emitted from the flash discharge tube onto a predetermined range of the subject, and inserting a photodiode into the aperture.
A light-receiving element such as a phototransistor is provided, and the detection is performed based on the output signal of this light-receiving element. However, since the output signal of such a Ukeiko is an output of a minute level □, its electric circuit is a circuit that can handle minute levels, and therefore, this circuit is extremely vulnerable to external noise.
The high-voltage trigger signal used to trigger the flash discharge tube sometimes caused it to malfunction. Further, the high-voltage trigger signal is transmitted to the light-receiving element via stray capacitance or the like, which may cause deterioration or malfunction of the element.

Further, in a conventional static type flat light emitting strobe p-type flash device, an impedance element such as a resistor is inserted in series with the flash discharge tube, and the light flows through this impedance element. If the discharge current of the flash discharge tube is detected and the switching element is controlled on/off based on the detection current of 5KL, the light emission loss due to the impedance element increases, and the change in the light emission intensity and the above There is also a possibility that the relationship with the change in discharge current will not match, and accurate light emission control will not be possible.

Furthermore, if the terminal voltage of the flash discharge tube is detected and the switching element is controlled on and off based on this, the transient voltage generated by turning on and off the switching element will cause the above-mentioned There is also a possibility that the on/off control of the switching element may malfunction.

Further, in conventional static flat flash flash devices, the amount of light emitted by the flash discharge tube, or a monitor value approximately equivalent to this amount of light, is compared with a preset reference value, and the monitor value exceeds the reference value. If the monitored value falls below the reference value, the switching element is turned on. Therefore, the on/off control of the switching element is performed between the upper limit value and the lower limit value, which are very close to each other, with the reference value as the boundary, so an extremely highly accurate circuit configuration is required, and the circuit configuration is complex. In addition to this, there are problems in that it is easy to malfunction due to variations in the circuit components.

(Objective) The present invention has been made in view of the above-mentioned situation, and its purpose is to control the flash discharge tube to repeatedly emit pulsed light, thereby improving the conventional static type flat light emitting device. The purpose of the present invention is to provide a flat light emitting strobe device (hereinafter referred to as a dynamic type flat light emitting strobe device) that can obtain light emitting characteristics substantially equivalent to those of a strobe p-type flash device. It is possible to achieve this with a simple circuit configuration that does not require the following.

(Summary) The dynamic type flat light emitting device of the present invention generates a signal when the charging voltage of the main capacitor reaches a predetermined voltage to open the main switching element connected in series with the flash discharge tube. The closing operation of the main switching element is performed based on the light emission restart signal generated in conjunction with the light emission stop signal. The present invention is characterized in that by repeatedly generating a signal, pulsed light emission from a flash discharge tube is repeatedly generated during a shutter exposure operation in a camera.

(Example) Next, before explaining the present invention, the extent to which the light emission interval of continuous pulsed light emission according to the present invention can be made coarser in practice will be explained in relation to the slit exposure time.

If the slit light emission interval t1 is P, then time 1
The number of times n of light emission during this period is given by the following equation.

n=/ ・・・・・・■ To simplify the theoretical formula, if the emission time width of each pulse emission is treated as "0", rnJ will be an integer value, so if t/P is an integer value: n=[/Pko...■n=[/
Pco or n=[/Pco+1...■. Here, the glass signal [a] represents the largest integer that does not exceed the real number a.

To explain the above formulas ``■'' and ``■'' with reference to the kit in Figure 2, the hatched part of the exposure time in the figure is [/P] +1 (=4), and the white part is the light emission of [/P] (=3). You can see that it has been exposed to light. Also, as mentioned above, set the emission time width to "0".
Therefore, one of the front and rear intersections of the exposure diagonal lines in FIG. 2 is not calculated.

As can be seen from Fig. 2, if we consider ideal slit exposure that is uniform over the entire screen, a uniform illumination effect can be obtained by selecting rPJ as a common divisor of rtJ, and the maximum value of rPJ is equal to rtJ. This means that it can be done as follows. However, as is well known, an actual focal plane shutter has variations in exposure time for each screen part due to differences in the running characteristics of the front and rear shutters. Now, adjust the exposure unevenness by ±dst
Consider a shutter with a guaranteed nominal exposure time T. The actual exposure time in this shutter ranges from a maximum of 2 XT (@ short 1 III) to 2 x T (longest side) depending on -d d in the screen portion. Therefore, as described above, if one light emission interval is rPJ, the number of light emissions included in each limit time is as follows. Considering the difference from the standard value [T/P] under the worst conditions, the value will be small on the shortest side, and the h value will be thicker on the longest side, so the step from the standard value on the shortest side will be To simplify the step difference equation with the reference value on the longest difference side, the emission interval P is a common divisor of FT'' and jゎ is T4. Normally, integer 877. U “t” = n (regular,), and ■
,■Equations will be different. Furthermore, from this value, we can calculate the inherent shutter exposure time unevenness, that is.

By subtracting ±dstep, the exposure value unevenness Δ11(nl, ΔEV2(n)) increased by the strobe light can be calculated.

When calculating the above formula (■) with the eigenvalue d of each shutter as 0.2 and 0.3, it becomes 5 as shown in Tables 1 to 3, and the characteristics when graphed are shown in Figure 3. It's like K. As shown in Fig. 3, if the allowable increase in unevenness when using a strobe is set to 0.1, "n" must be set to 10, that is, '
/P=n=10, and if the above tolerance is 0.2, the number of people 6. It is sufficient to choose Il and J such that −〇=4. Since the change in rTJ decreases as the number of included pulses increases, it goes without saying that rTJ should be at its nominal maximum seconds.

In other words, the exposure unevenness was kept to 0.2 EV! l
For a camera with i 1/s, the increase is 0.1000 EVK, and if you want to suppress it, '/1000 ×'/p = 1
rPJ set as 0' = '/1000° is the minimum pulse width allowed, and if it is allowed up to 0.2 Bv, rPJ is possible up to /4000.This is sufficient with the technology of the present invention. This is a number that can be easily achieved.

If the emission pulse intervals are selected as shown in Table 1, Table 2, Table 3, it can be considered that the exposure is substantially uniform.

Next, a first embodiment of the dynamic flat light emitting strobe device will be described with reference to FIGS. 4 to 10.

The dynamic flat light emitting strobe device according to this embodiment has two functions: a dynamic flat light emitting mode and a flash light emitting mode. First of all,
The configuration of main circuit 100 will be explained. This main episode N1
0OK is equipped with a step-up power supply circuit 1 made of a well-known DC-DC converter, and the negative output terminal of this circuit 1 is connected to the negative voltage supply line! .

(hereinafter abbreviated as line !0) and is grounded. The positive output end of the circuit 1 is also connected to a positive voltage supply line (hereinafter referred to as line!) via a rectifier diode 2.
(abbreviated as 1) k-connected.

Between both lines Ao and Jr, a main capacitor 3, which is the main power source for flashlight emission, is connected, and a voltage divider circuit consisting of a series circuit of 4.5 resistors is connected.
．． 5 so that the monitor voltage signal M is sent out from the connection point 5. In addition, a charging completion detection circuit consisting of a series circuit of a resistor 6 and a neon lamp 7 is connected between both 2-in A6°25, and a trigger capacitor 8 and a trigger transformer are connected at the connection point between the resistor 6 and the neon lamp 7. It is connected to the line 13o through the primary coils 9 and 9 in sequence. The connection point between the trigger capacitor 8 and the resistor 6 is connected to the anode of the trigger thyristor 10, and the cathode is connected to the line 4°K.
The gate is connected to the line AoK via the resistor 11. A resistor 12 is connected to the gate of the thyristor 10.
A light emission trigger signal A is supplied via the capacitor 13 and the capacitor 13. One end of the trigger transformer 90 secondary coil is connected to line 1oVC.

The other end is connected to a trigger electrode of a flash discharge tube 14 such as a xenon discharge tube, and one electrode of the flash discharge tube 14 is connected to line AtK. A series circuit including a resistor 15, a commutating capacitor 16, and a resistor 17 is connected in this order between the two inverters. Also, a thyristor 18 for rapidly charging the commutation capacitor 16
is provided, and the anode of the thyristor 18 is connected to the line,
The cathode is connected to the resistor 15 and the commutating capacitor 16.
The gate is connected to its own cathode via a resistor 19. Further, a rapid Marugame signal is supplied to the gate of the thyristor 18 via a resistor 20 and a capacitor 21 in sequence. The cathode of the thyristor 18 is connected to the anode of the commutation thyristor 22, and the cathode of the thyristor 22 is connected to the line! . It is connected to the. Same thyristor 22
is connected to line 4o via resistor 23,
Further, the same gate is connected to the output terminal of the OR gate 26 via the resistor 24 and the capacitor 25.
Each of the two input terminals has two systems of light emission stop signals C,
, C2 are supplied.

The other discharge electrode of the flash discharge tube 14 is connected to the connection point between the commutating capacitor 16 and the resistor 17, and is also connected to the anode of the main thyristor 27. The same main thyristor 270 cathode is line! (2) The gate is connected to the line AOVc via the resistor 28. The gate of the thyristor 27 is connected to the output terminal of an OR gate 31 via a resistor 29 and a capacitor 30 in sequence, and a light emission start signal B and a light emission restart signal B2 are supplied to two input terminals of the OR gate 31, respectively. It is now possible to do so.

A control circuit 200 described below is connected to the main circuit 100 configured in this manner.

That is, as shown in FIG. 5, the control circuit 200 includes a light emission interval setting circuit section 201, a monitor (b) tread section 202, and a side light circuit section 203.

One input terminal of the AND gate 40 is supplied with a flat light emission start signal x1 from a camera body (not shown), and the output terminal of the AND gate 40 is connected to a low level input signal (hereinafter referred to as L level). ) to high level (
It is connected to the input end of a pulse generating circuit 41 that outputs an H level pulse of a predetermined width when the output voltage rises (hereinafter referred to as an H level). The output terminal of the pulse generating circuit 41 is connected to one input terminal of the OR gate 42, and the output terminal of the OR gate 42 is connected to a light emission trigger signal A and a light emission start signal B.
, and are now sent. Or gate 4 above
The other input end of 0 is connected to the input end of the inverter 43 and the movable contact terminal of the mode changeover switch 44.

The first fixed contact terminal 44A of the mode changeover switch 44
is connected to a terminal to which a positive power supply 44B is applied, and the second fixed contact terminal 44B is grounded.

A flash light emission start signal x2 from a camera body (not shown) is supplied to one input terminal of the AND gate 45, and the output terminal of the inverter 45 is connected to the other input terminal. The output terminal of the AND gate 45 is
It is connected to the input terminal of a pulse generation circuit 46 similar to the pulse generation circuit 41, and the output terminal of the pulse generation circuit 46 is connected to the other input terminal of the OR gate 42. It is connected to a set input terminal of a tube circuit (hereinafter abbreviated as FF circuit) 47. Same F
The output end of the F'1g circuit 47 is an inverter 48 and a resistor 49.
are connected to the pace of the NPN type switching transistor 5o through the . A resistor 51 and ISO sensitivity are connected between the terminal to which the positive power supply 1B is applied and the ground terminal.

A series circuit is connected with a variable resistor 52 set based on the aperture, etc., and a series circuit is connected in sequence with the collector/emitter of a %NPN type phototransistor 53, a resistor 54, and an integrating capacitor 55. It is connected. A connection point between the resistor 51 and the variable resistor 52 is connected to a non-inverting input terminal of an operational amplifier 56 forming a voltage comparison circuit,
The inverting input terminal of the operational amplifier 56 is connected to a connection point between the resistor 54 and the capacitor 55. Further, the collector and emitter of the transistor 50 are connected to both ends of the capacitor 55, respectively.

The output end of the operational amplifier 56 is connected via an inverter 57 to the input end of a pulse generation circuit 58 similar to the pulse generation circuit 41, and the output end of the circuit 58 is connected to the reset input end of the FF circuit 47.

A light emission stop signal C2 is sent from the output end of the pulse generation circuit 58.

The output terminal of the pulse generating circuit 41 is connected to one input terminal of an OR gate 59, and the output terminal of the OR gate 59 is F
Connected to the set input terminal of the F circuit 60,
The output terminal of is connected to the input terminal of the inverter 61.

Further, the output terminal of the pulse generating circuit 41 is connected to the FF circuit 62.
The output terminal of the FF circuit 62 is connected to one input w4 of the AND gate 63.

The output terminal of the AND gate 63 is a preset counter 64.
The same preset counter 6 is connected to the 0 count input terminal.
The count output terminal of No. 4 is connected to the set input terminal of the FF circuit 65, and the output terminal of this FF circuit 65 is connected to the AND gate 66.
is connected to one input end of the Same and gate 66
The output terminals of are connected to respective reset input terminals of the FF circuits 62 and 65 and the preset counter 64.

Further, from the output terminal of this AND gate 66, the control circuit 2
Reset signal RH8E to reset all 00
K is set so that T is sent out.

In the brisect counter 64, the dynamic type 7-
) Data x based on the total viewing time U when the light is lit
3 is preset, and this time U,
is set to be longer than the time from when the leading curtain starts running and exposes the film to when the trailing curtain completes running and film exposure ends.

The other input terminal of the AND gate 66 is connected to the FF circuit 60.
is connected to the reset input terminal of the FF circuit 6.
70 set input terminal. The other input terminal of the AND gate 66 is connected to the output terminal of an oscillation circuit 68. A resistor 69 and a capacitor 70 for setting the oscillation frequency are connected between the oscillation circuit 68 and the application terminal of the power supply element B. The output terminal of the oscillation circuit 68 is connected to one input terminal of an AND gate 71, and the other input terminal of the AND gate 71 is connected to the output terminal of the FF circuit 67. The output terminal of the AND gate 71 is the preset counter 72
is connected to the count input terminal of The output terminal of the preset counter 72 is connected to the input flfl of a pulse generating circuit 73 similar to the pulse generating circuit 41, and the output terminal of this pulse generating circuit 73 is connected to the input terminal of a delay circuit 740. The output terminal of the delay circuit 74 is set at 5' so that a quick charge signal is sent out.

In this delay circuit 74, a delay time τ is set.

The preset counter 72 is preset with data x4 based on the light emission interval time U2 from when the pulsed light emission stops to when the next pulsed light emission restarts during dynamic flat light emission. This time U2 is set to "'C" based on the shutter speed, etc. The output terminal of the pulse generating circuit 76 is connected to the FF circuit 67 and the reset input terminal of the preset counter 72, and the other of the OR gates 59 The pulse generating circuit 73 is configured to send out a light emission restart signal B2.

On the other hand, the resistor 75 to which the monitor voltage signal M is supplied from the main circuit 100 is connected to an operational amplifier 76 forming an inverting amplifier circuit.
A resistor 77 is connected between the inverting input terminal and its output terminal, and its non-inverting input terminal is grounded. The output terminal of the operational amplifier 76 is the integrating resistor 7.
8 to an inverting input terminal of an operating circuit forming an integrating circuit, and an integrating capacitor 80 is connected between the inverting input terminal and its own output terminal. The non-inverting input terminal of the operational amplifier 79 is grounded. The output terminal of the operational amplifier 79 is connected to the inverting input terminal of an operational amplifier 81 forming a voltage comparison circuit. A resistor 82 and a variable resistor 86 are connected between the terminal to which IE source +B is applied and the ground terminal.
A voltage dividing circuit in which the resistor 82 and the variable resistor 83 are connected in sequence is connected, and the connection point between the resistor 82 and the variable resistor 83 is connected to the non-inverting input terminal of the operational amplifier 81. The variable resistor 83 is a resistor that is set depending on the shutter speed and the like. The above operational amplifier 81
The output terminal of is connected to the other input terminal of the AND gate 66 through the input terminal 84 and the pulse generating circuit 85 in sequence.The pulse generating circuit 85 outputs the light emission stop signal C. It's starting to get colder.

The collector of an NPN switching transistor 86 is connected to the output terminal of the operational amplifier 79, the emitter of the transistor 86 is grounded, and the base is connected to the output terminal of the inverter 61 via a resistor 87.

Next, the operation of the dynamic type flat light emitting strobe device of this embodiment configured as described above will be explained.

First, the operation of the "dynamic flat light emission mode" will be explained using Figures 6, 7, and 8.
Since the movable contact terminal No. 4 is switched to the first fixed contact terminal 44A, the positive power supply element B is supplied to the input terminal of the AND gate 40, and the AND gate 40 is opened.
The -CL level output is supplied to the input terminal of the AND gate 45 through the inverter 43, so that the AND gate 45 is in a closed state rlI4. Therefore, the input of the flat light emission start signal x1, which depends on the temperature of the camera body, is allowed, and the input of the flash light emission start signal x2 is no longer allowed. Then, when the flat light emission start signal Zl rises to H level, the output of the AND gate 40 becomes H level,
The pulse generating circuit 41 outputs an H level one-shot pulse. This H level pulse is generated by the OR gate 42.
The light emission trigger signal A is applied to the gate of the trigger thyristor 10 via the capacitor 13 and the resistor 12 to make the trigger thyristor 10 conductive. When the trigger thyristor 10 is made conductive, both ends of the trigger capacitor 8 are short-circuited via the primary coil of the trigger transformer 9, and the discharge current of the charge charged in the trigger capacitor t8 flows to the primary coil of the trigger transformer 9. A high voltage is generated in the secondary coil, and this high voltage is applied to the trigger electrode of the flash discharge tube 14, so that the flash discharge tube 14 is brought into an excited state.

Further, at the same time as the light emission, an H level pulse outputted from the pulse generation circuit 41 is transmitted through the OR gate 42 to generate the light emission start signal B.

As or gate 311 capacitor 30. The main thyristor 27 is made conductive via the resistor 29. When the main thyristor 27 is made conductive, the charge stored in the main capacitor 3 is discharged through the excited flash discharge tube 14 and the anode/cathode of the main thyristor 27, and the flash discharge tube 14 starts emitting flash light. . Further, at the same time, an H-level one-shot pulse outputted from the pulse generating circuit 41 sets the FF circuit 60 via the OR gate 59.

The output of the FF circuit 60 becomes H level. This H level output is inverted to L level by inverter 61, so transistor 86 is turned off.

Further, since the FF circuit 62 is set by the H level one-shot pulse output from the pulse generating circuit 41, the output of the FF circuit 62 is inverted to H level, and accordingly, the AND gate 66 is opened. , the output pulses of the oscillation circuit 68 are input to the preset counter 6i and counting is started.

On the other hand, the monitor voltage signal M obtained by dividing the voltage of the main capacitor B by the resistors 4 and 5 is inverted and amplified by the operational amplifier 76 forming an amplifier circuit, and this inverted and amplified voltage signal is sent to the resistor 78 and the capacitor. It is integrated by a time constant determined from 80. The output voltage of the operational amplifier 79 at this time is applied as a comparison voltage vlN to the inverting input terminal of the operational amplifier 81 forming the voltage comparison circuit, and the reference voltage vR is obtained by dividing the voltage of the positive power supply element B by the resistor 82 and the variable resistor 83Fc] cF. When the voltage of the main capacitor 3 is high, k is the characteristic a in FIG.
As shown in FIG. 7, when the time tJ until the comparison voltage V□ reaches the reference voltage vRIFK is short and the voltage of the main capacitor 3 is low, the comparison voltage v
It takes a long time t2 for XN to reach the reference voltage vREFK. The comparison voltage vIN reaches the reference voltage vR1,F,
When vXN≧vRICF, the output of the operational amplifier 81 becomes L level. When the L level output of the operational amplifier 81 is inverted to the H level by the inverter 84, an H level hit pulse is generated at the output of the pulse generating circuit 85. This H level pulse is applied to the OR gate 26. as the light emission stop signal C8. The commutating thyristor 22 is made conductive through the capacitor 25 and the resistor 24 in sequence. When the commutating thyristor 22 is made conductive, the anode and cathode of the main thyristor 27 are reverse biased by the charged commutating capacitor 16, so that the main thyristor 27 becomes non-conductive. Furthermore, when the light emission stop signal C rises to the H level, the FF circuit 67 is set, so the AND gate 71 is opened and the output pulse of the oscillation circuit 68 is input to the preset counter 721' (counting starts). Furthermore, when the light emission stop signal C1 rises to the H level, F
Since the F circuit 60 is reset, the output of the FF circuit 60 is inverted to L level, and accordingly, the Etranlisk 8
6 is turned on, the inverting input terminal of the operational amplifier 81 is forcibly brought to the ground level, and the monitor circuit 202 that detects the monitor output voltage signal M becomes substantially inoperative.

The time U of the above-mentioned light emission interval is determined by the preset counter 72.
When the count corresponding to 2 is completed, the output of the preset counter 72 becomes H level, and accordingly, a pulse signal of KH level is generated at the output terminal of the pulse generating circuit 73. This H level pulse is the light emission restart signal B.
2 as orgate 31. Capacitor 50. The voltage is applied to the gate of the main thyristor 27 through the resistor 29 in order, making the main thyristor 27 conductive. At this time, since the deionization time has not elapsed since the flash discharge tube 14 last stopped emitting light, the discharge tube 14 resumes emitting light only when the main thyristor 27 is turned on. At the same time k.

The FF circuit 67 and preset counter 72 are reset. In addition, since the light emission restart signal B2 of the H level pulse sets the FF circuit 60 via the OR gate 59, the output of the FF circuit 60 is inverted to the H level, and accordingly, the output of the inverter 61 is set to the L level. Then, transistor 86 turns off. Therefore, as before, the operational amplifier 79 restarts the integration operation of the monitor output voltage M.

Further, the light emission restart signal B2 of the H level pulse is supplied to the delay circuit 7.
41C, the capacitor 21. The voltage is applied to the gate of the thyristor 18 through the resistor 20 in order, making the thyristor 18 conductive. When the thyristor 18 becomes conductive, the commutating capacitor 16 is rapidly charged in a very short time through the main path of line 4 -> anode/cathode of thyristor 18 -> commutating capacitor 16 -> anode/cathode of main thyristor 27 - line p0. When the charging of the capacitor 16 is completed, the energization to the thyristor 18 becomes less than the holding current, and the thyristor 18 becomes non-conducting. and,
When the output voltage of the operational amplifier 79, that is, the comparison voltage vIN exceeds the reference voltage vREF, the output of the operational amplifier 81 is inverted to L level. When the output of the operational amplifier 81 reaches the L level Ktx, the output power of the inverter 84 becomes the 1 (level), and the pulse generation circuit 85 sends out the light emission stop signal CI of the H level pulse in the same manner as before.

Similarly, the light emission restart signal B2. Since the quick charge signal becomes an H level pulse, the light emission waveform at the number of flashes 1 & 914 becomes a continuous pulse.

Then, the total viewing time U is determined by the preset counter 64.
When the count number corresponding to , is completed, the pF circuit 65 is set and the output of the FF circuit 65 is inverted to H level, so that when the light emission stop signal C1 of the H level pulse is generated thereafter, this The light emission stop signal CI at this time is obtained as a reset signal RESET through the AND gate 66. When the reset signal) tFisET occurs,
The same reset signal RE! SET is the FF circuit 62. Preset counter 64. The FF circuit 65 is reset, and all other circuits are also reset to complete the series of dynamic flat light emission operations.

In addition, in the above-mentioned "flat light emission mode", the movable contact terminal of the mode changeover switch 44 is connected to the first fixed terminal 4.
Since 4A is switching to crocodile, and gate 4
One input terminal of the AND gate 45 is at the L level, and even if the AND gate 45 is closed and the flash light emission start signal 3c2 is input, the pulse generation circuit 4
Circuits after 6 are not affected in any way. Along with this, since the output of the inverter 48 is at H level, the transistor 50 is always turned on, and there is no possibility that the light emission stop signal C2 to stop light emission is output from the photometry circuit section 203.

Next, the operation of the "flash light emission mode" is shown in Figures 9 and 10.
This will be explained using figures. When the movable contact terminal of the mode changeover switch 44 is switched to the second fixed terminal 44B and the "flash emission mode" is selected, the strobe device of this embodiment goes to the L level, the AND gate 40 is closed, and the flat light emission start signal x1 is no longer accepted, and the other input terminal of the AND gate 45 goes to the H level, so the AND gate 45 opens and the flash light emission starts. K is set to accept signal x2.

That is, when the camera is recognized and the flash light emission start signal x2 is input, the output of the AND gate 45 becomes H level, an H level pulse is generated in the pulse generating circuit 46, and this H level pulse is passed through the OR gate 42. Light emission trigger signal A
As a result, the trigger thyristor 10 is made conductive via the capacitor 13 and the resistor 12.

Also, as the light emission start signal B1, the OR gate 61. Capacitor 30. The main thyristor 27 is made conductive via the resistor 29. Therefore, the charge accumulated in the main capacitor 3 is discharged through the flash discharge tube 14 and the main thyristor 27, and the flash spreader 14 starts emitting flash light. Further, the FF circuit 47 is set by the H level output of the pulse generation circuit 46, the output of the FF circuit 47 is inverted to the H level, and the transistor 50 whose pace is set to the L level through the inverter 48 and the resistor 49 is turned off. Become.

Therefore, the photocurrent generated in the phototransistor 53 is integrated by the capacitor 55, and the photometry circuit section 203 starts photometry.

In the photometric circuit section 203, the capacitor 5
When the integrated voltage of 5 exceeds the reference voltage which is the connection point voltage of resistor 51.52, the output of operational amplifier 56 is inverted to L level, the output of inverter 57 becomes H level, and the output terminal of pulse generating circuit 58 is inverted to L level. The H level pulse from the OR gate 26 and the capacitor 25 . The thyristor 22 is made conductive via the resistor 24.

As a result, the main thyristor 27 is rendered non-conductive, similar to the operation in the above-mentioned "flat light emission mode" K.
Light emission stops. Therefore, the robot device of this embodiment is as follows:
The movable contact terminal of the mode changeover switch 44 is the fixed terminal 44.
When switched to B, it functions as a normal auto flash device.

Next, a second embodiment of the present invention will be described using FIGS. 11 to 15. Similarly to the first embodiment, this embodiment also has the following:
It is configured to have two functions: a "dynamic flat light emission mode" and a "flash light emission mode". First, the configuration of the main circuit 300 will be explained. This main circuit 300 is the same as the main circuit 100 (see FIG. 4) in the first embodiment except for some elements, so similar elements have the same reference numerals as shown in FIG. 4. The detailed explanation will be omitted.

Electrodes and lines of flashlight fiW14! . A normally-on electrostatic conduction type (SI type) thyristor 32 is connected between the
The anode and cathode of the thyristor 32 are connected to each other, and the gate of the thyristor 32 is connected to the connection point between the commutating capacitor 16 and the resistor 17. Further, the cathode of thyristor 330 is connected to the gate of thyristor 32, and the anode of thyristor 33 is connected to the line! . A resistor 34 is connected between the gate and its own cathode. The gate of the thyristor 33 is supplied with a light emission restart signal E via a resistor 35, a capacitor, and 36 in sequence.

A control circuit 400 having a circuit configuration as shown in FIG. 12 is connected to the main circuit 300 thus configured. This control circuit 400 includes a light emission interval setting circuit section 401, a monitor circuit section 402, and a photometry circuit section 403, and only some of the elements of the control circuit 200 in the first embodiment are changed. Since they are the same, similar elements are given the same reference numerals as those shown in FIG. 5, and their details will be omitted.

Pulse generation circuit 7 forming light emission interval setting circuit section 401
The light emitting stop signal E is sent out from the output end of No. 3.

Further, a resistor 88 to which the monitor voltage signal M is supplied from the main circuit 300 to the monitor circuit section 402 is connected to a non-inverting input terminal of an operational amplifier 89 forming a non-inverting amplifier circuit, and an inverting input terminal of the operational amplifier 89 is connected to a resistor 88. 90, and a resistor 91 is connected between this inverting input terminal and its own output terminal.
is connected. An integrating circuit including a resistor 92 and a capacitor 93 connected in series is connected to the output end of the operational amplifier 89. The emitter base collector of an NPN switching transistor 94 is connected to both ends of the capacitor 93, and the emitter is grounded. The terminal of the transistor 94 is connected to the output terminal of the inverter 61 via a resistor 95. A connection point between the resistor 92 and the capacitor 95 is connected to the inverting input terminal of the operational amplifier 81.

Next, the operation of the dynamic flat light emitting strobe device of the second embodiment configured as described above will be explained.

First, the operation of the "dynamic flat light emission mode" will be explained using FIG. Since the positive voltage signal B is supplied to the input terminal of the AND gate 40, the AND gate 40 is opened and the inverter 4 is switched to
Since the output of the -CL level is supplied to the input iK of the AND gate 45 through the input terminal IK, the AND gate 45 is in a closed state. Therefore, the input of the flat light emission start signal rl, which is unknown to the camera body, is allowed, and the input of the flash light emission start signal x2 is no longer allowed. When the flat light emission start signal x1 is input, the trigger thyristor 1o is made conductive by the light emission trigger signal A from the output terminal of the OR gate 42, as in the case of the previous embodiment, and the flash discharge tube 14 is brought into an excited state. Then, the charges stored in the main capacitor 3 are discharged through the excited flash discharge tube 14 and the anode/cathode of the main thyristor 32, and the flash discharge tube 14 starts emitting flash light.

Furthermore, at the same time, the H level one-shot pulse output from the pulse generating circuit 41 sets the FF circuit 60 via the OR gate 59, and the output of the FF circuit 60 becomes H level, so this H level The output of is inverted to L level by the inverter 61, which turns off the transistor 94 and starts the integrating operation of the monitor circuit 402.

Furthermore, since the FF circuit 62 is cassetted by the H level one-shot pulse output from the pulse generating circuit 41, the output of the FF circuit 62 is inverted to H level, and the AND gate 63 is accordingly opened. The output pulses of the oscillation circuit 68 are input to the preset counter 64 and counting is started.

On the other hand, the monitor voltage fi M obtained by dividing the voltage of the main capacitor 3 by the resistor 4 and the resistor 5 is amplified by the operational amplifier 89 forming a non-inverting amplifier circuit, and this amplified voltage signal is transmitted to the resistor 92 and the capacitor 93. It is integrated by a time constant. The integrated voltage at this time is the operational amplifier 8
The comparison voltage vXN is applied to the inverting input terminal of 1, and the positive t
A comparison is made with a reference voltage vREF obtained by dividing the voltage of B[+B by a resistor 82 and a variable resistor 83. Then, the output of the operational amplifier 81 is at L level, that is, vIN≧vRE
When the FK occurs, this L level output is inverted to H level by the inverter 84, and a one-shot pulse of 1 level is generated at the output of the pulse generation circuit 85. This H level pulse is sent to the OR gate as the light emission stop signal CI. 26
゜Capacitor 25. The commutating thyristor 22 is made conductive via the resistor 24 in sequence. When the commutation thyristor 22 becomes conductive, the charged load of the commutation capacitor 16 is discharged through the path of the commutation capacitor 16 → the anode/cathode of the commutation thyristor 22 → the resistor 17. Then, at this time, the main thyristor 32 Since the gate and cathode of the main thyristor 32 are reverse biased, the main thyristor 32 instantly becomes non-conductive.
Light emission stops. It should be noted that since the flash discharge tube 14 has a deionization time, it is necessary to keep the flash discharge tube 14 in a reverse bias state during this deionization time. Therefore, it is necessary to set the time constant determined by the commutating capacitor 16 and the resistor 17 to be longer than the above deionization time. Further, when the light emission stop signal CI rises to the H level, the FF circuit 67 is set, so the AND gate 71 is opened, and the output pulse of the oscillation N path 68 is input to the preset counter 72 to start counting. Furthermore, since the FF circuit 60 is reset when the light emission stop signal C1 rises to H level, the FF circuit 60 is reset.
The output of the F circuit 60 is inverted to L level, and accordingly, the transistor 94 is turned on, and the capacitor 93 is turned on.
The charged charges are discharged, and the monitor circuit 402 that detects the monitor output voltage signal M becomes substantially inoperative.

The time U of the above-mentioned light emission interval is determined by the preset counter 72.
When the count corresponding to 2 is completed, the output of the preset counter 72 becomes H level, and accordingly, the output terminal of the pulse generating circuit 73 generates a pulse at the KH level. This H level pulse is applied as the light emission restart signal E to the gate of the thyristor 33 via the capacitor 36 and the resistor 35 in sequence.

Therefore, the thyristor 33 becomes conductive and both ends of the resistor 17 are short-circuited, so that the charge stored in the commutating capacitor 111 is transferred from the anode/cathode of the commutating thyristor 22 to the resistor 1.
Since the discharge path changes from the discharge path of No. 7 to the anode/cathode of the commutating thyristor 22 and then the anode/cathode of the thyristor 33, the gate potential of the main thyristor 32 becomes approximately the ground potential, and the main thyristor 32 Conduct. When the main thyristor 32 becomes conductive after 5K, the flash discharge tube 14, which has not elapsed the deionization time since the previous stop of light emission, resumes light emission. At the same time, the FF circuit 67 and preset counter 72 are reset. Further, since the light emission restart signal E of the H level pulse sets the FF circuit 60 via the OR gate 59, the output of the FF circuit 60 is inverted to the H level, and accordingly, the output of the inverter 61 goes to the L level. become,
Transistor 94 is turned off.

Therefore, the integration operation of the monitor output voltage M in this monitor circuit 402 is restarted.

The light emission restart signal E is delayed by a time τ by a delay circuit 74, and is used as a high-level pulse rapid charging signal for the capacitor 21. The voltage is applied to the gate of the thyristor 18 through the resistor 20 in order, making the thyristor 18 conductive. When thyristor 18 conducts, the line! Yi → Thyristor 1 day anode/cathode → Commutation capacitor 16 →
Main thyristor 32 gate/cathode → line! 0
The commutating capacitor 16 is rapidly charged in an extremely short time through the main path. When the charging of the capacitor 16 is completed, the energization to the thyristor 18 becomes less than the holding current, and the thyristor 18 becomes non-conductive. Then, when the integrated voltage by the resistor 92 and the capacitor 93, that is, the comparison voltage vI exceeds the reference voltage vRBF, the output of the operational amplifier 81 goes low.
Flip to level. When the output of the operational amplifier 81 becomes L level, the output of the inverter 84 becomes H level, and the pulse generation circuit 85 sends out the light emission stop signal C3 of the H level pulse as before.

In the same manner, the light emission restart signal E and the quick charge signal are set to H.
Since the level pulse is generated, the light emission in the flash discharge tube 14 becomes a continuous pulse.

Then, the total viewing time U is determined by the preset counter 64.
When the count corresponding to , is completed, the FF circuit 65 is set, the output of the FF circuit 656 is inverted to H level, and after that, the light emission stop signal C of the H level pulse is output.
7 is obtained, the signal C3 is sent through the AND gate 66 as a reset signal RESET to the F'F circuit 62. Preset counter 64. The FF circuit 65 is reset, all other circuits are reset, and a series of dynamic flat light emission operations are completed.

Next, the movable contact terminal of the mode changeover switch 44 is switched to the second fixed terminal 44B to select the "flash light emission mode".
When is selected, the operation is similar to that of the "flash light emission mode" in the first embodiment, so the explanation thereof will be omitted. However, in this second embodiment, since a normally-on thyristor 32 is used, the 15th thyristor 32 is used.
As is clear from comparing the flowchart in the figure with the chart 70 in FIG.
As in the case of , the light emission start signal B is not required.

In the dynamic flat light emitting device of the first and second embodiments, the light emitting interval setting circuit section 20
1, a light emission interval setting circuit section 201' as shown in FIG. 16 may be used. In this light emission interval setting circuit 201', the output terminal of the FF circuit 67, which is supplied with the light emission stop signal C1 from the monitor circuit 202 or 402, is connected to one input terminal of the FF circuit 102 via the inverter 101. The output terminal of the OR gate 102 is connected to the base of an NPN switching transistor 1040 via a resistor 103. A series circuit including resistors 105 and 106 and the emitter collector of the transistor 104, an integrating capacitor 107, and a constant current circuit 108 are connected between the terminal of the positive atom B and the ground terminal. connected to the series circuit. The terminal of the positive atom B is connected to the emitter of a PNP transistor 109, and the base of the transistor 109 is connected to the resistor 1.
05 and the connection point between resistor 106. The collector of the transistor j09 is connected to the connection point between the capacitor 107 and the constant current circuit 108.

Furthermore, the output terminal of the inverter 101 is connected to an OR gate 11.
The output terminal of the OR gate 110 is connected to the base of an NPN switching transistor 112 via a resistor 111. The connection between the terminal of the positive atom B and the ground terminal is a series circuit that sequentially passes through m resistors 113 and 114 and the collector/emitter of the transistor 112, an integrating capacitor 115, and a constant current circuit 116. The series circuit is connected through the ℃.

The terminal of the positive atom B is connected to the emitter of a PNP transistor 117, and the base of the transistor 117 is connected to the connection point between the resistor 113 and the resistor 114. The collector of the transistor 117 is connected to the connection point between the capacitor 115 and the constant current circuit 116.

The connection point between the capacitor 107 and the constant current circuit 108 is connected to the inverting input @ of the operational amplifier 118 forming a voltage comparison circuit, and the connection point between the capacitor 115 and the constant current circuit 116 forms a voltage comparison circuit. The inverting input terminal of the operational amplifier 119 is connected to the inverting input terminal of the operational amplifier 119. The monitor voltage signal M is supplied to the non-inverting input terminals of both operational amplifiers 118 and 119 via resistors 120 and 121, respectively.

Furthermore, the respective output terminals of the operational amplifiers 118 and 119 are connected to the two input terminals of the OR gate 122, and the output terminal of the OR gate 122 is connected to the set input terminal of the FF circuit 123. One end is connected to the input end of the inverter 124 and the other input end of the OR gate 102 .

The output terminal of the inverter 124 is connected to the other input terminal of the OR gate 110. Further, the output terminal of the FF circuit 123 is connected to the count input @ of the preset counter 125.

The preset counter 125 is preset to a predetermined count number by data Jcs. The count output terminal of the preset counter 125 is connected to the pulse generation circuit 75.
The light emission restart signal B2 is connected to the input terminal of the pulse generating circuit 73, and the light emission restart signal B2 is sent from the output terminal of the same pulse generating circuit 73.

The operation of the light emitting interval setting circuit section 201' configured as described above will be explained with reference to FIGS. 17 and 18.

When the output of the FF circuit 67 based on the light emission stop signal CI is at the L level, the output of the inverter 101 and the outputs of the OR gates 102 and 110 are at the H level, so the transistors 104 and 112 are both turned on.
Along with this, both transistors 105 and 117 are turned on. Therefore, both ends of capacitor 107 and both ends of capacitor 115 are short-circuited. Therefore, the potential at the inverting input terminal of each of the operational amplifiers 118 and 119 becomes approximately the same as the potential of the positive power supply element B. Therefore, operational amplifier 118
.

When the light emission stop signal C3 is input to the FF circuit 67, the same F
The F circuit 67 is set, and accordingly the inverter 10
1 output becomes L level, OR gate 102.11
Each output of 0 becomes dependent on the output state of the FF circuit 123. That is, when the output of the FF circuit 123 is at the L level, the output of the OR gate 102 is at the L level, so the transistor 104 is turned off. On the other hand, the output of the OR gate 110 is also at the H level, so the transistor 112 is turned on. Become. Accordingly, transistor 109 is turned off and transistor 117 is turned on.

Therefore, from this point on, the constant current flowing through the constant current circuit 108 starts charging the °C capacitor 107.Then, the potential V at the connection point between the capacitor 107 and the constant current circuit 108 becomes As shown in FIG. 17, the potential vI gradually decreases with the charging operation, and when this potential vI becomes lower than the potential −1 of the monitor voltage signal M, that is, the potential vM of the non-inverting input terminal of the operational amplifier 118, The output of the operational amplifier 118 is inverted to H level, and this H level signal is guided to the FF circuit 123 via the OR gate 122 and sets the FF circuit 123, so that the output VFF of the FF circuit 123 becomes H level. This FF circuit 125
The output of vFF is busy due to the high level signal) 1
The transistor 104 is turned on via the resistor 103 and the transistor 104, and accordingly the transistor 109 is turned on, and the charge stored in the capacitor 107 Vc is discharged. At the same time, the output of the inverter 124 becomes L level, so the output of the OR gate 110 becomes L level.

Both transistors 112 and 117 are turned on, and from this point on, charging of the capacitor 115 is started by the constant current (2) flowing through the constant current circuit 116. Then, the potential V at the connection point between the capacitor 115 and the constant current circuit 116 gradually decreases in the same way as the above-mentioned potential η, and this potential v2 becomes the potential vM of the monitor voltage signal M, that is, the non-inverting input of the operational amplifier 119. When the potential at the end drops below vM, the same operational amplifier 11
The output of 9 is inverted to H level. When this H level signal is led to the FF circuit 123 via the OR gate 122 and resets the F'F circuit 123, this FF circuit 12
The output vFF of No. 6 is inverted to L level. This FF circuit 1
The L level signal of the output vFF of 23 is oh goo) 102
1C, the transistor 104 is turned off, and it is inverted by the inverter 124 and the OR gate 1 is turned off.
10 turns on the transistor 112, so the potential V rises again to the potential of the positive power supply element B, and the potential V2 begins to fall toward the bottom.

Thereafter, the above-described operation is repeated in the same manner, and a pulse train signal is obtained as the output vFP of the FF circuit 123.

Then, the period TFF of the output vFF of the FF circuit 123 is
When the potential vM of the monitor m pressure signal M is lower than the state shown in FIG. 17 (5), that is, when the charging voltage of the main capacitor is low, the ratio is The period becomes long TFP'. Conversely, the potential vM
is higher than the state shown in FIG. 17(4), the period becomes shorter than the period TFF.

When the output vFF of the FF circuit 123 is input to the reset counter 125, the preset counter 125 counts the number of pulses of the preset data
5 sends an H level pulse to the pulse generating circuit 73, and as a result, a light emission restart signal B2 of an H level pulse is sent from the output end of the pulse generating circuit 76. When the light emission restart signal B2 is sent out, the above-mentioned monitor circuit section 20
2 or 402, the light emission stop signal C3 is supplied, and the output of the FF circuit 67 is inverted to L level, returning to the above-mentioned initial state. In this way, the light emission time of each pulse light emission is determined by the state of the reset counter 125 which depends on the pulse period of the output 'FF' of the %FF circuit 123. Therefore, when the voltage of the main capacitor 3 is low, the light emission time of each pulse light emission is The light emission time becomes longer, and when the voltage of the main capacitor 3 is high, the light emission time becomes shorter. Therefore, the charge of the main capacitor 41 corresponding to the amount of light emitted by each pulse can be kept constant regardless of the voltage.

Further, a light emission interval setting circuit section 6 having a configuration as shown in FIG.
00 may also be used. This light emission interval setting circuit section 600 has a capacitor 1 of a constant current charging circuit that is the same as the constant current charging circuit in the light emission interval setting circuit section 201' shown in FIG.
07 and the connection point between constant current circuit 108.

Connect the inverting input terminal of the operational amplifier 128 forming the voltage comparison circuit, and apply the monitor voltage signal M to the non-inverting input terminal of the operational amplifier 128 via the resistor 127.
, Furthermore, the output terminal of the same operational amplifier 128 is connected to the inverter 12.
9 to the input terminal of the pulse generation circuit 730, and further to the output terminal of the FF circuit 67.

Configuration 1 is connected to the resistor 103 via the inverter 126.
Similarly to the case explained in Fig. 8, when the potential of the monitor voltage signal M is high, that is, when the voltage of the main capacitor 3 is high, the integration times T and o become short as shown in Fig. 19 (A). Conversely, when the potential of the monitor voltage signal M is low, the integration time T2° becomes longer as shown in FIG. 19 (CB). As a result, as the pressure on the main capacitor 3 becomes lower, the time of inversion of the output level of the operational amplifier 128 is delayed, so that the light emission time of each pulse light emission becomes longer.

In this way, the voltage of the main capacitor decreases over time when each pulse emission is performed continuously, so if the emission time of the short pulse emission is kept constant, each pulse emission will increase This means that the amount of light emitted from the scale will decrease. By changing the light emission time according to the voltage of the main capacitor 3, the light emission amount of each pulse light emission can be made constant regardless of the voltage of the main capacitor 3.

Also, based on the above idea, the light emission time is fixed and the light emission interval is varied by a circuit similar to the above embodiment. By using a circuit in which the circuit 108 is connected in reverse between the power supply element B and the ground, the emission interval becomes shorter as the voltage of the main capacitor decreases.
The number of light-emitting hands per unit time can be kept constant.

Note that the constant current (b) paths 108 and 11 in the above embodiment
Of course, a resistor may be used instead of 6.

(Effects of the Invention) As described above, according to the present invention, changes in the light intensity of the flash discharge tube are detected by replacing them with changes in the voltage of the main capacitor, which has the advantage of not being adversely affected by high-voltage light emission trigger signals. .

In addition, unlike conventional static flat flash units, the flash discharge tube is not controlled on and off between the extremely small upper and lower limits, which simplifies the circuit configuration and provides extremely high accuracy. It also has the advantage of being cheaper because it does not require the use of a voltage comparison circuit.

Therefore, it is possible to provide a dynamic type flat light emitting flash device which overcomes the conventional drawbacks mentioned at the beginning of the specification and is extremely convenient to use.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the light emission intensity characteristics of a conventional strobe device and the dynamic type flat light emitting strobe device of the present invention, and FIG. 2 is a diagram showing the light emission intensity characteristics of a dynamic type flat light emitting strobe device of the present invention. spacing and 7
Diagram showing the relationship with the slit width of Ocal Plane Shutter,! FIG. 3 is a diagram showing exposure unevenness in the focal plane shutter when using the dynamic flat light emitting device according to the first embodiment of the present invention. FIG. 5 is an electrical circuit diagram showing the main circuit of the strobe device; FIG. 5 is an electrical circuit diagram showing a control circuit connected to the main circuit shown in FIG. 4; FIG. 6 is the electrical circuit diagram shown in FIGS. The first aspect of the present invention shown in FIG.
Each signal waveform diagram for explaining the operation of the "flat light emitting mode" in the dynamic type flat light emitting strobe device of the embodiment, FIG. 7 is a line diagram for explaining the operation of the monitor circuit shown in FIG. 5 above. figure. FIG. 8 is a 7o chart showing the operation of the "flat light emission mode" in the strobe device of the first embodiment, and FIG. Each signal waveform diagram, FIG. 10, for explanation is shown in FIG.
FIG. 11 is an electric circuit diagram showing the main circuit of the dynamic flat flash flash device according to the second embodiment of the present invention. FIG. 12 is a diagram showing the operation of the flash mode. FIG. 13 is an electrical circuit diagram showing a control circuit connected to the main circuit shown in FIG. FIG. 14 is a signal waveform diagram for explaining the operation of "mode" in the strobe device of the second embodiment.
15 is a flowchart showing the operation of the "flash light emission mode" in the strobe device of the second embodiment; FIG. 16 is the figure 5 or 12 shown above. 17(A) and 17(B) are electrical circuit diagrams showing other examples of the light emission interval setting circuit section in the control circuit shown in FIG. 16. Each signal waveform diagram, FIG. 18 is an electric circuit diagram showing still another example of the light emission interval setting circuit section in the control circuit shown in FIG. 5 or FIG. 12, and FIGS. 19 (A) and CB) are 19 is a signal waveform diagram for explaining the operation of the light emission interval setting circuit shown in FIG. 18. FIG. 3゛...Main capacitor 14...Flash discharge tube 16...Commuting capacitor 18...Thyristor (switching element for rapid charging) 22...Commuting thyristor (commutating element) 27.32...- Main thyristor (main switching element) -100,500"... Main circuit 200.400... Control circuit 201.201', 401...・Emission interval setting circuit section 202, 402-・e11@monitor circuit section horse 1
Figure d = 0.2 Easy 6 Figures Horse 7 Sections 9 Figures 8 Areas 314 Figures Horses 16 Figures / 201' Directions 17 Areas Ru Old Maps 19 Sections Procedures Amendment Book (Voluntary) 1. Indication of the case: 1982 Patent Application No. 82335 2,
Title of the invention Dynamic flat light emitting strobe device 6, relationship to the amended person's case Address of patent applicant 2-43-2 Hatagaya, Shibuya-ku, Tokyo Name Title
(037) Olympus Optical Industry Co., Ltd. 4゜ Representative Osamu
Address 5-52-14 Matsubara, Setagaya-ku, Tokyo Name (7 (555) Fujikawa Nanabu (524-27)
00) 5. “Claims” and “Detailed Description of the Invention” of the specification subject to amendment
Each column of "Brief explanation of drawings", drawing 6, and the scope of amendment (1) "Claims" of the specification will be revised according to the 'AI group. (2) Delete the text after "was" written on page 7, line 10 of the specification and before "let" written on page 7, line 17 of the specification, and substitute the first sentence. Masu. [The semiconductor switching element is turned off when the voltage of the main capacitor reaches a predetermined value, and the semiconductor switching element is turned on during the deionization time l in the flash discharge tube after the flash discharge tube stops emitting light. (3) After "each" in the sixth line from the bottom of page 11 of the same, , “a, 1. I am joining J. (4) “■,■” written in the fifth line from the bottom of page 11
” will be changed to “■′,■′”. (5) "This" written in the fourth line from the bottom of page 11 will be changed to "Calculate the formulas ■ and ■ above based on this." (6) "This" written in the third line from the bottom of page 11 of the same
"In addition, each of P = 1024°512, 256.128.ψ... shown in Tables 1 to 5 above is the nominal exposure time T') seconds'/'1ooo・'1500・'/2
50・1/125・°°. are the values corresponding to each of them. In addition, the above Tables 1 to 3 will be revised. (7) Add "nominal exposure time T" after "was" at the end of line 6 on page 12. (8) "Minimum pulse width" stated in page 12, line 9 of the same
is changed to "maximum flash interval". (9) "ORGATE" written in the second line of page 20 will be changed to % "ANDGATE". (10) Add the following sentence after "I'm here." at the end of line 8 on page 37. "Unlike the circuit shown in FIG. 5 above, the output terminal of this pulse generation circuit 73 is not connected to each of the reset counter 72 and the F'F circuit 67.
It is connected only to the OR gate 590 input terminal. Also,
The output terminal of the pulse generation circuit 41 is connected to the FF circuit 62 as described above.
0 input terminal, and also connected to the input terminal of the PF circuit 67, unlike the circuit shown in FIG. Further, the preset counter 72 is configured to output an H-level one-shot pulse when counting up to the count number corresponding to data x4 is completed, and at the same time start counting again. (11) Add the following sentence at the end of page 59, line 19, after "will be." [Furthermore, since the FF 00 M 67 cassette is generated by the H level one-shot pulse output from the pulse generation circuit 41, the output of the circuit 67 is inverted to the H level, and accordingly, the AND gate 71 is opened. , oscillation times j! 2) A 6B output pulse is input to the preset counter 72 and counting is started. (12) Same No. 4
Delete the text from "There is" written on page 1, line 6 to before "Also" written on page 41, line 10. (13) IMJ Page 41, line 17 Substitute the time [J2/J] for the next light emission interval of "above" described inside. (14) The text after "Resuming." written on page 42, line 15 of the same page and before "Also." written on page 42, line 17 of the same page is deleted. Delete the text after "above" written in the beginning of line 6 on page 45 to before "output end of" written in line 12 on page 45, and substitute the following sentence. In the dynamic type flat light emitting strobe device according to the second embodiment, a light emitting time setting circuit section 404 as shown in FIG. That is, in this light emission time setting circuit section 404, the output terminal of the OR gate 59 is connected to the set input terminal, and the output terminal of the pulse generation circuit 130 is connected to the reset input terminal, that is, the terminal to which the light emission stop signal C1 is sent. FF@FF path 6 is connected and substitute the following statement: The pulse generation circuit 130 is connected to the pulse generation circuit 130, and a light emission stop signal C1 is sent from the output terminal of the pulse generation circuit 130. 1711 (A) and (B). FF circuit 60" (17) VC description in page 48, line 11 (Dr105
J. Changed to r109J. (18) Delete the text after "1 flash" written on page 48, line 17 of the same page and before "set" written on the last line of page 48, and substitute the following sentence. The time setting circuit section 404 is configured so that there is no substantial VCa. When the H level pulse of the OR gate 59 is input to the set input terminal of the FF circuit 6o, the FF circuit 60J (19) Next to "will be done" written in line 5 on page 50, "at the same time, the output of the operational amplifier 118 goes low again."
Flip to level. Also, add j. (20) Change “vl” written in the 4th line of No. 51 Sada to “
v2”. (21) "v2" written in line 5 on page 51 of the same is replaced with "
vl". (22) "73j stated in the last line of page 51," (
``150J.'' (23) Delete the text from the word "circuit" written at the beginning of the second line on page 52 to before "in this way," written on the seventh line of page 52, Substitute the following statement: A light emission stop signal CI of an H level pulse is sent from the output terminal of [130]. Then, the FF circuit 6o is reset by this light emission stop signal C8, and the output of the circuit 60 is inverted to L level, returning to the above-mentioned initial state. Then, the light emission time setting circuit 404 does not work until the next output pulse from the OR gate 59 occurs. ” (24) “Also” stated at the beginning of line 16 on page 52 of the same
r201'J described at the end of page 52, line 18 after .
Delete up to and substitute the following statement. Instead of the light emitting time setting circuit section 404 having the configuration shown in FIG. 16 above, a light emitting time setting port 199405 having the structure shown in FIG. 18 may be used. Light emission time setting circuit section 404 J shown in FIG.
It will be changed to 150J. (26) "67" written in the 6th line of page 53 of the same is replaced with "
60". (27) "18" written at the beginning of line 10 on page 53 will be changed to "17". (28) "19" written in page 54, line 10 of the same. Change it to "18". (29) Add the following sentence on a new line next to "Deru." written at the end of line 17 on page 54. "Next, a third embodiment of the present invention will be explained using FIG. , same as the first and second embodiments above, r dynamic type 72-bit light emission mode j and "flash light emission mode J
It is configured with two functions: First, the configuration of the main circuit 500 shown in FIG. 2Q will be explained. This main circuit 500 is the main circuit 300 (11th
Since only some of the elements (see figure) are changed and the rest are the same, similar elements are given the same reference numerals as those shown in FIG. 11, and detailed explanation thereof will be omitted. The gate of the SI type thyristor 32 similar to that shown in FIG. 11 is connected to the connection point between the resistors 502 and 505 connected in series. The output terminal of the OR gate 522 is a resistor 50 connected in series.
5 and 508 to ground, and the resistor 505
The connection point between and 508 is connected to the base of an NPN transistor 507, and the emitter of the transistor 507 is connected to ground. The collector of this transistor 507 is connected to the positive terminal of the first DC power supply 519 via series-connected resistors 506 and 504. Connected to 2. The connection point between the resistors 506 and 504 is connected to the base of a PNP transistor 501, and the emitter of the transistor 501 is connected to the line ! ,It is connected to the. Furthermore, the collector of the transistor 501 is connected to the resistor 50.
Connected to 2. The output of the OR gate 523 is connected to the line 13oFc through series-connected resistors 517 and 518.
This 2-in Ilo is connected to the negative pole of the DC power supply 519 and further connected to the positive pole of the second DC power supply 521. The connection point between the resistors 517 and 518 is connected to the base of an NPN transistor 5160, the emitter of the transistor 516 is connected to the line JoK, and the collector is connected to the line JoK through series-connected resistors 515 and 514. Connected to 2. In addition, the resistor 51
The connection point between 4 and 515 is connected to the base of a PNP transistor 513, and the emitter of the transistor 513 is connected to the line! , and the collector is connected to resistor 5.
11 to the base of an NPN transistor 509. The emitter of the transistor 509 is connected to the line 43 connected to the negative terminal of the DC power supply 521, and the base of the transistor 509 is connected to the line 43 through a resistor 512. Connected to 3. Further, the collector of the transistor 509 is connected to the gate of the main thyristor 32 via the resistor 503. By skillfully arranging the two DC power supplies 519 and 521 as described in 5 above, the gate of the main thyristor 32 is supplied with either a higher potential or a lower potential than the ground potential which is the reference potential, The main circuit 500 Vc configured as described above is connected to the control circuit 600 having an M circuit configuration as shown in FIG. 21, which controls the on/off state of the thyristor 32. This control circuit 600 has the same configuration as the control circuit 400 in the second embodiment (see FIG. 12) except for adding some of the configuration and some of the elements. are given the same reference numerals as those shown in FIG. 12, and detailed explanation thereof will be omitted. Pulse generation circuit 7 forming light emission interval setting circuit section 601
The output terminal of the pulse generation circuit 73 is connected to the first input fail of the three-man power OR boot 610. The second input iK of this OR gate 610 is connected to the output end of the pulse generation circuit 85, which is the output end of the monitor circuit 402, and the third input end of the OR gate 610 is connected to the light emission start signal A to the main circuit 500. The output terminal of the OR gate 42 which sends out is connected. And the above ORGATE 61
The output terminal of 0 is connected to the FF times PIi6110 input terminal,
The output terminal of the circuit 611 derives a light emission start control signal q,
This signal is applied to the first input terminal of the OR gate 522 of the main circuit 500. Furthermore, the output terminal of the pulse generating circuit 73 is connected to one input terminal of the OR gate 612.
The other input end of is connected to the output end of the pulse generation path 85. Furthermore, the output terminal of the gate 612 is an FF
It is connected to the input end of the circuit 613, and its output end is configured to derive the light emission stop signal H and apply it to the first input end of the OR gate 523 of the main circuit 500. The reset terminal is connected to the output terminal of delay circuit 614. And the above-mentioned delay (b) path 61
The input terminal of 4 is connected to the output terminal of AND gate 66. Further, the output terminal of the inverter 57 is connected to a pulse generation circuit 617.
The output terminal of the circuit 617 derives a light emission stop signal C2, which is applied to the second input terminal of the OR gate 523 of the main circuit 500. One input terminal of the OR gate 615 is connected to the output terminal of the pulse generation circuit 617, and the other input terminal is connected to the reset terminal of the pulse generation circuit 617 and the output terminal of the pulse generation circuit 46. . The output terminal of the OR gate 615 is connected to the FF circuit 61.
The output terminal of the circuit 616 is connected to the second input terminal of the OR gate 522 of the main circuit 500, and the output terminal of the circuit 616 derives the light emission start control signal F and applies it to the second input terminal of the OR gate 522 of the main circuit 500. Next, an explanation will be given of the operation of the dynamic type flat light emitting stop four-point device of the #I3 embodiment configured as shown in FIG. First, to explain the operation of the "dynamic flat light emission mode", in the case of this "flat light emission mode",
Since the movable contact terminal of the mode changeover switch 44 is switched to the first fixed contact terminal 44A side, the operating voltage B is supplied to the input terminal of the AND gate 40, and the AND gate 40 is opened. Since the L level output is supplied to the input 1iIiK of the AND gate 45 via the AND gate 45, the AND gate 45 is in a closed state. Therefore, it is now possible to input the 7-rat flash start signal without knowing the camera body, and the flash light start signal x2 is now allowed to be input.
input is no longer allowed. When the flat light emission stop signal is input, the output of the pulse generating circuit 41 is outputted as the light emission start signal A via the OR gate 42 via the capacitor 13 and resistor 12 of the main circuit 500 (see 2nd TL, figure). The trigger current is supplied to the gate of the trigger thyristor 10 and makes the thyristor 10 conductive, so that a trigger current flows from the trigger capacitor 8 to the primary side of the trigger transformer 9. On the other hand, since the signal A sets the FF circuit 611 via the OR gate 610, its H level output is supplied as the light emission start control signal G to the first input terminal of the OR gate 522 of the main circuit 500, and the transistor 507 , 501 are turned on one after another to make the thyristor 32 conductive. Then, as described above, since the trigger current flows through the primary side of the trigger transformer 9, the discharge tube 14 starts flash discharge, that is, starts emitting light. Further, at the same time as the start of the light emission, the pulse light emission circuit 41
With the single cut pulse at the H level, the integral operation of the monitor circuit section 402 is started in the same manner as in the second embodiment, and further, the counting of the preset counter 64 is started. As a result of emitting light as described above, the monitor voltage signal M
When reaches a predetermined level, the output of the operational amplifier 81 is inverted to the L level, and the output of the inverter 84 is inverted as in the second embodiment.
is transmitted to the pulse generating circuit 85 as an H level output, and further inputted to the OR gate 610, and further transmitted from the gate 610 to the input terminal of the FF circuit 611 at the H level, so that the circuit 611 is reset and the L level is output. Outputs a level signal. Then, the output of the OR gate 522 also goes to L level, while the output of the pulse generation circuit 85 is input to the OR gate 612, and further to the PF circuit 613.
Since the KH level output is input, the circuit 613 is set and outputs the H level. Then, or gate 52
Since the output of 5 is set to H level, the transistors 516 and 5
15 and 509 are made conductive in sequence, and the gate potential of the thyristor 32 is made lower than the ground potential. Then, the thyristor 32 stops conducting, and the discharge tube 14 also stops emitting light. On the other hand, the H level output of the pulse generating circuit 41 is
Set the circuit 67 and make the AND gate 71 conductive.
Therefore, an output pulse is applied to the preset counter 72 only when the oscillation side Wr6B outputs an H level. The output from this counter 72 is then sent to the pulse generating circuit 73.
The output pulse of the pulse generating circuit 73 is input to the FF circuit 611 via the OR gate 610, so the circuit 611 is set and outputs an H level signal. On the other hand, since the output of the pulse generation circuit 73 is also applied to the OR gate 612, the FF circuit 613 is operated in an inverted manner. Then, the circuit 613 outputs an L level signal, so the output of the OR gate 525 becomes L level, and the discharge tube 14 emits light again in the same manner as described above. By repeating such an operation, the discharge tube 14 is caused to emit light and stop continuously. After that, when the preset counter 64, which had started counting at 5 as described above, completes counting the number of counts corresponding to ##, - light time, the output of the FF circuit 65 becomes H level, and the AND gate 66 is opened. , the output of the pulse generation circuit 85 is output to RESET via the AND gate 66, and the delay time is output to the discharge tube 14.
The output of the delay circuit 614 is input to the reset terminal of the FF circuit 613, which is set to be longer than the deionization time of the circuit 6.
Reset 15. That is, during the first extinguishing time of the discharge tube 14, the thyristor 32 is kept in an OFF state to prevent the discharge tube 14 from emitting light again. Furthermore, the FF circuit 62, preset counter 64. The F'F circuit 65 is reset and all other circuits are reset to complete the series of dynamic flat light emission operations. Next, in the case of "r flash light emission mode", the movable contact terminal of the mode changeover switch 44 is switched to the second fixed terminal 44B, similar to the first embodiment described above. At this time,
) The output of the H signal of the pulse generation circuit 46 is the OR gate 6.
15, the FF circuit 616 is set and outputs an H level signal. Then, this is used as the light emission start control signal F.) 5
22 (see FIG. 20) to cause the discharge tube 14 to emit light, and also to cause the discharge tube 14 to emit light.
The signal is input to the reset terminal of the circuit 617, and the circuit 617 is reset. Then, after proper exposure, the output of the operational amplifier 56 is inverted and becomes the L level, which is further changed to the H level by the inverter 57, and the pulse generation circuit 617 supplies the H level (pulse signal) to the OR gate 615, so the FF circuit 616 outputs an L level signal. Also, during the above-mentioned proper exposure, an H level output is applied to the OR gate 523 as the light emission stop signal C2, so transistors 516, 515, and 509 are sequentially turned on, and the gate of the thyristor 62 is turned on. Reverse) (Iasu, same thyristor 3
2 to stop the discharge tube 14 from emitting light. In addition, resistance 5
If the resistance value of 06 is made too large, the turn-off time of the thyristor 32 becomes longer, so an appropriate resistance value must be selected. Note that the pulse width of the pulse generating circuit 6170 needs to be longer than the deionization time of the discharge tube 14. Further, even when the output signal of the pulse generation circuit 46 is applied to the reset terminal of the pulse generation circuit 617 and the output signal is being generated from the pulse generation circuit 617, the output signal from the pulse generation circuit 46 , the pulse generation circuit 617 is reset. The reason for this configuration is that the pulse width of the light emission stop signal C2 output from the pulse generating circuit 617 is set to be sufficiently longer than the deionization time of the discharge tube 14.
L-Kasp Magazine #Le Nobuta 1. When the freezing tank switching is performed, the light emission start control signal F is inputted to the OR gate 522 before the stop signal C2 of the generation circuit 617 changes from the H level to the L level, and the light emission start control signal F and the light emission stop signal F are input to the OR gate 522. signal C3
Both signals will be input to the thyristor 320 control section of the main circuit 500 at the same time. Since it is not preferable to simultaneously input signals of contradictory nature to the control section, the light emission stop signal C2 is intentionally shortened so that the light emission stops when a reverse bias is applied to the control section. This is to prevent In this way, it is possible to control the main thyristor 32 on and off, and to make the discharge tube emit light and stop it at minute intervals, without using a rapid charging capacitor. It goes without saying that a part of this embodiment can also be changed to the circuits shown in FIGS. 16 and 18 above. (30) "Figure 5 or" stated in the third line of page 58 of the same
Delete. (31) Add "," at the end of line 7 on page 58, add a new line, and add the following sentence. 20 is a circuit diagram showing the main circuit of a Dynamin octagonal flat light emitting strobe device according to a third embodiment of the present invention, and FIG. 21 is a control circuit connected to the main circuit shown in FIG. 20 above. (32) In the drawings attached to the application, No. 12.15.14.
Figures 16 and 18 will be revised as shown in the attached drawings. (33) Add the attached drawings in Figures 20 and 21 to the drawings attached to the application. Attachment ``2. Claims connecting circuit; and a monitor circuit for detecting the voltage of the main capacitor, and generating the light emission stop signal and the Doi light emission restart signal repeatedly during the exposure operation of the shutter in the camera. A dynamic flat light emitting device characterized in that the flash discharge tube is made to emit pulsed light repeatedly by causing the flash discharge tube to repeatedly emit light in a pulsed manner. (Voluntary) June 27, 1980 Manabu Shiga, Commissioner of the Patent Office1, Indication of the case Patent Application No. 82335 of 19822,
Title of the invention Dynamic flat light emitting strobe device 6, relationship to the amended person's case Address of patent applicant 2-43-2 Hatagaya, Shibuya-ku, Tokyo Name Title
(037) Olympus Optical Industry Co., Ltd. 4, Yoshikazu
Address 5-52-14 Matsubara, Setagaya-ku, Tokyo Name (7 (555) Fujikawa Nanabe (324-27)
00) 5. Subject of amendment The procedural amendment submitted dated June 1, 1980, 6. Contents of amendment The output level of the monitor circuit that detects the specified level is revised. (2) Lines 10 and 11 of page 5, lines 2 of page 6, lines 12, 17, and 19 of page 7 are truncated at the beginning and end of the line. and "luminescence" mentioned in the beginning of the 8th purchase, respectively, will be deleted and replaced. (6) The phrase ``1 flash'' written in line 7 on page 6 of the same will be changed to ``this''.

Claims (1)

[Scope of Claims] A series circuit of a main switching element connected in series to a flash discharge tube, each switching element connected at both ends to a main capacitor for rapid charging and commutation of a commutating capacitor, a commutation capacitor inserted between a series circuit between the flash discharge tube and the main switching element, and a series circuit between the rapid charging switching element and the commutation switching element; A monitor circuit that detects the voltage of the main capacitor; and a light emission stop signal that closes the commutation switching element and opens the main switching element when the output voltage of the monitor circuit reaches a predetermined level. generate,
The flash discharge tube starts its operation in response to the light emission stop signal, and generates a light emission restart signal for re-closing the main switching element 1 after a predetermined time shorter than the deionization time in the flash discharge tube, and a control circuit that generates a quick charge signal for closing a switching element of the camera; and a control circuit that repeatedly generates the light emission stop signal, the light emission restart signal, and the quick charge signal during an exposure operation of a shutter in the camera. A dynamic flat light emitting strobe device characterized in that the flash discharge tube is heated to 5tC so as to repeatedly emit light in a pulsed manner.