JPH0695191B2 - Strobe device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a strobe device for performing stroboscopic photography in synchronism with shutter release, and more specifically, to repeatedly perform pulsed light emission by a flash discharge tube to emit the light. The present invention relates to a dynamic flat light emitting strobe device having a substantially constant intensity.

(Prior Art) Generally, the emission intensity of a flash discharge tube in a strobe device is
It has a peak shape, and increases sharply from the start of light emission, and the light emission ends in an extremely short time of several milliseconds (see the characteristic S _{0 in} FIG. 1).

Therefore, in a camera adopting the focal plane shutter, there is a problem that the strobe cannot emit synchronized light at a high speed shutter time longer than the strobe synchronization time, and normal stroboscopic photography cannot be performed. That is, when the shutter speed is higher than the flash synchronization time, the focal plane shutter does not fully open, and the slit formed by the front curtain and the rear curtain runs in front of the film surface. No matter which point the flash device flashes, only part of the film surface is exposed by the flash light,
It was not possible to take a photo of uniform exposure.

Therefore, in order to solve the above problems, a flat flash strobe device (hereinafter, this is called a static type flat flash device) that keeps flashing at a substantially constant intensity while the slit is running in front of the film surface. A flash strobe device) has already been provided (characteristics in FIG. 1).
See S _1. ). This static type flat light emission strobe device has a series circuit of a flash discharge tube, an inductor, and a switching element at both ends of a main capacitor in which light emission energy is stored, as described in, for example, JP-A-55-129327. The basic circuit configuration is that the diodes are connected in parallel to the series circuit formed by connecting the flash discharge tubes and the inductor. Then, the amount of light emitted from the flash discharge tube is monitored, and when the amount of light emitted from the flash discharge tube falls below a predetermined value, the switching element is turned on, and conversely, when the light amount exceeds a predetermined value, the switching element is turned off. Flat light emission with a constant light intensity is performed. To detect the amount of light at this time, an opening is formed in a part of the reflector for irradiating the light emitted from the flash discharge tube to a predetermined range of the subject, and a light receiving element such as a photodiode or a phototransistor is provided in this opening. , Is performed based on the output signal of this light receiving element. However, since the output signal of such a light receiving element is an output of a minute level, its electric circuit is a circuit corresponding to a minute level, and therefore, this circuit is very vulnerable to external noise and the flash discharge tube The high-voltage trigger signal that triggers the signal may cause a malfunction. Further, the high-voltage trigger signal may be transmitted to the light receiving element via the stray capacitance or the like, and the element may deteriorate or malfunction.

Further, in a conventional static type flat light emission strobe device, an impedance element such as a resistor is inserted in series with the flash discharge tube, and a discharge current of the flash discharge tube flowing in the impedance element is detected. When the on / off control of the switching element is performed, the light emission loss due to the impedance element increases, and the relationship between the light emission intensity and the change and the change in the discharge current do not match, and accurate light emission control is performed. May not be possible.

Further, when the terminal voltage of the flash discharge tube is detected and the switching element is turned on / off based on the detected voltage, the transient voltage generated by turning on / off the switching element causes On / off control of the switching element may cause a malfunction.

Furthermore, in the conventional static type flat light emission strobe device, the light emission amount of the flash discharge tube or a monitor value substantially equivalent to this light emission amount is compared with a preset reference value, and when the monitor value exceeds the reference value, The switching element is turned off, and conversely, when the monitor value becomes lower than the reference value, the switching element is turned on. Therefore, since the switching element is ON / OFF controlled between the upper limit value and the lower limit value that are extremely close to each other with the reference value as a boundary,
There is a problem that an extremely high precision circuit configuration is required, the circuit configuration becomes complicated, and malfunctions easily occur due to variations in the constituent elements of the circuit.

(Object) The present invention has been made in view of the above circumstances, and an object of the present invention is to control a flash discharge tube so as to repeatedly perform pulsed light emission, thereby achieving a conventional static flat light emission. It is to provide a flat light emission strobe device (hereinafter referred to as a dynamic type flat light emission strobe device) which can obtain a light emission characteristic substantially equivalent to that of a strobe device, and particularly requires high accuracy in opening / closing control of a main switching element. There is no simple circuit configuration to achieve.

(Outline) The dynamic flat flash device of the present invention is
The semiconductor switching element connected in series to the flash discharge tube is turned off when the output level of the monitor circuit for detecting the voltage of the main capacitor reaches a predetermined level,
The ON operation of the semiconductor switching element is performed between the stop of light emission of the flash discharge tube and the deionization time of the flash discharge tube. The OFF operation and the ON operation of the semiconductor switching element are performed. It is characterized in that the pulsed light emission by the flash discharge tube is repeatedly generated during the shutter exposure operation of the camera by repeatedly performing the above.

(Example) Next, prior to explaining the present invention, the extent to which the light emission interval of continuous pulsed light emission according to the present invention can be practically reduced in relation to the slit exposure time will be described.

If the tube is t during slit exposure and the light emission interval is P, the time t
The number n of light emission during the period is given by the following equation.

n = t / P ……… For simplification of the theoretical formula, if the emission time width of each pulsed emission is treated as “0”, “n” will be an integer value. Therefore, if t / P is an integer value: n = [T / P] ..... When t / P is not an integer value: n = [t / P] or n = [t / P] +1. Here, the Gauss symbol [a] represents the maximum integer that does not exceed the real number a.

The above equation will be described with reference to FIG. 2. The hatched portion of the exposure time in the figure is [t / P] +1 (= 4),
It can be seen that the white areas are exposed with the light emission of [t / P] (= 3). Further, since the light emission time width is set to "0" as described above, one of the intersection points on the front side or the rear side in the exposure diagonal line in FIG. 2 is not calculated.

As shown in FIG. 2, if ideal slit exposure that is uniform over the entire screen is considered, a uniform illumination effect can be obtained by selecting “P” as a common divisor of “t”. The maximum value of can be set to "t". However, as is well known, the actual focal plane shutter itself has variations in the exposure time for each screen portion due to the difference in the running characteristics of the front and rear curtains. Exposure unevenness is now ± dstep
Consider a shutter with a nominal exposure time T guaranteed to. Actual exposure time in the shutter will range from a maximum 2d ^× T (shortest side) by screen portion 2d × T (longest side). Therefore, the number of times of light emission included in each limit time with the light emission interval being “P” is That is as described above. Reference value [T /
Considering the difference with respect to P] under the worst condition, the shortest side has a small value and the longest side has a large value. Therefore, the step difference from the reference value on the shortest side. Step difference from the reference value on the longest side To simplify the formula, if the light emission interval P is a common divisor of [T],
Since T / P is always an integer, T / P = n (integer),
The expressions are Becomes Further, subtracting each original shutter exposure time unevenness, that is, ± dstep from this value, the exposure value unevenness ΔEV1 increased by the strobe light is obtained.
(N) and ΔEV2 (n) can be calculated.

When the above equations ′ and ′ are calculated with the eigenvalues d for each shutter being 0.1, 0.2 and 0.3 respectively, the results are as shown in Tables 1-3.
The characteristics when the above equations and equations are calculated based on this and graphed are as shown in FIG. In addition, the first
Each of P = 1024, 512, 256, 128, ... Shown in Table 3 is a value corresponding to each of the nominal exposure time T per second 1/1000, 1/500, 1/250, 1/125. Further, as can be seen from the above Tables 1 to 3 and FIG. 3, if the allowable increase value of unevenness when using the flash is 0.1, "n" is 10, that is, T / P = n = 10, "P" Should be selected, or if the above-mentioned allowable value is 0.2, "P" should be selected such that T / P = n = 4. It goes without saying that the change in "T" is reduced if the number of pulses included is not large, so that "T" may take the nominal maximum second. That is, in a camera with a nominal exposure time T of up to 1/1000 seconds, the exposure unevenness of which is guaranteed at 0.2 EV,
If you want to suppress the increase to 0.1 EV, 1/1000 × 1 / P = 10, P = 1 /
"P" set to 10000 is the minimum pulse width allowed, and if 0.2EV is acceptable, "P" can be up to 1/4000. This is a numerical value that can be achieved with sufficient margin in the technique of the present invention.

If the light emission pulse interval is selected as described above, it can be regarded as substantially uniform exposure.

Next, a first embodiment of the dynamic flat flash device will be described with reference to FIGS.

The dynamic flat flash device according to the present embodiment is configured to have two functions, a "dynamic flat flash mode" and a "flash flash mode". First,
The configuration of the main circuit 100 will be described. The main circuit 100 is provided with a step-up power supply circuit 1 composed of a well-known DC-DC converter, and the negative output terminal of the circuit 1 has a negative voltage supply line.
It is connected to l ₀ (hereinafter abbreviated as line l ₀ ) and is grounded. The positive electrode output terminal of the circuit 1 is connected to the positive voltage supply line l ₁ (hereinafter line l ₁
(Abbreviated as)). Between both lines l ₀ and l _1, there is a main capacitor 3 which is the main power source for strobe light emission.
Is connected with a voltage dividing circuit consisting of a series circuit of resistors 4 and 5, and the monitor voltage signal M is connected from the connection point of both resistors 4 and 5.
Is sent. Also, both lines l ₀ , l ₁
A charge completion detection circuit composed of a series circuit of a resistor 6 and a neon lamp 7 is connected between them, and a trigger capacitor 8 and a primary coil of a trigger transformer 9 are sequentially connected to a connection point between the resistor 6 and the neon lamp 7. Connected to line l ₀ through. The connection point between the trigger capacitor 8 and the resistor 6 is connected to the anode of the thyristor 10 for triggering, the cathode is connected to the line l ₀ , and the gate is connected to the line l ₀ via the resistor 11. The light emission trigger signal A is supplied to the gate of the thyristor 10 via the resistor 12 and the capacitor 13. One end of the secondary coil of the trigger transformer 9 is connected to the line ₁₀ and the other end is connected to the trigger electrode of the flash discharge tube 14 such as a quinocene discharge tube, and one electrode of the flash discharge tube 14 is connected to the line l _0. Connected to ₁ . A series circuit including a resistor 15, a commutation capacitor 16, and a resistor 17 is sequentially connected between the lines l ₀ and l ₁ . In addition, a thyristor 18 is provided for causing the commutation capacitor 16 to be rapidly charged, and the anode of the thyristor 18 has a line l ₁
The cathode is connected to the connection point between the resistor 15 and the commutation capacitor 16, and is connected to its own cathode through the gate resistor 19. In addition, the gate of the thyristor 18 is provided with a quick charge signal D through a resistor 20 and a capacitor 21 sequentially.
Are being supplied. The cathode of the thyristor 18 is connected to the anode of the thyristor 22 for commutation, and the cathode of the thyristor 22 is connected to the line l ₀ . The gate of the thyristor 22 is connected to the line l ₀ via the resistor 23, and the gate is connected to the output end of the OR gate 26 via the resistor 24 and the capacitor 25, and the two input ends of the OR gate 26 are connected. Two systems of light emission stop signals C ₁ and C ₂ are supplied to each.

The other discharge electrode of the flash discharge tube 14 is a commutation capacitor.
It is connected to the connection point between 16 and the resistor 17 and to the anode of the main thyristor 27. The cathode of the main thyristor 27 is connected to the line l ₀ , and the gate is
It is connected to the line l ₀ via the resistor 28. The gate of the thyristor 27 is connected to the output terminal of the OR gate 31 through the resistor 29 and the capacitor 30 in sequence, and the gate of the OR gate 31 is connected.
The light emission start signal B ₁ and the light emission restart signal are respectively applied to the two input terminals.
B ₂ and are supplied.

A control circuit 200 described below is connected to the main circuit 100 configured as described above. That is, as shown in FIG. 5, the control circuit 200 includes a light emission interval setting circuit unit 201, a monitor circuit unit 202, and a photometric circuit unit 203.

A flat light emission start signal x ₁ from a camera body (not shown) is supplied to _one input end of the AND gate 40, and the output signal of the AND gate 40 has an input signal at a low level (hereinafter, L level). Level) to high level (hereinafter
It is connected to the input terminal of a pulse generation circuit 41 which outputs a pulse of H level having a predetermined width when it rises to (H level). The output end of the pulse generation circuit 41 is an OR gate 42.
One of the input ends of the OR gate 42 is connected, and the light emission trigger signal A and the light emission start signal B ₁ are transmitted from the output end of the OR gate 42. The other input end of the AND gate 40 is connected to the input end of the inverter 43 and the movable contact terminal of the mode changeover switch 44. Same mode selector switch
The first fixed contact terminal 44A of 44 is connected to the terminal to which the positive power source + B is applied, and the second fixed contact terminal 44B is grounded.

The flash light emission start signal x ₂ from the camera body (not shown) is supplied to one input end of the AND gate 45, and the output end of the inverter 43 is connected to the other input end. The output end of the AND gate 45 is connected to the input end of a pulse generation circuit 46 similar to the pulse generation circuit 41, and the output end of the pulse generation circuit 46 is the OR gate 42.
Of the RS type flip-flop circuit (hereinafter abbreviated as FF circuit) 47. The output terminal of the FF circuit 47 is connected to the base of an NPN type switching transistor 50 through an inverter 48 and a resistor 49 in order. Positive power supply + B
A series circuit of a resistor 51 and a variable resistor 52 that is set based on ISO sensitivity, aperture, etc. is connected between the terminal to which the voltage is applied and the ground terminal, and the collector and collector of the NPN phototransistor 53 are connected. A series circuit in which an emitter, a resistor 54, and a capacitor 55 for integration are sequentially connected is connected. The connection point between the resistor 51 and the variable resistor 52 is connected to the non-inverting input terminal of an operational amplifier 56 forming a voltage comparison circuit.
The connection point of the resistor 54 and the capacitor 55 is connected to the inverting input terminal of 56. The collector and emitter of the transistor 50 are connected to both ends of the capacitor 55, respectively.

The output terminal of the operational amplifier 56 is connected via the inverter 57 to the input terminal of a pulse generating circuit 58 similar to the pulse generating circuit 41, and the output terminal of the circuit 58 is connected to the reset input terminal of the FF circuit 47. The light emission stop signal C ₂ is sent from the output end of the pulse generation circuit 58.

The output end of the pulse generation circuit 41 is connected to one input end of an OR gate 59, and the output end of the OR gate 59 is an FF circuit 60.
Of the FF circuit 60, and the output terminal of the FF circuit 60 is connected to the input terminal of the inverter 61. The output end of the pulse generation circuit 41 is connected to the set input end of the FF circuit 62, and the output end of the FF circuit 62 is connected to one input end of the AND gate 63. The output terminal of the AND gate 63 is connected to the count input terminal of the preset counter 64, the count output terminal of the preset counter 64 is connected to the set input terminal of the FF circuit 65, and the output terminal of the FF circuit 65 is the AND gate 66. Is connected to one input end. Same and gate
The output terminal of 66 is connected to the reset input terminals of the FF circuits 62 and 65 and the preset counter 64, respectively. Also,
From the output end of the AND gate 66, a reset signal RESET for resetting the entire control circuit 200 is sent.

In the preset counter 64, the data x ₃ based on the total light emission time U ₁ in the dynamic flat light emission is preset, and this time U ₁ is the time after the front curtain starts running and the film is exposed. It is set to a time longer than the time when the trailing curtain finishes traveling and film exposure ends.

The other input end of the AND gate 66 is connected to the reset input end of the FF circuit 60. The other input end of the AND gate 63 is connected to the output end of the oscillation circuit 68. A resistor 69 for setting an oscillation frequency and a capacitor 70 are connected between the oscillation circuit 68 and an application terminal of the power source + B. The output end of the oscillation circuit 68 is connected to one input end of the AND gate 71, and the other input end of the AND gate 71 is connected to the output end of the FF circuit 67. The output terminal of the AND gate 71 is connected to the count input terminal of the preset counter 72. The output terminal of the preset counter 72 is connected to the input terminal of a pulse generating circuit 73 similar to the pulse generating circuit 41,
The output terminal of the pulse generating circuit 73 is connected to the input terminal of the delay circuit 74. The quick charge signal D is sent from the output terminal of the delay circuit 74. In this delay circuit 74, the delay time γ is set.

In the preset counter 72, data x ₄ based on the light emission interval time U _{2 from the} time when the light emission of the pulsed light emission is stopped to the time when the light emission of the next pulsed light emission is restarted in the dynamic flat light emission is preset. This time U ₂ is set based on the shutter speed and the like. The output terminal of the pulse generation circuit 73 is connected to the FF circuit 67 and the reset input terminal of the preset counter 72, and is also connected to the other input terminal of the OR gate 59. A light emission resumption signal B ₂ is sent from the pulse generation circuit 73.

On the other hand, the resistor 75 to which the monitor voltage signal M is supplied from the main circuit 100 is connected to the inverting input of the operational amplifier 76 forming the inverting amplifier circuit, and the resistor 77 is provided between the inverting input terminal and its own output terminal. Connected and the non-inverting input is grounded.
The output terminal of the operational amplifier 76 is connected to the inverting input terminal of an operational amplifier 79 forming an integrating circuit via a resistor 78 for integration,
A capacitor 80 for integration is connected between the inverting input terminal and its own output terminal. The non-inverting input terminal of the operational amplifier 79 is grounded. The output terminal of the operational amplifier 79 is connected to the inverting input terminal of the operational amplifier B ₁ forming a voltage comparison circuit. A voltage dividing circuit in which a resistor 82 and a variable resistor 83 are sequentially connected is connected between the terminal to which the power source + B is applied and the ground terminal, and the connection point between the resistor 82 and the variable resistor 83 is an operational amplifier 81.
Connected to the non-inverting input of. The variable resistor 83 is a resistor that is set according to the shutter speed and the like. The output terminal of the operational amplifier 81 is connected to the other input terminal of the AND gate 66 through the inverter 84 and the pulse generating circuit 85 in order. The light emission stop signal C ₁ is sent from the pulse generation circuit 85.

The collector of an NPN type switching transistor 86 is connected to the output terminal of the operational amplifier 79.
The emitter is grounded, and the base is connected to the output end of the inverter 61 via the resistor 87.

Next, the operation of the thus constructed dynamic flat flash device of the present embodiment will be described.

First, the operation of the "dynamic flat light emission mode" will be described with reference to FIGS. 6, 7 and 8. In this "flat light emission mode", the movable contact terminal of the mode changeover switch 44 has the first fixed contact. Since it is switched to the contact terminal 44A, the positive power supply + B is supplied to the input end of the AND gate 40 to open the AND gate 40, and the output of the L-bell to the input end of the AND gate 45 via the inverter 43. Since it is supplied, the AND gate 45 is closed. Therefore, the flat light emission start signal x ₁ is allowed to be input from the camera body, and the flash light emission start signal x ₂ is not allowed to be input. And the flat emission start signal x ₁
Rises to the H level, the output of the AND gate 40 becomes the H level, and the pulse generating circuit 41 outputs the H level one-shot pulse. This H-level pulse is applied to the gate of the trigger thyristor 10 via the OR gate 42 as the light emission trigger signal A via the capacitor 13 and the resistor 12 to make the trigger thyristor 10 conductive. When the trigger thyristor 10 is turned on, both ends of the trigger capacitor 8 are short-circuited via the primary coil of the trigger transformer 9, and the discharge current of the charge charged in the trigger capacitor 8 flows to the primary coil of the trigger transformer 9. As a result, a high voltage is generated in the secondary coil, and this high voltage is applied to the trigger electrode of the flash discharge tube 14, and the flash discharge tube 14 is excited. At the same time, the H-level one-shot pulse output from the pulse generation circuit 41 makes the main thyristor 27 conductive via the OR gate 42, the capacitor 30, and the resistor 29 as the light emission start signal B ₁ . Main thyristor
When 27 is turned on, the electric charge charged in the main capacitor 3 is discharged through the flash discharge tube 14 in the excited state and the anode / cathode of the main thyristor 27, and the flash discharge tube 14 starts flash emission. Further, at the same time, the H level one-shot pulse output from the pulse generation circuit 41 sets the FF circuit 60 via the OR gate 59, and
The output of the FF circuit 60 becomes H level. This H level output is inverted to the L level by the inverter 61, so that the transistor 86 is turned off.

Further, since the FF circuit 62 is set by the H-level one-shot pulse output from the pulse generation circuit 41,
The output of the FF circuit 62 is inverted to the H level, the AND gate 63 is opened accordingly, and the output pulse of the oscillation circuit 68 is input to the preset counter 64 to start counting.

On the other hand, the monitor voltage signal M obtained by dividing the voltage of the main capacitor 3 by the resistors 4 and 5 is inverted and amplified by the operational amplifier 76 forming the non-inverting amplifier circuit, and this inverted and amplified voltage signal is resistor 78 and the capacitor 80. It is integrated by the time constant determined from. The output voltage of the operational amplifier 79 at this time is applied as the comparison voltage V _IN to the inverting input terminal of the operational amplifier 81 forming the voltage comparison circuit, and the reference voltage V _REF obtained by dividing the voltage of the positive power supply + B by the resistor 82 and the variable resistor 83.
Compared to. When the voltage of the main capacitor 3 is high, as shown in the characteristic a of FIG. 7, the comparison voltage V _{IN
Takes a} short time t ₁ to reach the reference voltage V _REF, and when the voltage of the main capacitor 3 is low, the time t ₂ until the comparison voltage V _IN reaches the reference voltage V _REF as shown by the characteristic b in FIG.
Takes a long time. Comparison voltage V _IN reaches the reference voltage V _REF, V _IN
When ≧ V _REF , the output of the operational amplifier 81 becomes L level. The L level output of the operational amplifier 81 is the inverter 84.
When it is inverted to H level at, an H level one-shot pulse is generated at the output of the pulse generation circuit 85. The H level pulse makes the commutation thyristor 22 conductive as the light emission stop signal C _{1 through the} OR gate 26, the capacitor 25, and the resistor 24 in order. When the commutation thyristor 22 is turned on, the charged commutation capacitor 16 reverse-biases the anode / cathode of the main thyristor 27, so that the main thyristor 27 is turned off. Further, since the FF circuit 60 is reset at the rising of the H level of the light emission stop signal C ₁ ,
The AND gate 71 is opened and the output pulse of the oscillation circuit 68 is input to the preset counter 72 to start counting. Also, at the rising of the H level of the light emission stop signal C ₁ , the FF circuit
Since 60 is reset, the output of the FF circuit 60 is inverted to the L level, the transistor 86 is turned on accordingly, and the inverting input terminal of the operational amplifier 81 is forcibly set to the ground level. The monitor circuit 202 that detects the monitor output voltage signal M substantially does not work.

When the preset counter 72 completes counting the number of counts corresponding to the light emission interval time U ₂ , the output of the preset counter 72 becomes H level, and accordingly, the output terminal of the pulse generating circuit 73 becomes H level. A pulse is generated. This H-level pulse is applied to the gate of the main thyristor 27 through the OR gate 31, the capacitor 30, and the resistor 29 in order as the light emission restart signal B ₂ , and the main thyristor 27
To conduct. Then, at this time, since the flash discharge tube 14 has not passed the deionization time from the previous stop of light emission, the discharge tube 14 resumes light emission only when the main thyristor 27 is turned on. At the same time, the FF circuit 67 and the preset counter
72 is reset. Further, since the light emission restart signal B ₂ of the H level pulse sets the FF circuit 60 via the OR gate 59, the output of the FF circuit 60 is inverted to the H level, and the output of the inverter 61 is changed to the L level accordingly. At level, transistor 86 turns off. Therefore, as in the previous case, the integrating operation of the monitor output voltage M is restarted by the operational amplifier 79.

Further, the light emission restart signal B ₂ of the H level pulse is delayed by the time γ by the delay circuit 74, and the capacitor 21 and the resistor 20 are sequentially applied to the gate of the thyristor 18 as the rapid charge signal D of the H level pulse. Conduct 18 When thyristor 18 becomes conductive, line l ₁ → thyristor 18
The anode / cathode → the commutation capacitor 16 → the anode / cathode of the main thyristor 27 → the main path of the line l ₀ is rapidly charged to the commutation capacitor 16 in an extremely short time. When the charging of the capacitor 16 is completed, the power supply to the thyristor 18 becomes less than the holding current, and the thyristor 18 becomes non-conductive. Then, when the output voltage of the operational amplifier 79, that is, the comparison voltage V _IN exceeds the reference voltage V _REF , the output of the operational amplifier 81 is inverted to the L level. When the output of the op amp 81 becomes L level, the output of the inverter 84 becomes H level, and the pulse generation circuit 85 outputs the pulse emission stop signal C _{1 of} H level in the same manner as above. Similarly, since the light emission restart signal B ₂ and the quick charge signal D become H level pulses, the light emission waveform in the flash discharge tube 14 becomes a continuous pulse.

When the preset counter 64 completes counting the number of counts corresponding to the total light emission time U ₁ , the FF circuit 65 is set and the output of the FF circuit 65 is inverted to the H level. When the light emission stop signal C ₁ is generated, the light emission stop signal C _{1 at} this time is obtained as a reset signal RESET through the AND 66. Reset signal RES
When ET occurs, the reset signal RESET resets the FF circuit 62, the preset counter 64, and the FF circuit 65, and resets all other circuits, thus ending a series of dynamic flat light emission operations.

In the "flat emission mode" described above, the movable contact terminal of the mode changeover switch 44 is the first fixed terminal 44A.
Since one of the AND gates 45 is switched to the L level, one of the input ends of the AND gate 45 is at the L level.
Even when the flash light emission start signal x ₂ is input from the camera when the gate of the pulse generator is closed, the circuits after the pulse generation circuit 46 are not affected at all. With this, the inverter 48
Since the output of is the H level, the transistor 50 is always turned on, and there is no possibility that the photometry circuit section 203 outputs the light emission stop signal C _{2 for} stopping the light emission.

Next, the operation in the "flash emission mode" will be described with reference to FIGS. 9 and 10. When the movable contact terminal of the mode changeover switch 44 is switched to the second fixed terminal 44B and the "flash light emission mode" is selected, the strobe device of the present embodiment has the other input end of the AND gate 40. Goes to the L level, the AND gate 40 is closed, the flat light emission start signal x ₁ is not accepted, and the other input end of the AND gate 45 goes to the H level, and the AND gate 45 opens and flashes. Start signal x ₂ will be accepted.

That is, when the flash light emission start signal x ₂ is input from the camera, the output of the AND gate 45 becomes H level, an H level pulse is generated in the pulse generation circuit 46, and this H level pulse is passed through the OR gate 42. As the light emission trigger signal A,
The trigger thyristor 10 is made conductive via the capacitor 13 and the resistor 12. Also, as the light emission start signal B ₁ , OR gate 3
The main thyristor 27 is made conductive via the capacitor 1, the resistor 29 and the resistor 29. Therefore, the electric charge accumulated in the main capacitor 3 is discharged through the flash light discharge tube 14 and the main thyristor 27, and the flash light discharge tube 14 starts flash light emission. Further, the H level output of the pulse generation circuit 46 sets the FF circuit 47, the output of the FF circuit 47 is inverted to the H level, and the transistor 50 whose base is brought to the L level through the inverter 48 and the resistor 40 is turned off. Become. Therefore, the photocurrent generated in the phototransistor 53 is integrated by the capacitor 55, and the photometric circuit unit 203 starts photometry.

Then, in the photometry circuit section 203, when the integrated voltage of the capacitor 55 exceeds the reference voltage which is the connection point voltage of the resistors 51 and 52, the output of the operational amplifier 56 is inverted to L level and the output of the inverter 57 is H level. And the pulse generator 58
An H-level pulse from the output end of the thyristor as a light emission stop signal C ₂ via the OR gate 26, the capacitor 25, and the resistor 24.
Conduct 22.

As a result, the main thyristor 27 is turned off and the light emission is stopped in the same manner as the operation in the "flat light emission mode" described above. Therefore, the strobe device of the present embodiment functions as a normal austro strobe device when the movable contact terminal of the mode changeover switch 44 is switched to the fixed terminal 44B.

Next, a second embodiment of the present invention will be described with reference to FIGS. 11 to 15. Like the first embodiment, this embodiment is also configured to have two functions, a "dynamic flat light emission mode" and a "flash light emission mode". First, the main circuit 30
The configuration of 0 will be described. This main circuit 300 is the same as the main circuit 100 (see FIG. 4) in the first embodiment except that only some of the elements are replaced.
The same reference numerals as those shown in the figure are attached, and detailed description thereof will be omitted.

The anode / cathode of a normally-on type electrostatic induction type (SI type) thyristor 32 is connected between the electrode of the flash discharge tube 14 and the line l _0, and the gate of the thyristor 32 is commutated. It is connected to the connection point between the capacitor 16 and the resistor 17. Also, the gate of the thyristor 32 is connected to the cathode of the thyristor 33, the anode of the thyristor 33 is connected to the line l ₀ , and the resistance between the gate and its own cathode is
34 is connected. The gate of the thyristor 33 has a resistance of 35.
A light emission restart signal E is supplied through the capacitor 36 and the capacitor 36 in sequence.

A control circuit 400 having a circuit configuration as shown in FIG. 12 is connected to the main circuit 300 thus configured. The control circuit 400 is configured to include a light emission interval setting circuit unit 401, a monitor circuit unit 402, and a photometric circuit unit 403, and only some of the elements of the control circuit 200 in the first embodiment are changed, and the other components are Since they are the same, the same elements are denoted by the same reference numerals as those shown in FIG. 5, and their details are omitted.

The light emission stop signal E is sent from the output terminal of the pulse generation circuit 73 which constitutes the light emission interval setting circuit section 401. Unlike the circuit shown in FIG. 5, the output terminal of the pulse generation circuit 73 is not connected to the reset terminals R of the preset counter 72 and the FF circuit 67, and the OR gate 59 is not connected.
Is not connected only to the input terminal of, but is connected only to the input terminal of the OR gate 59. The output end of the pulse generation circuit 41 is connected to the input end of the FF circuit 62 in the same manner as described above, and
Unlike the circuit shown in the figure, it is connected to the input terminal of the FF circuit 67. Further, the preset counter 72 is formed so as to output a one-shot pulse of H level when the count up to the count number corresponding to the data x ₄ is completed, and at the same time, to start counting again.

Further, the resistor 88 to which the monitor voltage signal M is supplied from the main circuit 300 to the monitor circuit section 402 is connected to the non-inverting input terminal of an operational amplifier 89 forming a non-inverting amplifier circuit,
The inverting input of 89 is grounded through resistor 90, this inverting input is grounded through resistor 90, and this inverting input is
It is grounded via 90, and a resistor 91 is connected between this inverting input terminal and its own output terminal. An integrating circuit in which a resistor 92 and a capacitor 93 are connected in series is connected to the output terminal of the operational amplifier 89. The NPN type switching transistor 94 has an emitter and a collector connected to both ends of the capacitor 93, and the emitter is grounded. The base of the transistor 94 is an inverter 61 via a resistor 95.
Is connected to the output end of. The connection point between the resistor 92 and the capacitor 93 is connected to the inverting input terminal of the operational amplifier 81.

Next, the operation of the dynamic flat flash device of the second embodiment having such a configuration will be described.

First, the operation in the "dynamic flat light emission mode" will be described with reference to FIGS. 13 and 14. In the case of the "flat light emission mode", the movable contact terminal of the mode changeover switch 44 is the first fixed contact terminal 44A. Since it is switched to the side, the positive power source + B is supplied to the input end of the AND gate 40 to open the AND gate 40, and the L level output is supplied to the input end of the AND gate 45 via the inverter 43. Therefore, the AND gate 45 is closed. Therefore, the flat light emission start signal x ₁ is allowed to be input from the camera body, and the flash light emission start signal x ₂ is not allowed to be input. When the flat light emission start signal x ₁ is inputted, the trigger thyristor is triggered by the light emission trigger signal A from the output end of the OR gate 42 as in the case of the above embodiment.
10 is turned on and the flash discharge tube 14 is excited. Then, the electric charge charged in the main capacitor 3 is discharged through the flash discharge tube 14 in the excited state and the anode / cathode of the main thyristor 32, and the flash discharge tube 14 starts flash emission. Further, at the same time, the pulse generation circuit 41
The H-level one-shot pulse output from the OR sets the FF circuit 60 via the OR gate 59, and the output of the FF circuit 60 becomes the H level. This H-level output is inverted to the L level by the inverter 61. As a result, the transistor 96 is turned off, and the integration operation of the monitor circuit unit 402 is started.

Further, since the FF circuit 62 is set by the H-level one-shot pulse output from the pulse generation circuit 41,
The output of the FF circuit 62 is inverted to the H level, the AND gate 63 is opened accordingly, and the output pulse of the oscillation circuit 68 is input to the preset counter 64 to start counting.
Further, since the FF circuit 67 is set by the H level one-shot pulse output from the pulse generation circuit 41, the output of the FF circuit 67 is inverted to the H level, and the AND gate 71 is opened accordingly, and the oscillation is generated. The output pulse of the circuit 68 is input to the preset counter 72 and counting is started.

On the other hand, the monitor voltage signal M obtained by dividing the voltage of the main capacitor 3 by the resistors 4 and 5 is amplified by the operational amplifier 89 forming a non-inverting amplifier circuit, and the amplified voltage signal is divided by the resistor 92 and the capacitor 93. It is integrated by the time constant. The integrated voltage at this time is applied as the comparison voltage V _IN to the inverting input terminal of the operational amplifier 81, and the voltage of the positive power supply + B is divided by the resistor 82 and the variable resistor 83 to be compared with the reference voltage V _REF . Then, when the output of the operational amplifier 81 becomes L level, that is, V _IN ≧ V _REF , at this time, this L level output is inverted to H level by the inverter 84, and the output of the pulse generation circuit 85 becomes H level one shot. A pulse is generated, and this H-level pulse makes the commutation thyristor 22 conductive through the OR gate 26, the capacitor 25, and the resistor 24 in order as the light emission stop signal C ₁ . When the commutation thyristor 22 is turned on, the charge stored in the commutation capacitor 16 is charged.
→ Anode / cathode of commutation thyristor 22 → Discharge through the route of resistor 17. Then, at this time, the gate and cathode of the main thyristor 32 are reverse-biased, so that the main thyristor 32 instantly becomes non-conductive and the light emission stops. Since the flash discharge tube 14 has a deionization time, it is necessary to continuously maintain the reverse bias state during this deionization time. Therefore, it is necessary to set the time constant determined by the commutation capacitor 16 and the resistor 17 to the deionization time or more. Further, since the FF circuit 60 is reset when the light emission stop signal C ₁ rises to the H level, the FF circuit 60 is also reset.
Output is inverted to the L level, and accordingly, the transistor 94 is turned on, the charge of the capacitor 93 is discharged, and the monitor circuit section for detecting the monitor output voltage signal M is detected.
The 402 is essentially dead.

When the preset counter 72 completes counting the number of counts corresponding to the time U ₂ ′ of the light emission interval set to a time longer than the above time U ₂ , the output of the preset counter 72 becomes H level, and accordingly. Pulse generator 73
An H level pulse is generated at the output terminal of the. This H-level pulse is applied to the gate of the thyristor 33 as the light emission restart signal E through the capacitor 36 and the resistor 35 sequentially.

Therefore, since the thyristor 33 becomes conductive and both ends of the resistor 17 are short-circuited, the charge stored in the commutation capacitor 16 is transferred from the anode / cathode of the commutation thyristor 22 to the discharge path of the resistor 17 to the commutation thyristor 22. Since the path changes from the anode / cathode to the anode / cathode of the thyristor 33 and is discharged, the gate potential of the main thyristor 32 becomes substantially the ground potential and the main thyristor 32 becomes conductive. When the main thyristor 32 becomes conductive in this way, the flash discharge tube 14 in a state where the deionization time has not elapsed since the last stop of light emission resumes light emission. Further, since the light emission restart signal E of the H level pulse sets the FF circuit 60 via the OR gate 59, the output of the FF circuit 60 is inverted to the H level, and the output of the inverter 61 is accordingly changed to the L level. And transistor 94 is turned off. Therefore, this monitor circuit unit 40
The integration operation of the monitor output voltage M in 2 restarts.

Further, the light emission restart signal E is sent to the delay circuit 74 by the time γ
The thyristor 18 is made conductive by delaying it by a rapid charging signal D of H level pulse and sequentially applying it to the gate of the thyristor 18 through the capacitor 21 and the resistor 20. When the thyristor 18 becomes conductive, the line l ₁ → the anode / cathode of the thyristor 18 → the commutation capacitor 16 → the main thyristor 32
The gate / cathode → the main path of the line l ₀ allows the commutation capacitor 16 to be rapidly charged in an extremely short time. When the charging of the capacitor 16 is completed, the power supply to the thyristor 18 becomes less than the holding current, and the thyristor 18 becomes non-conductive. Then, when the integrated voltage by the resistor 92 and the capacitor 93, that is, the comparison voltage V _IN exceeds the reference voltage V _REF , the output of the operational amplifier 81 is inverted to the L level. When the output of the operational amplifier 81 becomes L level, the output of the inverter 84 becomes H level, and the pulse generation circuit 85 outputs the emission stop signal C ₁ of H level pulse as in the previous time. Similarly, since the light emission restart signal E and the quick charge signal D become H level pulses, the light emission in the flash discharge tube 14 becomes a continuous pulse.

When the preset counter 64 completes counting the number of counts corresponding to the total light emission time U ₁ , the FF circuit 65 is set, the output of the FF circuit 65 is inverted to the H level, and thereafter, the H level pulse When the light emission stop signal C ₁ is obtained, the signal C ₁ is sent through the AND gate 66 to the reset signal RE.
As the SET, the FF circuit 62, the preset counter 64, and the FF circuit 65 are reset and all the other circuits are reset, and a series of dynamic flat light emission operations are completed.

Next, when the movable contact terminal of the mode changeover switch 44 is switched to the second fixed terminal 44B and the "flash light emission mode" is selected, the operation of the "flash light emission mode" in the first embodiment is performed. Since the operation is similar to, the description thereof will be omitted. However, in this second embodiment, since the normally-on thyristor 32 is used, as is apparent from the comparison of the flowchart of FIG. 15 with the flowchart of FIG. As in the case, the light emission start signal B ₁ is unnecessary.

In the dynamic flat flash device of the second embodiment, a time setting circuit unit 404 as shown in FIG. 16 may be used instead of the light emission interval setting circuit unit 401 and the monitor circuit unit 402. That is, in the time setting circuit unit 404, the output end of the OR gate 59 is connected to the set input end,
The reset input terminal is connected to the output terminal of the pulse generation circuit 130, that is, the terminal to which the light emission stop signal C ₁ is transmitted.
The output terminal of the FF circuit 60 is connected to one input terminal of the OR gate 102 via the inverter 101, and the output terminal of the OR gate 102 is connected to the base of the NPN switching transistor 104 via the resistor 103. There is. Between the terminal of the positive power source + B and the ground terminal, a series circuit in which resistors 105 and 106 and an emitter / collector of the transistor 104 are sequentially inserted, and a series circuit in which a capacitor 107 for integration and a constant current circuit 108 are sequentially inserted. And are connected. The terminal of the positive power supply + B is connected to the emitter of the PNP type transistor 109, and the base of the transistor 109 is connected to the connection point between the resistor 105 and the resistor 106. The collector of the transistor 109 is connected to the connection point between the capacitor 107 and the constant current circuit 108.

Further, the output terminal of the inverter 101 is connected to one input terminal of the OR gate 110, and the output terminal of the OR gate 110 is connected through a resistor 111 to an NPN switching transistor 11 for switching.
2 connected to the base. Between the terminal of the positive power source + B and the ground terminal, a series circuit in which resistors 113 and 114 and a collector / emitter of the transistor 112 are sequentially interposed, and a series circuit in which an integration capacitor 115 and a constant current circuit 116 are sequentially interposed. And are connected. The terminal of the positive power source + B is connected to the emitter of the PNP type transistor 117, and the base of the transistor 117 is connected to the connection point between the resistors 113 and 114. The collector of the transistor 117 is connected to the connection point between the capacitor 115 and the constant current circuit 116.

The connection point between the capacitor 107 and the constant current circuit 108 is connected to the inverting input terminal of an operational amplifier 118 forming a voltage comparison circuit, and the connection point between the capacitor 115 and the constant current circuit 116 forms a voltage comparison circuit. It is connected to the inverting input terminal of the operational amplifier 119. The monitor voltage signal M is supplied to the non-inverting input terminals of both operational amplifiers 118 and 119 via resistors 120 and 121, respectively.

Further, the output terminals of the operational amplifiers 118 and 119 are respectively connected to the two input terminals of the OR gate 122, the output terminal of the OR gate 122 is connected to the set input terminal of the FF circuit 123, and the output terminal of the FF circuit 123 is It is connected to the input terminal of the inverter 124 and is also connected to the other input terminal of the OR gate 102. The output terminal of the inverter 124 is connected to the other input terminal of the OR gate 110. The output terminal of the FF circuit 123 is connected to the count input terminal of the preset counter 125. Same preset counter 12
5 is preset to a predetermined count number by data x ₅ . The count output end of the preset counter 125 is connected to the input end of the pulse generation circuit 130, and the light emission stop signal C ₁ is transmitted from the output end of the pulse generation circuit 130.

The operation of the time setting circuit unit 404 configured as described above is
A description will be given with reference to FIGS. When the output of the FF circuit 60 is at the L level, the output of the inverter 101 and the outputs of the OR gates 102 and 110 are at the H level, so that the transistors 104 and 112 are both turned on, and accordingly the transistors 109 and 117 are also turned on. Therefore, both ends of the capacitor 107 and both ends of the capacitor 115 are short-circuited. Therefore, the potentials of the inverting input terminals of the operational amplifiers 118 and 119 are substantially the same as the potential of the positive power source + B.
Therefore, the outputs of the operational amplifiers 118 and 119 are both at the L level, and the light emission time setting circuit unit 404
Is effectively disabled. And FF circuit
When the H level pulse from the OR gate 59 is input to the set input terminal of 60, the same FF circuit 60 is set, the output of the inverter 101 becomes L level accordingly, and the respective outputs of the OR gates 102 and 110 become It becomes dependent on the output state of the FF circuit 123. That is, when the output of the FF circuit 123 is at the L level, the output of the OR gate 102 is at the L level, so the transistor 104 is turned off. On the other hand, the output of the OR gate 110 is at the H level, the transistor 112.
Turns on. Accordingly, the transistor 109 is turned off and the transistor 117 is turned on.

Therefore, from this point, the constant current I flowing in the constant current circuit 108
The charging of the capacitor 107 is started by ₁ . And
The potential V _{1 at} the connection point between the capacitor 107 and the constant current circuit 108
As shown in FIG. 17 (A), it gradually decreases with the charging operation, and this potential V ₁ falls below the potential V _M of the monitor voltage signal _M , that is, the potential V _M of the non-inverting input terminal of the operational amplifier 118. When turned around, the output of the same operational amplifier 118 is inverted to the H level, and this H level signal is guided to the FF circuit 123 via the OR gate 122 and sets the same FF circuit 123, whereby the output V of the FF circuit 123 is set. _FF is inverted to H level. This FF circuit 123
Of the output V _FF of the H level signal turns on the transistor 104 via the OR gate 102 and the resistor 103, and accordingly, the transistor 109 turns on and the capacitor 107
The electric charge stored in the battery is discharged. At the same time, the output of the operational amplifier 118 is inverted to the L level again. At the same time, since the output of the inverter 124 becomes L level, the output of the OR gate 110 becomes L level, and the transistors 112 and 117 are both turned off. From this point, the constant current I ₂ flowing in the constant current circuit 116 causes the capacitor 115. Will start charging. Then, the capacitor 115 and the constant current circuit 116
The potential V ₂ at the connection point between the gradually decreases in the same manner as the potential V ₁ of the above, the potential V ₂ is the potential V _M of the monitor voltage signal M, that is, the potential V _M of the non-inverting input terminal of the operational amplifier 119 When it goes down, the output of the operational amplifier 119 is inverted to the H level. When this H-level signal is guided to the FF circuit 123 via the OR gate 122 and the FF circuit 123 is reset, the output of this FF circuit 123
V _FF is inverted to L level. Since the L level signal of the output V _FF of the FF circuit 123 is guided to the OR gate 102, the transistor 104 is turned off, and the signal is inverted by the inverter 124 and guided to the OR gate 110, so that the transistor 112 is turned on. the potential V ₂ rises to the potential of the positive power source + B, the potential V ₁ was begins to fall toward the potential V _M.

In the same manner, the above operation is repeated and the FF circuit
A pulse train signal is obtained as the output V _FF of 123. And
The cycle T _FF of the output V _FF of the FF circuit 123 is the monitor voltage signal M
When the potential V _M of the main capacitor is lower than that shown in FIG. 17 (A), that is, when the charging voltage of the main capacitor is low,
As shown in FIG. (B) becomes the period T _FF longer than the period T _FF '. On the contrary, when the potential V _M is higher than the state shown in FIG. 17 (A), the period becomes shorter than the period T _FF .

When the output V _FF of the FF circuit 123 is input to the preset counter 125, the preset counter 125 counts the number of pulses of preset data x ₅ , and when this count is finished, the preset counter 125 outputs the pulse generation circuit. An H level pulse is sent to 130, which causes
From the output terminal of the pulse generation circuit 130, an emission stop signal C ₁ of H level pulse is sent. Then, this light emission stop signal
The FF circuit 60 is reset by C ₁ , the output of the FF circuit 60 is inverted to the L level, and the initial state described above is restored. Then, the time setting circuit 404 does not work until the output pulse of the OR gate 59 occurs next time. In this way, since the light emission time of each pulse emission is determined by the state of the preset counter 125 depending on the pulse cycle of the output V _FF of the FF circuit 123, when the voltage of the main capacitor 3 is low, the emission of each pulse emission described above is performed. The time becomes long, and when the voltage of the main capacitor 3 is high, the light emission time becomes short. Therefore, the light emission amount per each pulse light emission can be kept constant regardless of the charging voltage of the main capacitor.

Further, the time setting circuit unit 40 having the configuration shown in FIG.
Instead of 4, a time setting circuit 405 configured as shown in FIG. 18 may be used. This time setting circuit unit 405 forms a voltage comparison circuit at the connection point between the capacitor 107 and the constant current circuit 108 of the constant current charging circuit which is the same as the constant current charging circuit in the time setting circuit unit 404 shown in FIG. The operational amplifier 128 is connected to the inverting input terminal thereof, the monitor voltage signal M is applied to the non-inverting input terminal of the operational amplifier 128 via the resistor 127, and the output terminal of the operational amplifier 128 is connected to the inverter 129.
Connected to the input end of the pulse generation circuit 130 via the inverter 126, and the output end of the FF circuit 60 via the inverter 126.
It is configured by connecting to 03. With this configuration, the integrated voltage V ₁₀ in the capacitor 107 can be the same as the monitor voltage signal M ₁₀ as in the case described with reference to FIGS.
When the potential V _M of the main capacitor 3 is high, that is, when the voltage of the main capacitor 3 is high, the integration time T _{10 is} increased as shown in FIG.
Becomes shorter, and conversely, when the potential of the monitor voltage signal M is low, the integration time T ₂₀ becomes longer as shown in FIG. 19 (B).
As a result, the lower the voltage of the main capacitor 3 is, the later the inversion time of the output level of the operational amplifier 128 is delayed, so that the emission time of each pulse emission becomes longer.

As described above, when the above pulsed light emission is continuously performed, the voltage of the main capacitor decreases with time. Therefore, if the light emission time of the short pulsed light emission is constant, the time for each pulsed light emission increases with time. The amount of light emission will decrease. Therefore, by changing the light emission time according to the voltage of the main capacitor 3, the light emission amount of each pulsed light emission can be made constant regardless of the voltage of the main capacitor 3.

Further, based on the above idea, if the light emission time is made constant and the light emission interval is changed by a circuit similar to the above embodiment, that is, for example, the capacitor 107 of the circuit shown in FIG.
By using a circuit in which the constant current circuit 108 and the constant current circuit 108 are reversely connected between the power supply + B and the ground and shortening the light emission interval as the voltage of the main capacitor decreases, the light emission amount per unit time becomes constant. be able to.

Of course, resistors may be used in place of the constant current circuits 108 and 116 in the above embodiment.

Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment, the quick charge capacitor is not used for the on / off control of the main thyristor. Also in this embodiment, as in the first and second embodiments, there are two types of "dynamic flat light emission mode" and "flash light emission mode".
It has a function. First, the configuration of the main circuit 500 shown in FIG. 20 will be described. The main circuit 500 is the same as the main circuit 300 (see FIG. 11) in the second embodiment except that only a part of the elements is changed. Therefore, the same elements as those in FIG. 11 have the same reference numerals. Is attached and the detailed description thereof is omitted. The gate of the SI type thyristor 32 similar to that shown in FIG. 11 is connected to the connection point of the resistors 502 and 503 connected in series.

The output terminal of the OR gate 522 is connected to the ground through the connected resistors 505 and 508, and the connection point of the resistors 505 and 508 is NP.
It is connected to the base of an N-type transistor 507, and the emitter of the transistor 507 is connected to ground. The collector of the transistor 507 is connected to the line l ₂ connected to the positive electrode of the first DC power supply 519 via the resistors 506 and 504 connected in series. Above resistance 50
The connection point between 6 and 504 is connected to the base of the PNP transistor 501, and the emitter of the transistor 501 has the line l ₂
It is connected to the. The collector of the transistor 501 is connected to the resistor 502.

The output terminal of the OR gate 523 is connected in series to the resistor 517.
When connected to the line l ₀ through a 518, the line l ₀ is connected to the negative electrode of the DC power source 519, and further connected to the positive pole of the second DC power supply 521. The connection point between the resistors 517 and 518 is connected to the base of the NPN transistor 516, the emitter of the transistor 516 is connected to the line l ₀ , and the collector is connected in series to the resistors 515 and 514.
Connected to line l ₂ via and. Also, the above resistance
The connection point between 514 and 515 is connected to the base of the PNP type transistor 513, the emitter of the transistor 513 is connected to the line l ₂ , and the collector is connected to the NPN via the resistor 511.
Connected to the base of the transistor 509. The emitter of the transistor 509 is connected to the line l ₃ connected to the negative electrode of the DC power supply 521, and the base of the transistor 509 is connected to the line l ₃ via the resistor 512.
The collector of the transistor 509 is connected to the gate of the main thyristor 32 via the resistor 503.

By skillfully arranging the two DC power supplies 519 and 521 as described above, the gate of the main thyristor 32 is
Either a higher potential or a lower potential than the ground potential, which is a reference unit, is supplied to control the on / off of the thyristor 32.

A control circuit 600 having a circuit configuration as shown in FIG. 21 is connected to the main circuit 500 thus configured. This control circuit 6
00 is the control circuit 40 in the second embodiment (see FIG. 12).
Since the other parts have the same structure only by adding a part of the structure of 0 and a part of the elements, the same elements are denoted by the same reference numerals as those shown in FIG. The description is omitted.

The output terminal of the pulse generating circuit 73 and the input terminal of the OR gate 59 which constitute the light emission interval setting circuit section 601 are connected, and the output terminal of the pulse generating circuit 73 is connected to the first input terminal of the 3-input OR gate 610. Has been done. The output terminal of the pulse generation circuit 85, which is the output terminal of the monitor circuit 402, is connected to the second input terminal of the OR gate 610.
The output terminal of the OR gate 42 for sending the light emission start signal A to the main circuit 500 is connected to the third input terminal of 0. The output end of the OR gate 610 is connected to the input end of the FF circuit 611, and the output end of the circuit 611 derives the light emission start control signal G, which is the first signal of the OR gate 522 of the main circuit 500. It is applied to the input end.

Furthermore, the output end of the pulse generation circuit 73 is connected to one input end of the OR gate 612, and the other input end of the gate 612 is connected to the output end of the pulse generation circuit 85.
Further, the output end of the gate 612 is connected to the input end of the FF circuit 613, and these output ends derive the light emission stop signal H and apply it to the first input end of the OR gate 523 of the main circuit 500. The reset terminal of the FF circuit 613 is connected to the output terminal of the delay circuit 614. The input terminal of the delay circuit 614 is connected to the output terminal of the AND gate 66.

Further, the output end of the inverter 57 is connected to the input end of the pulse generation circuit 617, and the output end of the circuit 617 is connected to the light emission stop signal C ₂
From the OR gate 523 of the main circuit 500.
Is applied to the second input end of the. One input terminal of the OR gate 615 is connected to the output terminal of the pulse generating circuit 617, and the other input terminal is connected to the reset terminal of the pulse generating circuit 617 and the output terminal of the pulse generating circuit 46. . And the above OR gate 61
The output end of 5 is connected to the input end of FF circuit 616,
The output end of the main circuit 50 outputs the light emission start control signal E.
0 is applied to the second input terminal of the OR gate 522.

Next, the operation of the dynamic type flat light emission strobe device of the third embodiment constructed as described above will be explained.

First, the operation of the "dynamic flat emission mode" will be described. In the case of the "flat emission mode",
Since the movable contact terminal of the mode changeover switch 44 is switched to the first fixed contact terminal 44A side, the operating voltage + B is supplied to the input end of the AND gate 40 to open the AND gate 40, and the inverter 43 Since the L level output is supplied to the input terminal of the AND gate 45 via the AND gate 45, the AND gate 45 is closed.

Therefore, the flat emission start signal x _{1 from the} camera body
Is permitted, and the flash light emission start signal x ₂ is not permitted. When the flat light emission start signal x ₁ is input, the output of the pulse generation circuit 41 is output as the light emission start signal A via the OR gate 42 to the main circuit 500.
It is supplied to the gate of the trigger thyristor 10 via the capacitor 13 (see FIG. 20) and the resistor 12, and the thyristor 10
As a result, the trigger current flows from the trigger capacitor 8 to the primary side of the trigger transformer 9. On the other hand, since the signal A sets the FF circuit 611 through the OR gate 610, its H level output is supplied as the light emission start control signal G to the first input terminal of the OR gate 522 of the main circuit 500, and the transistors 507 and 501 are connected. Are sequentially turned on so that the thyristor 32 can be turned on. Then, since the trigger current is flowing through the primary side of the trigger transformer 9 as described above, the discharge tube 14 starts flash discharge, that is, light emission.

Simultaneously with the start of the light emission, an integration operation of the monitor circuit unit 402 is started by the one-shot pulse of H level from the pulse light emitting circuit 41, and the preset counter 64 starts counting. .

Then, as a result of emitting light as described above, the monitor voltage signal M
When the voltage reaches a predetermined level, the output of the operational amplifier 81 is inverted to the L level and transmitted to the pulse generation circuit 85 via the inverter 84 and further input to the OR gate 610 as the output of the H level as in the second embodiment. , And the same gate 6
Since it is transmitted from 10 at the H level to the input terminal of the FF circuit 611, the circuit 611 is reset and outputs the L level signal. Then, the output of the OR gate 522 also becomes L level, while the output of the pulse generating circuit 85 is the OR gate 612.
To the FF circuit 613, and the H level output is input to the FF circuit 613, so that the circuit 613 is set and outputs the H level. Then, the output of the OR gate 523 is set to the H level, so that the transistors 516, 513 and 509 are sequentially turned on and the gate potential of the thyristor 32 is made lower than the ground potential. Then, the thyristor 32 stops conducting, and the light emission from the discharge tube 14 also stops.

On the other hand, the H level output of the pulse generating circuit 41 is the FF circuit.
Since 67 is set and the AND gate 71 is made conductive, an output pulse is applied to the preset counter 72 only when the oscillation circuit 68 outputs H level. The output from the counter 72 is applied to the pulse generating circuit 73. The output pulse of the pulse generation circuit 73 is fed to the FF via the OR gate 610.
Since the signal is input to the circuit 611, the circuit 611 is set and outputs an H level signal. On the other hand, the output of the pulse generation circuit 73 is also applied to the OR gate 612, so that the FF circuit 613 is inverted. Then, the same circuit 613 outputs an L level signal, so the output of the OR gate 523 becomes L level, and the discharge tube 1
4 emits light again in the same manner as described above. By repeating such an operation, the discharge tube 14 continuously emits light and stops.

After that, when the preset counter 64, which has started counting as described above, completes counting the number of counts corresponding to the total light emission time, the output of the FF circuit 65 becomes H level,
Since the AND gate 66 is opened, the output pulse of the pulse generation circuit 85 is output to RESET via the AND gate 66, and the output of the delay circuit 614 whose delay time is set to be equal to or longer than the deionization time of the discharge tube 14 is output. It is input to the reset terminal of the FF circuit 613 and resets the circuit 613. That is, the discharge tube 14
During the deionization time, the thyristor 32 is kept in the off state to prevent the discharge tube 14 from emitting light again. Further, the FF circuit 62, the preset counter 64, and the FF circuit 65 are reset by the reset signal, and all the other circuits are reset to complete a series of dynamic flat light emission operations.

Next, in the "flash emission mode", the movable contact terminal of the mode changeover switch 44 is set to the second contact point, as in the first embodiment.
The fixed terminal 44B of is switched to alligator. At this time, the H level output of the pulse generation circuit 46 is output to the F level via the OR gate 615.
The F circuit 616 is set and an H level signal is output. Then, this is the OR gate 522 (second
(Refer to FIG. 0), and causes the discharge tube 14 to emit light, and is input to the reset terminal of the pulse generation circuit 617 to reset the circuit 617. Then, after the proper exposure, the output of the operational amplifier 56 is inverted and becomes L level. Further, this becomes H level by the inverter 57 and is supplied from the pulse generation circuit 617 to the OR gate 615 as a pulse signal of H level. Output level signal. Further, at the time of proper exposure, the output of H level is applied to the OR gate 523 as the light emission stop signal C ₂ , so the transistors 516, 513, 509 are sequentially turned on, the gate of the thyristor 32 is reverse biased, and the thyristor 32 is turned off to turn off the discharge tube. Stops the light emission of 14. If the resistance value of the resistor 503 is made too large, the turn-off time of the thyristor 32 becomes long, so an appropriate resistance value must be selected. The pulse width of the pulse generation circuit 617 needs to be longer than the deionization time of the discharge tube 14. Further, even while the output signal of the pulse generating circuit 46 is being applied to the reset terminal of the pulse generating circuit 617 and the output signal is being generated from the generating circuit 617, the pulse generating circuit 46
The pulse generation circuit 617 is reset by the output signal from the. With this configuration, when the pulse width of the light emission stop signal C ₂ output from the pulse generation circuit 617 is set to be sufficiently longer than the deionization time of the discharge tube 14, the motor drive device is used. When high-speed shooting is performed, the light emission start control signal F is input to the OR gate 522 before the stop signal C ₂ of the generation circuit 617 changes from H level to L level, and the signal F and the light emission stop signal C ₂ are input. Both signals will be input to the control unit of the thyristor 32 of the main circuit 500 at the same time. Since it is not preferable to input signals having mutually opposite properties to the control unit at the same time, the light emission stop signal
This is to make C ₂ consciously short and prevent the control unit from being reverse-biased and stopping the light emission.

In this way, the main thyristor 32 can be controlled to be turned on and off without using the rapid charging capacitor, and the discharge tube can be turned on and off at a minute interval time.

In addition, also in this embodiment, a part thereof is shown in FIG. 16 and FIG.
Of course, the circuit shown in FIG. 18 can be changed.

(Effect of the Invention) As described above, according to the present invention, since the change in the light intensity of the flash discharge tube is detected by replacing it with the change in the voltage of the main capacitor, there is an advantage that it is not adversely affected by the high-voltage light emission trigger signal. .

In addition, since the flash discharge tube is not turned on / off between the upper and lower limits, which is extremely small like the conventional static flat flash device, the circuit configuration is simplified and the accuracy is extremely high. Since it is not necessary to use the voltage comparison circuit of, there is also an advantage that the cost is low.

Therefore, it is possible to provide a dynamic flat flash device which is extremely convenient in use and which solves the conventional drawbacks described at the beginning of the specification.

[Brief description of drawings]

FIG. 1 is a diagram showing a light emission intensity characteristic by a conventional strobe device and a light emission intensity characteristic by a dynamic flat light emission strobe device of the present invention, and FIG. 2 is a light emission interval in a dynamic flat light emission strobe device of the present invention. FIG. 3 is a diagram showing a relationship with the slit width of the focal plane shutter, FIG. 3 is a diagram showing exposure unevenness in the focal plane shutter when the dynamic flat flash device of the present invention is used, and FIG. FIG. 6 is an electric circuit diagram showing a main circuit of the dynamic type flat light emitting strobe device of the first embodiment of the invention, FIG. 5 is an electric circuit diagram showing a control circuit connected to the main circuit shown in FIG. 4, and FIG. Is the "flat light emission" in the dynamic flat light emission strobe device according to the first embodiment of the present invention shown in FIGS. Waveform diagram for explaining the operation of the monitor circuit, FIG. 7 is a diagram for explaining the operation of the monitor circuit shown in FIG. 5, and FIG. 8 is the first embodiment. 9 is a flow chart showing the operation in the "flat light emission mode" in the flash device of FIG. 9, FIG. 9 is a signal waveform diagram for explaining the operation in the "flash light emission mode" in the flash device of the first embodiment, and FIG. FIG. 11 is a flow chart showing the operation of the “flash light emission mode” in the strobe device of the first embodiment. FIG. 11 is an electric circuit diagram showing the main circuit of the dynamic flat light emission strobe device of the second embodiment of the present invention. FIG. 12 is an electric circuit diagram showing a control circuit connected to the main circuit shown in FIG. 11, and FIG. 13 is a dynamic flat type of the second embodiment of the present invention shown in FIGS. 11 and 12. In flash strobe device FIG. 14 is a signal waveform diagram for explaining the operation in the “flat light emission mode” according to the present invention. FIG. 14 is a flowchart showing the operation in the “flat light emission mode” in the strobe device according to the second embodiment. FIG. 16 is a flow chart showing the operation of the “flash light emission mode” in the flash device of the embodiment, FIG. 16 is an electric circuit diagram showing another example of the light emission interval setting circuit section in the control circuit shown in FIG. 5 or FIG. 17 (A) and (B) are signal waveform diagrams for explaining the operation of the light emission interval setting circuit section shown in FIG. 16, and FIG. 18 is a light emission interval in the control circuit shown in FIG. An electric circuit diagram showing still another example of the setting circuit section, FIGS. 19 (A) and (B) are signal waveform diagrams for explaining the operation of the light emission interval setting circuit section shown in FIG. 18, and FIG. The figure shows the dynamic flat of the third embodiment of the present invention. Circuit diagram showing a main circuit of a light flash device, FIG. 21 is a circuit diagram showing a control circuit connected to the main circuit according to the Figure 20. 3 …… Main capacitor 14 …… Flash discharge tube 16 …… Commutation capacitor 18 …… Thyristor (switching element for rapid charging) 22 …… Commutation thyristor (switching element for commutation) 27,32 …… Main thyristor ( Main switching element) 100,300 …… Main circuit 200,400 …… Control circuit 201,201 ′, 401 …… Light emission interval setting circuit section 202,402 …… Monitor circuit section

Claims (1)

[Claims] 1. A series circuit means of a flash discharge tube and a semiconductor switching element inserted in a discharge loop of a main capacitor, a trigger circuit means for starting light emission of the flash discharge tube by a signal from a camera, Monitor means for detecting the ever-changing voltage of the main capacitor, and operation that starts in connection with light emission, and generates a light emission stop signal when the output of the constantly changing monitor means reaches a predetermined level. A light emission stop control means for turning off the conduction of the semiconductor switching element in response to a light emission stop signal and stopping the light emission of the flash discharge tube, and an operation associated with light emission is started, and after the light emission of the flash discharge tube is stopped. A light emission resuming control means for generating a light emission resuming signal until the deionization time of the flash discharge tube and restarting the light emission of the flash discharge tube by the light emission resuming signal, The light emission stop signal and the light emission restart signal are repeatedly generated while the focal plane shutter of the camera is running, and the pulsed small light emission is repeated to obtain a substantially flat light emission characteristic. Strobe device characterized by.