JPS60225434A - Formation of multi-element composite oxide film with high dielectric constant - Google Patents

Formation of multi-element composite oxide film with high dielectric constant

Info

Publication number
JPS60225434A
JPS60225434A JP59081362A JP8136284A JPS60225434A JP S60225434 A JPS60225434 A JP S60225434A JP 59081362 A JP59081362 A JP 59081362A JP 8136284 A JP8136284 A JP 8136284A JP S60225434 A JPS60225434 A JP S60225434A
Authority
JP
Japan
Prior art keywords
dielectric constant
high dielectric
film
substrate
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59081362A
Other languages
Japanese (ja)
Inventor
Toshiyuki Shimizu
俊行 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59081362A priority Critical patent/JPS60225434A/en
Publication of JPS60225434A publication Critical patent/JPS60225434A/en
Pending legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/482Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using incoherent light, UV to IR, e.g. lamps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Abstract

PURPOSE:To form an insulation film with a high dielectric constant, excellent in insulation, which can be applied for the capacitor of a high-quality cell part, on a semiconductor substrate by a method wherein thermal decomposition is carried out by adding a compound gas made mainly of an organic or inorganic compound of the main constituent of dielectric and containing another element, under irradiation with ultraviolet rays. CONSTITUTION:A film producer is composed of an ultraviolet ray source 101, a quartz tube 102, infrared ray heaters 103, raw material source bubblers 104 and 105, and ray material gas heaters 106 and 107. Light of 184.9nm wavelength emitted from a low-pressure mercury vapor lamp 101 is condensed by a reflection mirror 108, and the surface of a semiconductor condensed by a reflection mirror 108, and the surface of a semiconductor substrate 109 is irradiated with the light through the quartz tube 102. The substrate and the reaction gas are heated by the infrared ray heater 103 and a reflection mirror 110, thus carrying out vapor phase decomposition with photo energy and thermal energy; accordingly, a high-quality oxide can be deposited on the substrate.

Description

【発明の詳細な説明】 (技術分野) 本発明は高誘電率多元複合酸化膜の形成法に関し、特に
、紫外線照射を併う高誘電率多元複合酸化膜の形成方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a method for forming a high dielectric constant multi-component oxide film, and more particularly to a method for forming a high dielectric constant multi-component oxide film that includes ultraviolet irradiation.

(従来技術) 半導体基板、特にシリコン半導体基板上に形成される集
積回路は高集積化、大容量化の一途を辿シ、メモリ素子
の様な集積回路では1Mビット又はそれ以上へと増大し
てきている。この様な素子の大容量イしに於いては歩留
シやコストの点でチップサイズは極力小さくすることが
必要であシ、そのために種々の微細加工技術が開発され
ている。
(Prior Art) Integrated circuits formed on semiconductor substrates, particularly silicon semiconductor substrates, are becoming increasingly highly integrated and have a large capacity, and integrated circuits such as memory devices have increased to 1M bits or more. There is. In producing large-capacity devices, it is necessary to reduce the chip size as much as possible from the viewpoint of yield and cost, and various microfabrication techniques have been developed for this purpose.

現在ダイナミックRAMの様なICメモリーに於いては
情報蓄積部(以下セルと記す)を1個のトランジスタと
1個の情報蓄積容量部で構成するのが最も小形化に適し
たものと考えられるが、該方法での情報蓄積方式では半
導体ペレットの大部分を占めるのは前記セルの情報蓄積
容量部面積である。従って該方式によるダイナミックR
AMの大容量化に依るチップサイズの増大を抑えるため
には情報蓄積容量部面積の縮小が最も有効な手段となる
Currently, in IC memories such as dynamic RAM, it is considered most suitable for miniaturization that the information storage section (hereinafter referred to as cell) is composed of one transistor and one information storage capacitor section. In the information storage method in this method, the area of the information storage capacitor portion of the cell occupies most of the semiconductor pellet. Therefore, the dynamic R according to this method
In order to suppress the increase in chip size due to the increase in the capacity of AM, the most effective means is to reduce the area of the information storage capacitor.

しかしこの情報蓄積容量部面積を縮小することは誘電体
の誘電率が小さく、膜厚が一定の場合、容量値を減少さ
せることになシ、この容量部に蓄積される情報信号量を
減少させる。この情報信号量の減少は放射線によるメモ
リー内容の消失(ソフトエラー)効果等を防止する点か
ら好ましくない。このために単位千面積当シの容量値を
増加すべく膜厚の減少や容量部の積層化、誘電率の高い
材料が検討されているが、膜厚の減少はシリコン酸化膜
を用いた場合1Mピッ)DRAMでは耐圧等の点から絶
縁性はその限界に達し、1M以上の高集積メモリーでは
用いることが出来なくなる。積層型構造で容量部を形成
する際、2層目以上の絶縁膜は多結晶物質の熱酸化に依
らねばならないため、膜の絶縁性に問題が残る。又、誘
電体に高誘電材料を用いることは膜厚を厚くすることが
出来るため、有利であるが、しかし膜の形成法によシ絶
縁膜としての性質が大きく変わってしまうため種々の形
成法が検討されてい今が末だ有効な方法は見付かってい
ない。
However, reducing the area of this information storage capacitor will not reduce the capacitance value if the dielectric constant of the dielectric is small and the film thickness is constant, but will reduce the amount of information signal stored in this capacitor. . This reduction in the amount of information signal is undesirable from the viewpoint of preventing the effect of erasure of memory contents (soft error) due to radiation. For this reason, in order to increase the capacitance value per unit of 1,000 areas, reduction of film thickness, lamination of capacitance parts, and materials with high dielectric constant are being considered. In DRAMs (1M bits), insulation reaches its limit in terms of withstand voltage, etc., and it can no longer be used in highly integrated memories of 1M or more. When forming a capacitive part in a stacked structure, the second and higher insulating films must rely on thermal oxidation of polycrystalline materials, which leaves problems with the insulation properties of the films. In addition, using a high dielectric material for the dielectric is advantageous because the film thickness can be increased, but the properties of the insulating film vary greatly depending on the film formation method, so various formation methods are required. has been considered, but no effective method has been found.

(発明の目的) 本発明の目的は上述の如き問題点を解決し集積回路の大
容量化、更にはチップサイズの縮小が容易となる様な、
高誘電率多元複合酸化膜の形成法を提供するにある。
(Objective of the Invention) The object of the present invention is to solve the above-mentioned problems and to facilitate the increase in the capacity of integrated circuits and the reduction in chip size.
The present invention provides a method for forming a high dielectric constant multi-component oxide film.

(発明の構成) 本発明の高誘電率多元複合酸化膜の形成法は、石英中空
円筒管内部に膜形成用基板を配置し、高誘電率薄膜原料
となる複数のガスを前記石英中空円筒管内に導入し、前
記石英中空円筒管の外部に置かれた加熱ヒーター及び紫
外光によシ前起原料ガスを分解せしめ、前記膜形成基板
の一主面上に高誘電率多元複合酸化膜を気相成長させる
ことによシ構成される。
(Structure of the Invention) The method for forming a high dielectric constant multi-component oxide film of the present invention includes arranging a film forming substrate inside a quartz hollow cylindrical tube, and injecting a plurality of gases, which are raw materials for a high dielectric constant thin film, into the quartz hollow cylindrical tube. The precursor gas is decomposed using a heating heater placed outside the quartz hollow cylindrical tube and ultraviolet light, and a high dielectric constant multi-component oxide film is formed on one main surface of the film forming substrate. It is constructed by phase growth.

−(発明の原理と作用) 本発明によれば、紫外光を照射しながら、誘電体の主成
分となる元素を有する有機又は無機化合物を主原料とし
、これに他の元素を含む化合物ガスを加え熱分解を行な
わしめることによシ、半導体基板上に、誘電率が高く、
絶縁性に優れた、高品質のセル部の容量部に適用できる
絶縁膜が形成される。
- (Principle and operation of the invention) According to the present invention, while irradiating ultraviolet light, a compound gas containing an organic or inorganic compound containing an element that is the main component of a dielectric material is used as a main raw material, and a compound gas containing other elements is added to the main raw material. In addition, by performing thermal decomposition, a high dielectric constant,
An insulating film with excellent insulation properties and high quality that can be applied to the capacitive part of the cell part is formed.

本発明によれば誘電膜の成分となる原料ガスの気相分解
が起ζるため、ガスの種類や分圧を変化させることによ
り所望の膜の組成が得られ、しかもその組成が膜中で均
一である固溶複合酸化物が容易に形成可能となる。異な
る物理的化学的性質を有する材料の組み合わせと、組成
の均一な固溶体形成のため、それらの物理的化学的性質
を兼ね備えた膜が形成可能となシ、単体の酸化物では達
成されなかった電気的、物理的、化学的限界を補うこと
が可能となる。
According to the present invention, since vapor phase decomposition of the raw material gas that is a component of the dielectric film occurs, a desired film composition can be obtained by changing the type and partial pressure of the gas. A uniform solid solution composite oxide can be easily formed. By combining materials with different physical and chemical properties and forming a solid solution with a uniform composition, it is possible to form a film that combines these physical and chemical properties. It becomes possible to compensate for physical, physical, and chemical limitations.

又、気相生長の際の紫外線照射のために気相生長温度を
下げることが出来るため、高温処理で組成が変わってし
まう化合物半導体基板等の上の誘電膜形成に有効である
。又、金属の熱酸化等では酸化物になる際に体積膨張等
が起こり、膜にり2ツクが入ってリーク電流が流れる原
因となりているが、紫外線照射の化学気相生長を行なう
ことによシ低温分解によって細粒が堆積するために、こ
の様な体積膨張は生じず、又誘電率示大きい材料と粒成
長の少ない材料を組み合わせることにより熱アニールに
よるクラックの発生を抑えることが可能となシ、リーク
電流の少ない誘電膜が形成可能となる。
Furthermore, since the vapor phase growth temperature can be lowered due to ultraviolet irradiation during vapor phase growth, it is effective for forming a dielectric film on a compound semiconductor substrate or the like whose composition changes due to high temperature treatment. In addition, in thermal oxidation of metals, volume expansion occurs when they turn into oxides, which causes a leakage current to flow in the film, but chemical vapor growth using ultraviolet irradiation can Since fine grains are deposited by low-temperature decomposition, such volume expansion does not occur, and by combining a material with a high dielectric constant and a material with low grain growth, it is possible to suppress the occurrence of cracks due to thermal annealing. Furthermore, a dielectric film with low leakage current can be formed.

(実施例) 以下、本発明の実施例について、図面を参照して説明す
る。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図、第2図は本実施例に用いた光励起高誘電率薄膜
形成装置の説明用の模式断面線並びに赤外、紫外光源部
の説明図である。なお本実施例ではクリコノ基板上のT
a−8j−0系の誘電膜の形成について説明する。
FIGS. 1 and 2 are schematic cross-sectional lines and explanatory diagrams of infrared and ultraviolet light sources of the optically excited high dielectric constant thin film forming apparatus used in this example. Note that in this example, T
Formation of an a-8j-0 type dielectric film will be described.

第1図及び第2図に示すように、紫外光源101と石英
管102、赤外線ヒーター103、及び原料ガス源バブ
ラー104,105、ここでは原料気体としてT a 
(OCtHi ) *を原料ガス源バブラー104 K
、 8i (QC,H,)、を原料カスバブラー105
に入れた。その他原料ガス加熱器106,107から構
成されている。
As shown in FIGS. 1 and 2, an ultraviolet light source 101, a quartz tube 102, an infrared heater 103, and raw material gas source bubblers 104, 105, here, T a as a raw material gas.
(OCtHi) * as source gas source bubbler 104 K
, 8i (QC,H,), as the raw material gas bubbler 105
I put it in. It also includes raw material gas heaters 106 and 107.

また本装置においては低圧水銀2ンプ101から発光さ
れる波長184.91tNの光が反射鏡108によシ集
光され、石英管102を通して半導体装置109表面に
照射されるようにする。又赤外線加熱ヒーター103及
び反射鏡110によシ基板及び反応ガスを加熱し光エネ
ルギーと熱エネルギーにより気相分解を行うことができ
、これにより酸−化物を基板に堆積することができる。
Further, in this apparatus, light with a wavelength of 184.91 tN emitted from the low-pressure mercury pump 101 is focused by the reflecting mirror 108 and irradiated onto the surface of the semiconductor device 109 through the quartz tube 102. Further, the substrate and the reaction gas are heated by the infrared heater 103 and the reflecting mirror 110, and gas phase decomposition can be performed using optical energy and thermal energy, thereby allowing oxides to be deposited on the substrate.

ガス源は液体であるため原料ガス源バブシー104.1
05にてArfキャリアガスにして加熱器106,10
7にて加熱され気化する。キャリアガスは不活性ガスな
らば何でも艮い。Ta(OqHa)aは蒸気圧が低いた
め、(146℃で0.15朋Hg)加熱器106は16
0℃〜290℃に温度設定し、流量はパルプ111によ
って調節する。8i(OQI−L)4は常圧167℃で
沸騰するために加熱器107の加熱は20℃〜60℃で
良い。S i (OCJL、)+の流量はパルプ112
によって調節する。反応管までは気体が凝縮しない様に
リボンヒーター113で暖めておく。
Since the gas source is liquid, the raw material gas source Babsy 104.1
At step 05, the heaters 106 and 10 are converted to Arf carrier gas.
It is heated and vaporized at step 7. The carrier gas can be any inert gas. Since Ta(OqHa)a has a low vapor pressure (0.15 Hg at 146°C), the heater 106
The temperature is set at 0°C to 290°C, and the flow rate is adjusted by the pulp 111. Since 8i(OQI-L)4 boils at normal pressure of 167°C, heating by the heater 107 may be from 20°C to 60°C. The flow rate of S i (OCJL,)+ is pulp 112
Adjust by. The reaction tube is heated with a ribbon heater 113 to prevent gas from condensing.

この系ではTa(OC*Hs)sの蒸気圧が低いので、
0、1 Torr〜1’l1orrの減圧で気相生長さ
せる。ガス導入口114からかガスを導入し、反応管の
圧力を調節出来る様にする。反応管内は300℃〜50
0℃にて気相生長させることが出来る。反応後のガスは
排気口115から排気される。又本実施例の’l’a−
8i系複合酸化膜の形成によりSi元素のTa酸化物へ
の固溶によjD、600℃付近で起こるTa酸化物の粒
成長が抑制されるため、600℃〜700℃の高温アニ
ールによりリーク電流が少ない膜が形成できた。
In this system, the vapor pressure of Ta(OC*Hs)s is low, so
Gas phase growth is performed under reduced pressure of 0.1 Torr to 1'l1orr. Gas is introduced through the gas inlet 114 so that the pressure in the reaction tube can be adjusted. The temperature inside the reaction tube is 300°C to 50°C.
It can be grown in the vapor phase at 0°C. The gas after the reaction is exhausted from the exhaust port 115. Also, the 'l'a-
The formation of an 8i-based composite oxide film suppresses the grain growth of Ta oxide that occurs near jD and 600°C due to the solid solution of Si element into Ta oxide, so the leakage current is reduced by high-temperature annealing at 600°C to 700°C. A film with a small amount of oxidation was formed.

この他に、Nb (0鶴H6)、やHf (OらH,)
、等信の原料ガスを導入することも可能である。
In addition, Nb (0 Tsuru H6), Hf (O et H,)
It is also possible to introduce raw material gas such as , etc.

加熱方式として赤外線ヒーターのみでなく熱炉による加
熱も可能である。
As a heating method, not only an infrared heater but also a thermal furnace can be used.

なお、本実施例では基板としてシリコン基板を用いたが
シリコン基板に限定されるものでなく。
Note that although a silicon substrate is used as the substrate in this embodiment, it is not limited to a silicon substrate.

他の半導体基板でも、またセラミック基板等の絶縁基板
上でも同様に誘電膜を形成することができる。
Dielectric films can be similarly formed on other semiconductor substrates or on insulating substrates such as ceramic substrates.

(発明の効果) 以上説明し九とおシ、本発明によれば、高誘電率多元複
合酸化膜を得ることができ、この膜は単体の酸化膜の物
理的化学的限界をこえた誘電膜であシ、これを集積回路
に応用すれば集積回路の大容量化、更にはチップサイズ
の縮小が容易となるという効果がある。
(Effects of the Invention) As explained above, according to the present invention, a high dielectric constant multi-component oxide film can be obtained, and this film is a dielectric film that exceeds the physical and chemical limits of a single oxide film. Also, if this is applied to integrated circuits, it will be possible to increase the capacity of the integrated circuit and further reduce the chip size.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図は本発明の実施例に用いた光励起高誘電
率薄膜形成装置の説明用の模式断面図並びに赤外、紫外
光源部の説明図でちる。 101・・・・・・紫外光源(低圧水銀ランプ)、10
2・・・・・・反応石英fα、103・・・・・・赤外
線ヒーター、104.105・・・・・・原料ガス源バ
ブラー、106゜107・・・・・・原料ガス加熱器、
108・旧・・反射鏡、109・・・・・・半導体基板
、110・・・・・・反射鏡、111゜112・・・・
・・流# 調16 パルプ、113・・・・・・リボン
ヒーター、114・・・・・・ガス導入口、、115・
・・・・・排気口。 yF)2閃″′y
FIGS. 1 and 2 are schematic cross-sectional views for explaining the optically excited high dielectric constant thin film forming apparatus used in the examples of the present invention, as well as explanatory views of the infrared and ultraviolet light sources. 101... Ultraviolet light source (low pressure mercury lamp), 10
2...Reactive quartz fα, 103...Infrared heater, 104.105... Raw material gas source bubbler, 106°107... Raw material gas heater,
108・Old...Reflector, 109...Semiconductor substrate, 110...Reflector, 111゜112...
...Flow #16 Pulp, 113... Ribbon heater, 114... Gas inlet, 115.
·····exhaust port. yF) 2 flash"'y

Claims (1)

【特許請求の範囲】 石英中空円筒管内部に膜形成用基板を配置し。 高誘電率薄膜原料となる複数のガスを前記石英中空円筒
管内に導入し、前記石英中空円筒管の外部に置かれた加
熱ヒーター及び紫外光により前記原料ガスを分解せしめ
、前記膜形成基板の一生面上に高誘電率多元複合酸化膜
を気相成長させることを特徴とする高誘電率多元複合酸
化膜の形成方法。
[Claims] A film forming substrate is placed inside a quartz hollow cylindrical tube. A plurality of gases serving as raw materials for a high dielectric constant thin film are introduced into the quartz hollow cylindrical tube, and the raw material gases are decomposed by a heating heater placed outside the quartz hollow cylindrical tube and ultraviolet light, and the film forming substrate is decomposed over a lifetime. A method for forming a high dielectric constant multi-component oxide film, the method comprising growing a high dielectric constant multi-composite oxide film on a surface in a vapor phase.
JP59081362A 1984-04-23 1984-04-23 Formation of multi-element composite oxide film with high dielectric constant Pending JPS60225434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59081362A JPS60225434A (en) 1984-04-23 1984-04-23 Formation of multi-element composite oxide film with high dielectric constant

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59081362A JPS60225434A (en) 1984-04-23 1984-04-23 Formation of multi-element composite oxide film with high dielectric constant

Publications (1)

Publication Number Publication Date
JPS60225434A true JPS60225434A (en) 1985-11-09

Family

ID=13744219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59081362A Pending JPS60225434A (en) 1984-04-23 1984-04-23 Formation of multi-element composite oxide film with high dielectric constant

Country Status (1)

Country Link
JP (1) JPS60225434A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62134937A (en) * 1985-12-06 1987-06-18 Nec Corp Forming method for electric insulator film
JPS6450428A (en) * 1987-08-20 1989-02-27 Tokyo Noukou Univ Oxide thin film having high permittivity and formation thereof
US5112647A (en) * 1986-11-27 1992-05-12 Canon Kabushiki Kaisha Apparatus for the preparation of a functional deposited film by means of photochemical vapor deposition process
JPH0732150B2 (en) * 1989-11-13 1995-04-10 フラウンホファー―ゲゼルシャフト ツアフェルデルング デア アンゲバンテン フォルシュング アインゲトラゲナー フェライン Method for manufacturing silicate layer of integrated circuit
EP1837904A2 (en) * 2003-03-26 2007-09-26 Osaka Prefecture Method for manufacturing buried insulating layer type single crystal silicon carbide substrate and corresponding manufacturing device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62134937A (en) * 1985-12-06 1987-06-18 Nec Corp Forming method for electric insulator film
US5112647A (en) * 1986-11-27 1992-05-12 Canon Kabushiki Kaisha Apparatus for the preparation of a functional deposited film by means of photochemical vapor deposition process
JPS6450428A (en) * 1987-08-20 1989-02-27 Tokyo Noukou Univ Oxide thin film having high permittivity and formation thereof
JPH0732150B2 (en) * 1989-11-13 1995-04-10 フラウンホファー―ゲゼルシャフト ツアフェルデルング デア アンゲバンテン フォルシュング アインゲトラゲナー フェライン Method for manufacturing silicate layer of integrated circuit
EP1837904A2 (en) * 2003-03-26 2007-09-26 Osaka Prefecture Method for manufacturing buried insulating layer type single crystal silicon carbide substrate and corresponding manufacturing device
EP1837904A3 (en) * 2003-03-26 2007-12-26 Osaka Prefecture Method for manufacturing buried insulating layer type single crystal silicon carbide substrate and corresponding manufacturing device

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