JPS60225254A - Computer of two-phase sequence system - Google Patents

Abstract

PURPOSE:To secure the reliability in a degree equivalent to that of a full duplex system by realizing instruction comparing and deciding functions with addition of a simple circuit. CONSTITUTION:In a pseudo fetch cycle, contents of a program memory designated through an address bus 21 by the value of a pseudo program counter 12 are fetched in a pseudo instruction register 14 by a bus switch 19. In an effective fetch cycle, contents of the program memory designated through the address bus 21 by the value of an effective program counter 13 are fetched in an effective instruction register 16. Contents of pseudo instruction registers 14 and 15 are compared with each other, and a normal execution cycle is performed if they coincide with each other. If they do not coincide with each other, the value of the pseudo program counter 12 is transferred to the effective program counter 13, and the value of a pseudo program counter 11 is transferred to the counter 12, and thereafter, an operation similar to that of a jump instruction is performed.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to a two-phase sequence computer.

In particular, it relates to techniques for improving reliability in this type of basic computer system.

[Prior art]

Duplication is used as a method to ensure reliability in computer systems. If duplication is not economically advisable, a method is used, for example, to define a memory range to be accessed and prohibit access to other memories. In all of these, the computer control section remains the same as before.

FIG. 4 shows parts of a conventional computer control unit that are related to the present invention. 41 is a switch for switching between the output of the program counter 42 and the address bus 45 output during the effective cycle, and 46 is its output -1'6. 43 is an instruction register, which is connected to data bus 4 when fetching instructions.
The value of 7 is read. 40 is a control section.

However, it is not economically advisable to use full redundancy in such computers; on the other hand, it only provides partial protection and cannot be completely guaranteed.

[Purpose of the invention]

An object of the present invention is to provide a two-phase sequential computer which can easily guarantee reliability equivalent to complete duplexing using a method as simple as possible.

[Structure of the invention]

The present invention includes a first pseudo program counter that holds a program address two steps before.

A second pseudo program counter that holds the program address of one step before, an effective program counter that holds the program address that is actually executed, and a temporary instruction that is read from the address addressed by the second pseudo program counter. A first pseudo-instruction register that holds a comparison instruction, and a second pseudo-instruction register that holds a comparison instruction.

an effective instruction register that temporarily holds instructions to be actually executed, a comparator that compares the contents of the first and second pseudo-instruction registers, a control unit that controls these, and the second pseudo-program counter. A switch for switching the output of an effective program counter is added to a conventional computer basic control section.

〔Example〕

The present invention will be described in detail below with reference to FIGS. 1 to 3.

FIG. 1 shows, in block diagram form, one embodiment of the invention. For convenience, the instruction cycle is shown in FIG. FIG. 6 shows the instruction execution flow.

In FIG. 1, 11 is a first pseudo program counter that holds the program address of two steps before;
12 is a second pseudo program counter that holds the program address of one step before.

Reference numeral 13 denotes an effective program counter that holds the address of the program actually executed. The bus switch 19 is the second
The outputs of the pseudo program counter 12 and the effective program counter 13 are switched. 14 is a first pseudo-instruction register that temporarily holds instructions sent through the data bus 22, 15 is a second pseudo-instruction register that temporarily holds instructions for comparison, and 16 temporarily holds instructions that are actually executed. The effective instruction register 17 is a comparator. 18 is a control section for each section.

In a pseudo fetch cycle, the pseudo program counter 1 is transferred to the bus switch 19.
The contents of the program memory specified by the address bus 21 by the value of 2 are read through the data bus 22 and fetched into the pseudo-instruction register 14.

The clock pulse B is supplied from the control unit 18 as a clock pulse for that purpose. In the actual fetch cycle, the contents of the program memory specified by the address bus 21 according to the value of the effective program counter 13 are fetched into the effective instruction register 16 via the data bus n. In the check cycle, the comparator 17 compares the pseudo-instruction registers 14 and 15, and if there is a match (the pseudo-instruction register 14 contains the correctly executed instruction value of the previous step), the pseudo-instruction register 15 (However, the value in register 15 was read during the instruction cycle of the previous step, and the value in register 14 was read during the current instruction cycle.) For example, a normal execution cycle is performed and the following operations are performed. That is, the value of the effective instruction register 16 is transferred to the register 15 (
This is for comparison in the next cycle. ), the value of the pseudo program counter 12 is transferred to the pseudo program counter 11, and the value of the effective program counter 13 is further transferred to the pseudo program counter 12.

On the other hand, if they do not match (a mismatch indicates that the instruction value fetched in the previous step is not correct).
After transferring the value of the pseudo program counter 12 to the effective program counter 13 and transferring the value of the pseudo program counter 11 to the pseudo program counter 12, a jump instruction (
The jump destination address is given by the effective program counter 13. ) is performed.

〔Effect of the invention〕

As is clear from the above description, in the present invention, an extremely reliable computer can be easily realized by adding a simple circuit to provide an instruction comparison/judgment function.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of an embodiment of the present invention. FIG. 2 is a diagram showing an instruction cycle. FIG. 3 shows an execution flow in an instruction cycle, and FIG. 4 is a block diagram of a part of a conventional computer control unit. In the figure, 11.12... pseudo program counter, 13... effective program counter. 14, 15... pseudo-instruction register, 16... effective instruction register. 17... Comparator, 18... Control unit, 19... Bus switching device. Agent (7127) Patent Attorney Yosuke Gome Figure 1

Claims (1)

[Claims] 1. The first one that holds the program address from two steps ago.
a second pseudo program counter that holds the program address of the previous step; an effective program counter that holds the address of the program actually executed; and an address addressed by the second pseudo program counter. a first pseudo-instruction register that temporarily holds an instruction read from the first pseudo-instruction register, a second pseudo-instruction register that holds an instruction for comparison, an effective instruction register that temporarily holds an instruction that is actually executed; and a comparator 7 that compares the instructions held in the second pseudo-instruction register.
A two-phase sequence computer comprising: a control section 8 for each of the elements; and a switch 9 for switching between the outputs of the second pseudo program counter and the effective program counter.