JPS60225086A - Electronic timepiece for chess game - Google Patents

Abstract

PURPOSE:To make the apparatus lightweight and compact by providing a CPU to alternately perform the function of two timers for counting the time consumption of two players respectively. CONSTITUTION:Switches 12N and 12S are operated sequentially to set the play time of players L and R. Here, when the player R is the first move, upon the pressing of a switch 12L by the player L, the timer of the player R is operated to show the progress on a display panel 11R. Moreover when the player R presses the switch 12R, the display of the display panel 11R stops while the display of the switch 12L changes. Thereafter, the operation is repeated. When the timer of either player reaches the initialized time, the player is informed of the end of play employing a built in piezo-electric buzzer, a voice synthesization LSI or the like. After the time, pressing the switch 12S will permit reuse without setting time, while pressing the switch 12C permit the setting of the play time. Such an operation program is stored into a ROM45 and a CPU41 operates according to the program.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic watch used in various games and competitions with time constraints, such as chess.

In recent years, intellectual board games that deal with fictional wars and history have developed, and games such as Go and Shogi require specialized clocks, but conventional mechanical chess clocks are lightweight and compact. There are restrictions on what can be done, and it is difficult to provide many functions.

The present invention has been made to solve the above-mentioned drawbacks, and the features of the present invention will become more apparent from the following detailed description with reference to the drawings.

FIG. 1 is a perspective view showing an embodiment of the present invention. Second
This figure is a rear view of the electronic chess watch shown in FIG. 1. The main body 10 includes a liquid crystal display panel 11, a switch 12L operated by the contestant R, a switch 12R operated by the contestant R, a mode changeover switch 12M1, a switch for initially setting the running time, and a switch for setting the running time after the end of 12N1. Switch 12S that can be reused without resetting
A switch 12C is provided which returns the state to the one for setting the time limit after one end. Note that a battery is housed inside the main body 10 to supply necessary power.

FIG. 6 is a diagram showing an example of the liquid crystal display panel 11 shown in FIG. 1. In the figure, the "1 day" character is formed of a transparent electrode so as to be displayed when a driving voltage is applied, and the other parts are fixed background images drawn by printing or the like.

Here, the method of using this watch will be explained with reference to FIGS. 1 to 6. First, mode selector switch 12
Select the mode with M. This mode selector switch 1
2M may be a multi-stage slide type and also serve as a power 0N10FF switch.

Next, the switches 12N and 123 are operated in order to set the time allowed for contestants R and R. If it is player R's turn to go first, when player R presses switch 12L, player R's timer will start and the progress will be displayed on the display panel.
Displayed on 1H.

Furthermore, when the contestant R presses the switch 12R, the display of 11R on the display panel stops, and the number of hands on 12L changes. Thereafter, this operation is repeated, and when the timer of one of the contestants reaches the initially set time, the built-in piezoelectric buzzer or voice synthesis LSI or the like is used to notify the contestant of the end. Thereafter, if the switch 12S is pressed, the battery can be reused without resetting the expiration time, or if the switch 12C is pressed, the battery life can be set. 1
FIG. 4 shows a block diagram of this embodiment. In this configuration, the CPU 41 (for example, Z80 manufactured by Zilog) is supplied with the reference operating clock φ from the black/flip generation circuit 42. A ROM 45 and a RAM 46 are connected to the CPU 41 via an address bus 46 and a data bus 44. This ROM 45 stores an operation program, which will be described later, and the CPU 41 operates according to this operation program. The RAM 46 has a storage area as described later, and the CPU 41 is connected to a group of display data latches and an input latch via a data bus 4'4. The CPU 41 is used for the RAM 46 and the second group for display.
The write control signal <WR) is input from the write control signal <WR), and its write timing or latch timing is controlled. Also, ROM45, RAM46 and input latch have CP
A successive control signal (RD) from U41 is applied, and its detection timing or latch timing is controlled.

Further, an address decoder 47 is connected to the CPU 41 via an address bus 46. ROM45, RAM46
, a group of display latches, and an input latch are provided with a chip enable from this address decoder 47.

A signal (CE) is given. and address decoder 4
ROM45 by outputting UO or Un address from 7.
is activated and RA is activated by outputting addresses Yo to Yn.
M46 is activated, and addresses no to n13 are assigned to the display launch group and input latch.

Here, latches no to n11 are display data latches. Lattes n12 and n13 are included in an input latch 49, and switches 12M and 12C.

Mode switching, time setting, and time display commands are given from 12S and 12N. Furthermore, a one-second clock signal φ2 is applied to the input terminal 42 from the clock generation circuit 42. This 1 second clock φ2 has a repetition period of 1 second,
The output level is reversed every 0.5 seconds. Go to latch no. or latch 11.

The checked display data is given to the display driver 48.

This display driver 48 includes an exclusive or gate provided for each via 1- of latch data from latches no to n11.

Figures 5 and 6 show this exclusive gate and timing chart. As shown in the figure, this exclusive/poor gate is supplied with a child signal and also supplied with a display clock φ from a clock generation circuit 42. When the display clock φ1 and the latch signal do not match, a character drive signal is output.

FIG. 7 is an illustrative diagram showing storage areas of the RAM 46 and CPU 41 shown in FIG. 4. Here, this RAM46 is 8
Each bit is assigned to an address from YO to Y18-1.

Addresses YO to Y9 are used as registers and counters for storing the respective time periods for contestants R and R. Y
Addresses LO to Y15 are used as time counters to measure the elapsed time of contestants R and R, respectively. Y16 or Y
Address 18 is used as a flag area for storing the type of switch operated and the rise of the output of the one-second clock φ2 of the clock generating circuit 42 shown in FIG.

FIG. 8 shows the bits at addresses Y16 to Y18 mentioned above.

FIG.

9 to 16 are flowcharts for explaining the operation of this embodiment. In FIG. 9, the mode is first set. FIG. 10 shows the steps (S in the illustration) of the main routine of the electronic chess clock of the present invention.

First, in step 101, KEY2 of the RAM 46 is rewritten in response to the operation of a switch or the rise of the output of the 1 second clock φ2 from the clock generation circuit 42. This step 101 subroutine is the 11th subroutine.
As shown in the figure. At step 101a in FIG. 11, the contents of the input latch are transferred to the CPU by the address decoder 47.
It is transferred to register A of No. 41. And step 101
At b, the contents of register A and the contents of KEY2 are logically summed and the result is written to KEY2. Therefore, even if the same switch is pressed continuously, KEY2 can only be rewritten once. Furthermore, when the one-second clock φ2 is input, the contents of KEY2 change only at the rising edge of φ2, so each second counter, which will be described later, is updated every second.

Step 102 is for setting the time limit, and its subroutine is shown in FIG. 12 in abbreviated form. Next, in step 106, the remaining times of the contestants R and R are converted into seconds, and in step 104, they are gelatinized.

In step 105, initial values are cleared. Thereafter, step 106. until switch 12L or 12R is pressed.
Repeat step 107, and if you press 12L, step 201
or if you press 12R, it will move to step 01.

In step 601 shown in FIG. 10, it is determined whether the 7th bit of KEY2 is set (1 sec: see FIG. 8). As mentioned above, the one-second clock φ2 applied to the circuit 49 has a repetition period of one second, and its output level is inverted every 0.5 seconds. Since the 7th bit and G of KEY2 are set only by the rise of this 1 second clock φ2, the 7th pin of KEY2 is set at 1 second every second.
Times.

will be played. Therefore, in step 201, KEY2
The operation is repeated until the 7th bit 1 is set. However, if it is determined in step 201 that the seventh bit of KEY2 is set, each counter is activated in step 202.

Next, if you press switch 12R while timer R is operating,
It is determined as in step 206 and the process moves to step 301. If the switch 12R is not operated in step 206, the process proceeds to step 204, where it is determined whether ZR is 60 or not.

If ZR reaches 60, it is converted as in step 205, and in the same way, it is determined in step 206 whether YR has reached 60, and if YR reaches 60, it is converted as in step 207. . 2 The aforementioned XRXYR,
ZR is display data in hours, minutes, and seconds of the elapsed time of the contestant R, and is displayed as in step 208. Furthermore, in step 209, it is determined whether UR has become less than 0. If UR has not become less than 0 in step 209, the process returns to step 201 as shown in the figure, or in step 209, UR has become less than 0. Then, the process moves to step 401, where a piezoelectric buzzer or the like is used to generate a sound to notify that the time limit has expired.

After this, steps 402 and 403 are repeated until the switch 128-t or the switch 12C is operated, and if the switch 12S is pressed, the value latched in step 104 is substituted in step 404, and then the process returns to step 105, and the remaining time is You can now start the timer without having to reset it. Further, in step 406, when the switch 12C is pressed, the process returns to step 101.

For steps 301 to 309, the first
As shown in Figure 0, steps 201 to 209
Therefore, after one of the timers starts, each time the switch 1゜2L If the limit is reached, it indicates that the time limit has expired. Note that in the above-mentioned program, the time is displayed as an addition display, but it is also easy to display the time as a subtraction display.

FIG. 13 shows a flowchart when the mode changeover switch is set to TIME. For example, only the liquid crystal display panel 11L is used, and since this is a function of a normal watch, only a flowchart will be shown and the explanation will be omitted.

In the embodiments described above, a liquid crystal display panel is used as the time display panel, but the display panel may be constructed using a power-saving means such as an electrochromic display. Furthermore, in order to make it easier to understand which turn it is, that is, which timer is operating, switch 12L is used.
, R may be made of translucent resin with a built-in electric light, or high-intensity LEDs may be provided near each of the switches 12L and 12R, making it easier to use.

14A to 14C show an embodiment in which the main body is shaped like a rectangular parallelepiped, and FIG. 14B shows an embodiment in which the number of display panels is increased in order to simultaneously display the initial setting time and the elapsed time. Figure 14C is an example in which functions are omitted as much as possible, the player's turn can be seen only by a switch with a built-in light, and the elapsed time of the active timer is alternately displayed on one display panel. .

FIG. 15 is a flowchart of an embodiment of an electronic chess watch that displays subtraction.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of an embodiment of the present invention. FIG. 2 is a rear view of the electronic chess clock shown in FIG. 1. FIG. 6 is an example of a liquid crystal display panel. FIG. 4 is an embodiment of the present invention. Figures 5 and 6 are block diagrams showing the exclusive OR gate and timing chart. Figure 7 is an illustrative diagram showing the storage areas of the RAM 46 and CPU 41 shown in Figure 4. Figure 8 is addresses Y16 to Y18. Figures 9 to 16 are flowcharts for explaining the operation of one embodiment of the present invention. Figures 14A to 0 are diagrams showing other embodiments of the present invention. Figure 15 is a subtraction display. Flowchart for enabling the operation of an electronic chess clock Patent applicant Hiroki Ishijima f11 12 115 times 1! 6th 1! 71! l % 18 figure parrot? In the figure ■ All 11 figures + 31;

Claims (1)

[Scope of Claims] Two sets of timer functions for counting the time consumed by the 12 sets of competitors, one common central control device for operating both timer functions alternately, An electronic chess clock having one or more display panels responsive to display the time. 2. In response to at least one operating means, the central control device causes one of the two timers to operate while the other stops, counts and displays the total operating time of each timer, and calculates and displays the total operating time of each timer. The electronic chess clock according to claim 1, characterized by a function of notifying the end of the timer by sound or the like when one of the timers reaches the first set time. 6. The electronic chess watch according to claim 1 or 2, which is capable of selectively displaying the functions of a normal watch (timer, alarm, stopwatch), etc. using a mode changeover switch.