JPS60221818A - Information apparatus - Google Patents

Abstract

PURPOSE:To execute efficiently the processing of a program, when a drop of a power supply voltage has been reset, by providing a main CPU for controlling the whole device, and the first and the second slave CPUs, and providing an LCD control function for a display, a keyboard and a clock function. CONSTITUTION:Arithmetic and the whole system are controlled by a main CPU 1 of an electronic apparatus for executing reprocessing after a power supply voltage has dropped. Also, an I/O port 4 for executing connection to a peripheral apparatus, an interrupting controller 9 for controlling an interruption from the outside, a ROM 2, a RAM 3, etc. are connected to the CPU 1. Moreover, a sub-CPU 5 having a controller function for controlling an LCD for display is connected to the CPU 1, and by an instruction of the CPU 1, the contents of a ROM capsule 6 are loaded to the RAM 3. Also, a sub-CPU 10 having a keyboard and a clock function is connected to the CPU 1. In this state, when a drop of the power supply voltage has been reset, a program is processed in succession to a result of the previous processing.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to information equipment, and more particularly to information equipment that efficiently performs restart processing after a power failure.

(Prior Art) In conventional information equipment, once the power supply voltage begins to drop, the subsequent restart process requires executing the program from the beginning again, which is extremely inefficient.

(Objective) It is an object of the present invention to provide an information device that eliminates the above-mentioned drawbacks and efficiently executes a program in a restart process after the power supply has once decreased.

(Embodiment) FIG. 1 is a schematic block diagram showing an embodiment of the present invention. The main CPU 1 performs calculations and controls the entire system. In addition, the main 0PU1 has two slave CPUs, namely slave 0FUS and slave f:
! I have PU 10i. Commands and data are exchanged between the main 0PUI, slave 0PU5, and slave 0PU10. The slave cpns functions as an LCD controller that controls the LOD (not shown) for display, and also loads the contents of the ROM capsule 6 into the RAM 3 according to instructions from the main QpU1. On the other hand, the slave QPU 10 controls the keyboard (not shown), clock function, and power supply.

Next, the computer 10 board 4 connects with other peripheral devices, and the interconnected controller 9 controls all interrupts from the outside. Furthermore, 7 is a serial controller, and 8 is a timer. The ROM2 stores a program for starting the program, and when the RQM is stored in the DROM capsule 6, the contents of the stored ROM are loaded into the RAM 5 by the starting program of the ROM2, and the program is started. Execution begins.

The RAM 5 is used as a work area for the basic program stored in the ROM 2 or as a user area.

Next, the basic software configuration of the embodiment shown in FIG. 1 will be explained using the block diagram shown in FIG.

In Figure 2, the upper part has a very high software level (close to a human level), and the lower part has a very low software level (close to a machine level).

mass, console Φ command processor (hereinafter referred to as OO)
Abbreviated as P. ) 22 accepts commands input from the console and executes the corresponding application program 2.
This is a program that loads and executes 1.

Next, the basic disk operating system (hereinafter abbreviated as BDO8) 25 is a program that manages files on the RAM disk and floppy disk. Further, the basic input/output system (hereinafter abbreviated as Bnee O8) 25 is an input/output interface program between the hardware of the standard device 30 and the operating system. Further, a microcassette tape operating system (hereinafter abbreviated as MTO8) 24 is a program for managing file t- of a microcassette tape (not shown). Furthermore, the microcassette input/output system 26 is an input/output interface program between the hardware of the microcassette 31 and the operating system. Further, the expansion BIO 827 is an input/output interface program between the hardware of the expansion device 32 and the operating system.

Next, the operation of the embodiment of the present invention shown in FIG. 1 will be explained.

First, RoM'i in which the application program for the business content that you want to use is stored in the ROM capsule 6.
(Once stored, the program is stored in RAM 5 by the slave aptrs that receive instructions from the main 0PU1.
loaded into. Thereafter, the entire system is controlled by the GPUI and processing proceeds.

Therefore, if the power supply voltage drops now, I will think about money. This drop in power supply voltage is detected by slave 0PUIO. Slave 0PU10#;l:, When detecting a drop in the tS voltage, interrupts the main QPU1 and notifies the main 0PU1 of the power fail.

As a result, the main aptz immediately interrupts the execution of the program, and if the microcassette (not shown) is in the process of reading/writing, the power 7 error is displayed after completing the processing for one clock. Thereafter, if a power switch (not shown) is not turned off within a certain period of time, the Lalepe 0PU1'0 forcibly turns off the power.

Further, the suspension of program execution will be explained in more detail below. Slave 0PU due to power drop
When the main apυ1 receives the notification from the main apυ1, it stores in the RAM 3 information necessary for resuming the execution of the program so that there is no problem even if the execution of the program is interrupted. For example, if you are reading a microcassette, the process will not be interrupted in the middle of one block, and the VC will be completely read until the end of the block.
Aborts post-read processing. Main CPU1
When a drop in power is reported from thread τ0PU10,
After saving the information necessary to resume program execution,
The process is interrupted at a convenient point. Also, in the embodiment shown in FIG. 1, the memory, ROM2 and RAM5 are
Although it is a single unit, it can be expanded to include multiple ROMs and multiple R
It may also be configured as an AM. Also, main 0PU1. Slave 0PU5 and slave 0PU10 may be n4-bit microprocessors, 8-bit microprocessors, or 16-bit microprocessors.

(Effects) As described above, the present invention allows the main 0PU1 to take necessary processing in advance when a drop in power is detected. Therefore, when the power is restored, the program can be executed not from the beginning but from the stage before the power was turned off, and the program can be executed efficiently.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention. M2
The figure is a diagram showing the basic software configuration of the present invention. 1...Main CPU 2...ROM 3...RAM 5...Slave CPU 6...ROM capsule 10... Slave cptr Applicant: Epson Corporation Suwa Seikosha Co., Ltd. Agent Patent Attorney Tsutomu Mogami

Claims (1)

[Claims] A main CPU that controls the entire device, a first slave CPU that controls the power supply section, a second slave CPU that controls the display section and a ROM capsule that stores the business program, and a second slave CPU that controls the entire device. 1. An information device comprising a ROM in which a basic program is stored, and a RAM which is a work area for the basic program and an area that can be used by a user.