JPS60218866A - Complementary mos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a latch-up phenomenon without reducing the integration degree, by providing the thickness of a semiconductor layer having low impurity concentration, in which MOS transistors are formed, so that the impurities of a substrate do not reach the surface of the semiconductor layer. CONSTITUTION:Ions are implanted in a P type silicon substrate 6 having high impurity concentration, and an embedded layer 7 having high inpurity concentration is formed. A P type silicon part is epitaxially grown. A semiconductor layer 8 having low impurity concentration is formed to a width so that the impurities of the substrate 6 do not reach the surface. Phosphorus ions are implanted, and an island region 9 including the embedded layer 7 is formed. A field oxide film 12 is formed. An N-channel MOS transistor is formed in a region 8a. A P-channel MOS transistor is formed in the island region 9 including the embedded layer 7. The resistance of the semiconductor substrate is made low and the island region is made deep. Thus a latch-up phenomenon can be made hard to occur to a large extent.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in complementary MO8 semiconductor devices.

[Prior Art] Figure 1 shows a cross-sectional view of the main parts of a conventional complementary MO5 semiconductor device.
P-type silicon base with low impurity concentration of Ωcm.

The plate is an n-channel MOS transistor formed on the main surface of this P-type silicon substrate (1).

(2a) is the n-type drain region of a solid MOS transistor.

(2b) is seen in the n-type source region. (3) is the n-type island region (hereinafter referred to as well) with a low impurity concentration selectively formed on the main surface of the P-type silicon substrate (1), and is this n
P-channel MO formed on the main surface of the type well (3)
(4a) is a P-type drain region of this MOS transistor, (4b) is a P-type source region. (5) is a buried oxide layer separating the sides of these MOS transistors.

By the way, in the structure constructed in this way, as shown in FIG. and a vertical pnp first transistor Q1 serving as a collector, an n-type well (3), a p-type silicon substrate (1), and an n-channel MO
S) There is a parasitic thyristor of pnpnm construction with a horizontal npn second transistor Q2 whose collector, base and emitter are the source region (2b) of the transistor, and the resistance component of the n-type well (3) - and the resistance components of the P-type silicon substrate (1) become base resistances Rwell (8a) and Rsub (la) of the first transistor Q1 and the second transistor Q2, respectively. And, such a parasitic thyristor is P
Channel MO3) Drain region (4a) of transistor W
is at a high potential, the P-type silicon substrate (1) and the n-channel M
The source region (2a) of the transistor (OS) is at a low potential (
For example, when it is set to GND), it may be activated by an external noise voltage. When a current flows, resulting in transistor Q2 becoming conductive, current flows through the base resistor Rweee (8a) of the first transistor QI to the collector (3) of transistor Q2, resulting in transistor Q1 becoming conductive. Become. Then, the current flowing from the collector (1) of transistor Q+ is connected to the base resistance Rsub (la) of transistor Q2.
The base of transistor Q2 is biased again, and a positive feedback circuit is eventually applied to the closed loop circuit consisting of transistors Q+ and Q2.

Even if the trigger current due to external noise disappears, the parasitic thyristor continues to operate, that is, there is a steady state between the drain region (4a) of the P-channel MOS transistor W and the source region (2b) of the n-channel MOS transistor. This is something through which current will flow.

This kind of phenomenon is generally called latch-up phenomenon.

This latch-up phenomenon not only impedes the normal operation of the complementary MOS semiconductor device, but also rarely causes permanent damage to the device.

The first and second methods to prevent this kind of latch-up phenomenon are
Base resistance Rsub (la) shown in the figure, Rwe44
A method has been considered to reduce t(8a) so that transistors Q+ and Q2 do not operate.The second method is to reduce the transistor current by changing the base width and base impurity concentration of transistor Q and transistor Q2. Amplification factor β [
β Zheng□ (where W is the base width and N is the base impurity concentration)
] can also be considered.

However, as in the first method, the base resistance Rsub
(la), Rweg6 (8a), it is necessary to increase the impurity concentration of the P-type silicon substrate (1) and the n-type well (3), and in this case, the threshold value of the MOS transistor This causes problems such as difficulty in controlling the voltage vth, and also causes problems such as difficulty in controlling the voltage vth.
If the purity concentration N is increased, there will still be problems such as difficulty in controlling the threshold voltage vth of the MOS I-transistor, and it is conceivable to increase the depth of Jl/ (3), but in this case, The diffusion in the lateral direction along the surface of the silicon substrate (1) also increases, resulting in a low integration density of 1", and in order to widen the base width W2 of the transistor Q2, a P-channel MO transistor and an n-channel MOS transistor are used. It is conceivable to widen the interval between the two, but this also rarely causes the problem of lowering the degree of integration.

[Summary of the invention]

This invention was made in view of the above points,
In a complementary MOS semiconductor device, a low impurity concentration semiconductor layer in which a MOS transistor is formed is provided on the entire surface of a first conductivity type high impurity concentration semiconductor substrate, and a first conductivity type MOS transistor is formed. The latch-up phenomenon is determined by assuming that the island region containing the buried layer of both impurity concentrations is formed on the entire surface of the semiconductor substrate, and that the thickness of the semiconductor layer is such that the impurities of the semiconductor substrate do not reach the surface of the semiconductor layer. The present invention proposes a complementary MOS semiconductor device that is extremely unlikely to occur, does not reduce the degree of integration, does not impede the operation of the second conductivity type MOS transistor, and can improve design latitude.

[Embodiments of the invention].

An embodiment of the present invention will be described below based on the drawings. FIG. 8(a) is a sectional view of a main part of a complementary MOS semiconductor device, and in FIG. 2, (6) is a semiconductor substrate of a first conductivity type with a high impurity concentration, and in this example, the resistivity is 0.01.
~1.0Ω・C11l, impurity concentration 5XIO"~5X
IO"Cm""', P-type silicon with crystal direction 400>. (7) is a buried layer with a high impurity concentration of the second conductivity type selectively formed on the - main surface of this semiconductor substrate (6). in,
In this example, phosphorus ions, which are P-type impurities, are implanted to a depth of about 10 cm.sup.(8) is formed on the main surface of the semiconductor substrate (6). (6) A low impurity concentration semiconductor layer of the first conductivity type formed by epitaxial growth to a thickness that does not allow the impurities to reach the surface. In this example, the layer thickness is lOμm and the resistivity near the surface is lO ~80Ω・
cm 2 of P-type silicon. (9) is an island region of a second conductivity type including a buried layer (7) formed by being exposed from the buried layer (7) to the main surface of the semiconductor layer (8), (xoaJ (lob) is each The semiconductor layer (8
) formed on the -main surface of the first conductivity type region (8a).
The drain region and source region of the conductivity type MOS transistor, C11a) (llb), are each the island region (9).
The drain region and source region of the first conductivity type MOS transistor formed on the main surface of (2) are non-MO8l-
A field oxide film is used to separate the transistors.Next, to describe a method for manufacturing a complementary MOS semiconductor device configured in this way, first, as shown in FIG. A buried layer (7) with a high impurity concentration is formed on the -main surface of the semiconductor substrate (6) by selectively implanting phosphorus ions using a mask □□□.

Thereafter, the mask 4 is removed, and as shown in FIG. 8(C), P-type silicon having a normal resistivity of 10 to 80 Ω·cm is deposited on the semiconductor substrate (6) on which a MOS transistor will be formed. Epitaxial growth is performed for about 80 minutes at a high temperature of about 1050° C. to form a semiconductor layer (8).

At this time, impurities in the semiconductor substrate (6) and buried layer (7) are assumed to be diffused into the semiconductor layer (8) by autodoping. Therefore, in this example.

The semiconductor layer (8) is formed to a thickness that does not allow impurities of the semiconductor substrate (6) to reach the surface, and by doing so, a MOS transistor can normally operate on the surface of the semiconductor layer (8). The resistivity can be maintained at 10 to 80 Ω·cm without any shadow IW caused by impurities in the semiconductor substrate (6). Next, as shown in FIG. 8(d), the same mask (to) as that used for forming the buried layer (7) is used.
the buried layer (7) from the surface side of the semiconductor layer (8) using
After implanting phosphorus ions in the same position as above, the mask was removed and then annealing was performed for a long time to 5μ.

However, at this time, the impurities from the buried layer (7) are also diffused at the same time, so they merge to form an island region of the second conductivity type.Therefore, the island region ( 2) is formed including a buried layer (7), and since the impurity diffusion in the subsequent process does not need to be formed so deeply, it can be formed with less horizontal spread and a deep vertical depth. It is.

After that, a field oxide film @ is formed in the same manner as in the manufacturing process of a conventional polysilicon gate type complementary MOS semiconductor device, and then a first conductivity type region (gap, that is, an island) of the semiconductor layer (8) is formed. On the surface side of the area surrounded by the field oxide film (b) where no ri is formed, there is an N-channel, ie, second conductivity type MOS transistor, and a second conductivity type high impurity concentration buried layer. On the surface side of the second conductivity type island region including (7), a P channel, that is, a first conductivity type MOS) transistor is formed;
A complementary MO5+ conductor device as shown in Figure (a) is obtained.

Even in the complementary MOS semiconductor device configured as described above, there are parasitic transistors Q, +Q2, etc. as shown in FIG. Because of this method, the current amplification factor of the parasitic transistor is low, so the collector current of the parasitic transistor Q1 is also small, and the resistance of the semiconductor substrate (6) corresponding to the resistor Rsub (la) is 0.01 to 1.0Ω. Since the resistance is as low as cm, the voltage applied to the base of the parasitic transistor Q2 becomes considerably smaller as the collector current decreases, and the possibility that the parasitic transistor Q2 becomes conductive becomes extremely small.

This makes the latch-up phenomenon extremely unlikely to occur. Moreover, despite these measures against latch-up, the second conductivity type island region expands in the lateral direction due to the use of the buried layer (7).

It is no different from a normal complementary MOS semiconductor device like the one shown in Fig. 1, but in some cases it is narrower.
The degree of integration is never compromised.

In addition, the surface of the first conductivity type region (8a) of the semiconductor layer (8) is not affected by impurities in the semiconductor substrate (6) and maintains a high resistance, so that the operation of the second conductivity type MOS transistor is improved. There is no hindrance at all. This means that the resistivity of the semiconductor substrate (6) is 0.01Ω°cm and the semiconductor layer (
8) when the resistivity is 20 Ω cm at the time of formation.
This is also clear from FIG. 4, which shows the P-type impurity concentration in the cross section at 8- in FIG. 4(d). In other words, in this case, the above 8th
Under the conditions for forming the complementary MOS semiconductor device shown in Figures (b) to (d), the diffusion of impurities from the semiconductor substrate (6) into the semiconductor layer (8) by autodoping is approximately 8 μm, and therefore the semiconductor layer If the thickness of (8) is thinner than 8 μm, MOS
) The operation of the transistor may be hindered, but if the thickness of the semiconductor layer (8) is 10 μm as in this example, the impurity-free region of the semiconductor substrate (6) is about 2 μm from the surface.
This depth of 2 μm is the depth of normal MOS
) Since the depth is sufficiently deeper than the source/drain impurity diffusion depth of the transistor, the operation of the MOS transistor is not hindered at all.

By the way, in the above embodiment, the thickness of the semiconductor layer (8) was set to 1011 m, but the inventors further investigated the relationship between the thickness of the semiconductor layer (8) and the latch-up phenomenon.

Figure 5 shows the results of the analysis. In the figure, the vertical axis is the current to keep the thyristor on, that is, the holding current, and the horizontal axis is the distance between the adjacent N-type diffusion layer and P-type diffusion layer of the first and second conductivity type MO5 transistors. Yes, the resistivity of the semiconductor substrate “without semiconductor layer” is lO~80Ω・cm,
r semiconductor layer thickness 10 μm.

The resistivity of the semiconductor substrate is 0 for 15μm and 20xmJ.
．． 01 to 1.0 Ω·cm.

As is clear from FIG. 5, the one provided with the semiconductor layer (8) is different from the conventional one shown in FIG. On the other hand, the latch-up phenomenon is extremely unlikely to occur. Furthermore, it can be seen that if the latch-up phenomenon is the same, that is, the holding current is the same, then this example has the advantage that the distance between the P-N diffusions can be narrowed and the degree of integration can be improved. Yes, if the thickness of the semiconductor layer (8) is less than 8 μm, the influence of impurities in the semiconductor substrate will affect the semiconductor layer (8).
8) Since it also appears on the surface, MO is present in this semiconductor layer (8).
If an S transistor is formed, the operating characteristics of the transistor (MOS) cannot be uniform, and if it is made even thinner, the surface layer of the semiconductor layer (8) will have a low resistance, and the MOS transistor will not have uniform operating characteristics.
The S transistor would stop working. Therefore, it is preferable for the thickness of the semiconductor layer (8) to be 8 μm or more in order to produce a good complementary MOS semiconductor device.

Furthermore, if the thickness of the semiconductor layer (8) is made thicker than 20 μm, the latch-up countermeasures due to the formation of the semiconductor layer (8) will not be much improved compared to the conventional one.
It is preferable to set it to 0 μm or less. In the above embodiment, P type is used as the first conductivity type.

Although N-type is used as the second conductivity type, the same effect can be obtained even if all P-type and N-type are replaced. In the above embodiment, when forming the second conductivity type island region with a low impurity concentration, part of it was relied on by ion implantation from the surface of the semiconductor layer a9. )
It may also be formed by autodoping from.

〔Effect of the invention〕

As explained above, the present invention provides a complementary MOS semiconductor device in which a MOS transistor is formed on one main surface of a first conductivity type high impurity concentration semiconductor substrate. The island region in which the first conductivity type MOS transistor is formed includes a buried layer formed on one main surface of the semiconductor substrate and has an impurity concentration equal to the thickness of the semiconductor layer. Since the thickness is such that it does not reach the surface of the semiconductor layer, the synergistic effect of lowering the resistance of the semiconductor substrate and making the island region deeper has the effect of making latch-up extremely difficult to occur.

Moreover, even if the island region is formed deeply, the lateral expansion is small, so the degree of integration is not impaired, and the second conductivity type MOS
) Since the impurity concentration on the surface of the semiconductor layer on which the transistor is formed is not affected by impurities in the semiconductor substrate, the operation of the second conductivity type MOS transistor is not hindered, and the design margin is improved. This is what we are doing.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a conventional complementary MO5 semiconductor device, FIG. 2 is an equivalent circuit diagram of a thyristor parasitic to a complementary MO8 semiconductor device, and FIGS. Fig. 8(a) is a sectional view of the main part. Fig. 8(b) to (d) is a sectional view of the main part shown in the order of '1.tl process. Figure 6 shows the relationship between the parasitic thyristor holding current and the film thickness of the semiconductor layer. (8) is a semiconductor substrate with a low impurity concentration of the first conductivity type, (in July, a buried layer with a Shima impurity concentration of the second conductivity type, and a semiconductor substrate with low impurity concentration of the first conductivity type.
r, (2) is a second conductivity type low impurity concentration island region including the buried layer (1), (10a) and (lob) are the second conductivity type MOS transistor drain region and source region, respectively. (lla) and (llb) are the drain region and source region of a first conductivity type MOS transistor, respectively. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa Fig. 1 (α) (b. Fig. 2 (C- (j Fig. 3 11 ↓ Kb'I tE A'i (un)1, Indication of the case Japanese Patent Application No. 59-752113, Part 5 to Hitoshi Katayama, representative of the person making the amendment, Column 6 for detailed explanation of the invention in the specification subject to amendment , Contents of the amendment (υIn the 7th page, line 14 of the specification, "P-type impurity" is corrected to "N-type impurity". (2) In the same M? page, 15th line, "I X 10sOcIR-
+1 J toru (correct D to rixxo16a J.

Claims (1)

[Scope of Claims] (1) A semiconductor substrate of a first conductivity type with a high impurity concentration, a buried layer with a high impurity concentration of an m2 conductivity type selectively formed on the entire surface of the semiconductor substrate, a semiconductor substrate with a high impurity concentration of the m2 conductivity type; a first conductivity type low impurity concentration semiconductor layer formed by epitaxial growth on a surface to a thickness such that impurities in the semiconductor substrate do not reach the surface, and a semiconductor layer of a first conductivity type with a low impurity concentration exposed from the buried layer to the entire surface of the semiconductor layer; a second conductivity type island region formed on the entire surface of the first conductivity type region of the semiconductor layer;) a source region and a drain region of the transistor;
a first conductivity type MOS formed on the entire surface of the island region;
) A complementary MO5 semiconductor device comprising a source region and a drain region of a transistor. 1) Complementary MO according to claim 1, characterized in that the resistivity of the semiconductor substrate of the first conductivity type is IQ-c+B or less, and the thickness of the semiconductor layer is thicker than 8 μm.
8 semiconductor devices. (3) The complementary type M according to claim 1 or 2, characterized in that the resistivity of the semiconductor layer in the region where impurities in the semiconductor substrate do not reach is 1 (1 to 80 Ω·cm).
O8 semiconductor device.