JPS60216719A - Device for protecting gto inverter against shortcircuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field to Which the Invention Pertains] This invention relates to a short-circuit protection device for a voltage source inverter using a gate turn-off thyristor. 1 is a main circuit connection diagram showing a conventional example of a short-circuit protection device for a GTO inverter configured with thyristors (hereinafter abbreviated as GTO); FIG. This first
In the figure, 1 is a DC power supply, 2 is a smoothing capacitor for removing the pulsation of DC power from the DC power supply 1, and 3 and 4 are DC reactors. The GTO input/<- circuit 5 has a snubber circuit 5S connected in parallel with a GTO thyristor 5G, a feedback diode 5D connected antiparallel to the GTO thyristor 5G, and a resistor and a capacitor connected in series.
An O thyristor arm is formed, and this GTO thyristor arm is bridge-coupled.
TO inverter 5 converts DC power from DC power supply 1 into AC power and supplies it to load 6 .

By the way, various modes of short-circuit failures may occur in this GTO inverter 5. For example, (a) when current is flowing through the feedback diode of a certain GTO thyristor arm, this feedback diode is destroyed by an overcurrent, and then the opposite arm (an arm of the same phase but opposite polarity to that arm) When the GTO thyristor fires due to a firing command. (b) When the GTO thyristor of a certain arm is destroyed by an overcurrent while it is energized, and the GTO thyristor of the opposite arm is subsequently fired by the firing command. (c) While current is flowing through the feedback diode of a certain arm, a firing command is input to the GTO thyristor of the opposing arm, and in the process of turning off the opposing arm as the GTO thyristor becomes conductive, the arm on the turn-off side The feedback diode may be damaged by overvoltage or the snubber circuit may be damaged by overcurrent, or the thyristor may not turn off completely.
o When a ignition command is sent to the GTO thyristor of the opposing arm at the moment of commutation failure, such as destruction of the GTO thyristor due to overvoltage or excessive voltage change rate during the process of turning off the thyristor. (E) GTO during turn-off
When the thyristor fires incorrectly. etc.

Even if a short-circuit failure occurs in various modes as described above, the bypass thyristor 7 is connected in parallel to the DC side of the GTO inverter 5 as shown in FIG.
When a short-circuit fault occurs in the O thyristor 5, this bypass thyristor 7 is made conductive to divert the fault current, thereby reducing the current flowing to the GTO thyristor in which the fault has occurred and the voltage at turn-off, thereby configuring this GTO inverter. By turning off all GTO thyristors, we are preventing this accident from spreading.

Or fuse 8 in series with each GTO thyristor arm.
is inserted, and the fuse 8 is designed to prevent the accident from spreading by using the fuse 8, which is protected and coordinated so that in the event of a failure, the fuse 8 blows out before the GTO thyristor breaks down.

Even if the protection device described above is installed, in order to cut off the fault current by the turn-off function of the GTO thyristor, the capacitor of the snubber circuit connected in parallel to the GTO thyristor must be fully discharged and the voltage change rate must be low. Two conditions must be satisfied: the function to suppress the GTO thyristor has been restored, and the current cut off by the GTO thyristor is smaller than the maximum controllable current specified for the GTO thyristor. However, in the case of the failure mode of (a) to (a) of the short circuit failures mentioned above, the GTO
Since a short-circuit accident occurs immediately after the thyristor is turned on, the snubber circuit must wait for the snubber capacitor to recover its function before turning it off. In order to prevent the fault current from increasing, the inductance of the DC reactor 3 provided in the DC circuit must be set to a large value. However, if the inductance of this DC reactor 3 is large, the loss generated in this DC reactor 3 during normal operation of the GTO inverter 5 will be large, resulting in a decrease in efficiency, and the cost and space required for this DC reactor 3 will also be large. There is a drawback.

When the AC output of this GTO inverter 5 is connected to a voltage source such as a power distribution system, this GTO inverter 5
Since there are a plurality of fault current sources flowing through the circuit, it becomes difficult to perform a bypass operation using the bypass thyristor 7 or the like.

If an attempt is made to protect the GTO thyristor by interrupting the fault current with fuse 8, the loss occurring in the healthy semiconductor element through which the fault current is flowing will be reduced within the time it takes for fuse 8 to complete its interrupting operation. A fuse must be selected that has a protection coordination that is acceptable for this semiconductor device. However, this protection coordination is normally considered based on the value of the square of the current flowing multiplied by the current flowing time, i.e. 1''t.However, the false firing or turn-off of the GTO thyristor If the gate pulse of a healthy GTO thyristor during turn-on or turn-off operation is stopped due to a failure mode such as incomplete or a failure is detected, the conductive part reaches a part of the pellet of the GTO thyristor. When there is no on-gate pulse, the conduction on the pellet of the GTO thyristor spreads much more slowly than that of a thyristor or diode, so the GTO thyristor does not secure the initially determined I't. Therefore, there is a risk that even a healthy GTO thyristor may be destroyed.

[Purpose of the invention]

When a short circuit failure occurs in the GTO inverter, this invention
It is an object of the present invention to provide a short-circuit protection device for a GTO inverter that can reliably minimize and eliminate the spread of failures with a simple device.

[Key points of the invention]

This invention provides a GTO inverter composed of GTO thyristors, in which a fuse is inserted in series with each GTO thyristor arm formed by a GTO thyristor, a feedback diode, and a snubber circuit, and an overcurrent detector is installed for each arm or each phase. The overcurrent detected by this is processed by a logic circuit, and an on command gate pulse is given to the GTO thyristors of both the positive and negative arms of the phase where the short circuit occurred, and the GTO thyristors of the remaining arms are
By giving an off command to the capacitors of the snubber circuit connected in parallel to the TO thyristor in order of completion of discharge, the GTO thyristor in the healthy phase will cut off the current by itself, and in the faulty phase, the GTO thyristor will shut off. The fuse cuts off the fault current that flows to keep the inverter running, thereby reducing the fault current of the inverter to zero.

[Embodiments of the invention]

Fig. 2 is a main circuit connection diagram showing an embodiment of the present invention, and Fig. 3 is a logic circuit diagram showing an embodiment of the invention. has been done. Therefore, the details of the present invention will be described below with reference to FIGS. 2 and 3.

In FIG. 2, reference numeral 1 denotes a DC power supply, and the DC power from it is supported by a GTO inverter 5 via a smoothing capacitor 2, and the GTO inverter 5 converts the DC power into AC power and supplies it to a load 6. It has become. Here, the GTO inverter 5 is the GTO thyristor 5
G, a feedback diode 5D connected in antiparallel to this, and a snubber circuit 5S connected in parallel to these form one set of GT.
It is constructed by forming an O thyristor arm and connecting the arms with a bridge. In addition, snubber circuit 5S
Although shown in FIG. 2 as a series circuit of a resistor and a capacitor, it may be a snubber circuit composed of, for example, a capacitor, a resistor, and a diode. Furthermore, a fuse 8 and a current transformer 11 are connected in series to each arm of this GTO inverter 5, and a resistor 12 is connected to the secondary circuit of the current transformer 11. This constitutes an overcurrent detector.

An overcurrent detector connected to the first phase positive side arm, generally referred to as arm U, outputs a current signal U3 corresponding to the current flowing through that arm. Similarly, current signals V3. W3 is being output. Further, arm X is an arm for the first phase, second phase, and third phase on the negative side.

The current signal X3 of the corresponding arm is also obtained from Y and z.
Y3. Z3 is obtained.

In FIG. 3, the above-mentioned current signals U3°V3.
W3. X3. Y3. Z3 is each comparator 21~
26, but these comparators 21 to 2
6, by comparing the voltage from the reference power supply 15 and the aforementioned current signals U3 to z3 to detect overcurrent, the current in each arm is converted into a digital signal indicating whether or not there is an overcurrent. , and when there is an overcurrent, the logic is 1.
Output. The outputs of these comparators 21 to 26 are led to AND elements 37 to 3=9 to determine whether both the positive and negative arms of the same phase are overcurrent at the same time, that is, whether or not both arms are conducting at the same time. That is, current transformer 11 and resistor 1
2 and reference power supply 15 and comparator, 21 to 26 and AND
Elements 37 to 39 perform overcurrent detection for each phase.

However, even though the GTO inverter 5 is not faulty, currents in the same direction may flow simultaneously in both the positive and negative arms of the same phase. This is because the current flowing through the load 6 is almost zero, so even if the GTO thyristor in one arm is turned off, the capacitor of the snubber circuit is not charged, and when the GTO thyristor in the opposite arm is then turned on, this unused current flows from the DC circuit side. When charging current is supplied to the charging snubber capacitor and when current is flowing through the feedback diode, a reverse recovery current is supplied to the feedback diode so that the GTO thyristor in the arm opposite to it starts to turn on. After the feedback diode is turned off, the snubber capacitor connected in parallel to it is charged. Since these two modes are not abnormal, it is necessary to exclude them from abnormality detection.

Therefore, for each phase, for a certain period of time corresponding to the charging time of GTO-1+ of both the positive and negative arms, each (7) A
ND elements 37' to 39: 'R1, S1. A signal called TI is input. These signals R1, 81, and TI are always logic 1 signals, but there is a note that they become logic 0 only for the above-mentioned certain period of time to prevent abnormal signals from being output.
) No. 1 R1, 81, T1 and AND elements 37 to 39 form an overcurrent signal temporary blocking circuit.

AN when GTO inverter 5 is operating normally
Since the outputs of D elements 37 to 39 are logic 0, this signal passes through NOR element 41 and flip-flop element 42 to A.
Logic 1 is given to ND elements 51-56. Here arm U
(7) Command signal U to turn on and off the GTO thyristor
1 is input to the logic circuit shown in Fig. 3,
This signal Ul passes through an AND element 51, an OR element 61, and a monostable element 71, and is output as a signal U2. The on signal commanded by signal U1 is logic 1 and the off signal is logic 0.
Assuming that, the flip-flop element 4 during normal operation
The output of 2 is logic 1, and even if the input of monostable element 71 changes from logic 1 to logic 0, its output does not invert for a certain period of time, that is, remains logic 1, and changes to logic 0 after a certain period of time. It changes. Since this certain period of time is much shorter than the half cycle of the on/off operation of the GTO thyristor, the signal U1 input to this logic circuit and the signal U2 output from the logic circuit during normal operation are are completely in sync. This also applies to the input signals v1 to z1 and output signals v2 to Z2 of the other arms v, w, x, y, and z. Note that the signals of the positive and negative arms of the same phase, for example, the first phase input signals U1 and ■1
It goes without saying that both are never turned on at the same time.

Signals U2 to z2 output from the logic circuit shown in FIG. 3 are amplified by a circuit not shown, and a logic 1 becomes an on-gate pulse and a logic 0 becomes an off-gate pulse, turning on and off the GTO thyristor of the arm concerned. .

If a short-circuit accident occurs in which arm U and arm X become conductive at the same time, the current will be detected by the overcurrent detector and a current signal U3. When X3 exceeds the level set by the reference power supply 15, the output of the AND element 37 changes from logic 0 to logic 1, so the output from the AND element 37 becomes logic 1 regardless of the states of the on/off command signals Ul and Xi. The signal is interrupted and the OR elements 61, 62 and monostable element 7
After 1.72, the output signals U2 and X2 immediately become logic 1, and the GTO thyristors of arms U and X are given an on-gate pulse.

The logic 1 signal from AND element 37 is on the one hand NOR
In order to send a logic 0 signal to AND elements 51-56 via element 41 and flip-flop element 42, signal V2°T2. W2. Z2 is the input signal Vl, Yl, Wl.

It is a logic 0 regardless of the state of zl, and an off-gate pulse is applied to the GTO thyristors of these arms. However, as mentioned above, in order to prevent the GTO thyristor from turning off immediately after the GTO thyristor is turned on and before the snubber capacitor has finished discharging, the snubber circuit starts its function after the monostable elements 73 to 76 have been turned on for a certain period of time. The turn-off signal is not output during the time required to recover the condition, and the GT of that arm is
The O thyristor performs a turn-off operation. In this way, the fault current continues to flow through the GTO thyristor of the phase where the short circuit occurred.
Either one of the fuses 8 inserted in the positive and negative arms of that phase is blown out, and the semiconductor element of the failed phase having an I''t larger than the I''t of that fuse is prevented from being destroyed. In addition, the load 6 is connected between the AC output terminal of the healthy phase GTO thyristor and the AC output terminal of the faulty phase, and the time constant is usually large, so the increase in fault current is relatively slow. Turn-off is possible even after one failure occurs.

FIG. 4 is a logic circuit diagram showing a second embodiment of the present invention, which differs from the embodiment shown in FIG. 3 in that overcurrent is detected for each arm. That is, comparators 21-2
The outputs of 6 are input to AND elements 31 to 36 separately, and the outputs of these AND elements 31 to 36 are input to OR elements 61 to 66 respectively to turn on and off the GTO thyristor of the arm. The logic circuit is the same as the logic circuit shown in Fig. 3 except that the signal input to the NOR element 41 is changed from the number of phases to the number of arms. Although a description of the operation will be omitted, with this configuration, it is possible to detect failures other than DC short circuits, such as a short circuit accident on the load 6 side.

As a modification of the above-described embodiment, there may be a method of detecting the conduction state from the voltage of each arm instead of detecting the current of each arm, or a method of detecting the conduction state from the voltage of the arm instead of detecting the current of each arm, or applying abnormality prevention signals R1,
81, instead of inputting Tl, the AND elements 37 to 3
It is also consistent with the spirit of the present invention to configure a logic circuit that determines that there is an abnormality when the logic 1 signal outputted by 9 continues for a certain period of time or more.

〔Effect of the invention〕

According to this invention, an on-gate pulse is immediately applied to a phase or arm in which a failure has occurred in a GTO inverter to sustain the failure current, and the failure and current are suppressed by a fuse that has protection coordination with the semiconductor element of the arm. Since the fault current exceeds the maximum controllable anode current of the GTO thyristor, there is no risk of turning it off and destroying the device.In addition, for a healthy phase or arm, the snubber connected to the arm The circuit is configured to turn off the GTO thyristors after their circuit function has been restored, so even if a short circuit occurs, either the positive or negative fuse of the faulty phase will simply blow, reducing the fault current to zero. Therefore, parts replacement can be kept to a minimum, and operation can be resumed immediately. Furthermore, everything necessary to achieve this effect is comprised of logic circuits, except for the current transformer, so it is small and lightweight, and the increase in cost is negligible, and there is no energy loss during operation. It also has the effect of improving efficiency because it does not.

[Brief explanation of drawings]

FIG. 1 is a main circuit connection diagram showing a conventional example of a short circuit protection device for a GTO inverter. FIG. 2 is a main circuit connection diagram showing an embodiment of the present invention, FIG. 3 is a logic circuit diagram showing an embodiment of the invention together with FIG. 2, and FIG. FIG. 2 is a logic circuit diagram showing an embodiment of the present invention. 1... DC power supply, 2... Smoothing capacitor, 3, 4...
...DC reactor, 5...GTO inverter, 5D
...Feedback diode, 5G...GTO thyristor,
5S...Snubber circuit, 6...Load, 7...Short circuit thyristor, 8...Fuse, 11...Current transformer, 12
...Resistor, 15...Reference power supply, 21-26...Comparator, 31-39...AND element, 41...
NOR element, 42... flip-flop element, 51-
56...AND element, 61-66...OR element, 7
1-76... Things Figure 3 Figure 4

Claims (1)

[Claims] A voltage type GT that converts DC power into AC power by connecting a GTO thyristor arm in which a gate turn-off thyristor and a feedback diode are connected in anti-parallel, and a snubber circuit is connected in parallel to the anti-parallel connection circuit, and is bridge-coupled.
In the O inverter, a fuse is connected in series to each arm of the GTO inverter, an overcurrent detector detects overcurrent in each arm or each phase, and an on-gate pulse is applied to the gate turn-off thyristor, and then the snubber circuit is connected. An overcurrent signal temporary blocking circuit is configured not to output an overcurrent signal from the arm or phase during a predetermined period of time that overlaps with the charging time, and the hot current detector is connected via the overcurrent signal temporary blocking circuit. The output overcurrent signal gives an on-gate pulse to the gate turn-off thyristor of that arm or phase, and an off-gate pulse to the gate turn-off thyristors of the remaining arms or phases after the snubber circuit connected to that arm has completed discharging. 1. A short-circuit protection device for a GTO in/f-event, characterized in that it comprises a gate pulse control circuit configured to provide a gate pulse control circuit.