JPS60216599A - Method of producing thickn film hic - Google Patents

Method of producing thickn film hic

Info

Publication number
JPS60216599A
JPS60216599A JP7184284A JP7184284A JPS60216599A JP S60216599 A JPS60216599 A JP S60216599A JP 7184284 A JP7184284 A JP 7184284A JP 7184284 A JP7184284 A JP 7184284A JP S60216599 A JPS60216599 A JP S60216599A
Authority
JP
Japan
Prior art keywords
hic
insulating layer
conductor
film
thick film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7184284A
Other languages
Japanese (ja)
Other versions
JPH0248156B2 (en
Inventor
鍵井 孝夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP7184284A priority Critical patent/JPS60216599A/en
Publication of JPS60216599A publication Critical patent/JPS60216599A/en
Publication of JPH0248156B2 publication Critical patent/JPH0248156B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (技術分野) 本発明は厚膜HICの製造方法、特に厚膜HICの多層
化に関するものである・ (従来技術) 従来の厚膜HICの回路印刷において、印刷で形成され
る回路部分(導体、抵抗など)は20〜40μmの厚さ
を持っており、多層化する場合はこの上に絶縁層を重ね
た後、更に回路を印刷して積み重ねを行なっていた。
Detailed Description of the Invention (Technical Field) The present invention relates to a method for manufacturing a thick film HIC, and in particular to multilayering of a thick film HIC. (Prior Art) In conventional thick film HIC circuit printing, The circuit parts (conductors, resistors, etc.) to be used have a thickness of 20 to 40 μm, and in the case of multilayering, an insulating layer is layered on top of this, and then circuits are printed and stacked.

第1図は従来における多層化印刷の過程を示すものであ
シ、第1図(、)に示すセラミック基板1に導体20を
印刷した後(第1図(b) ) 、絶縁層30を印刷し
く第1図(C))、その後その上に更に導体21を積み
重ねて印刷(第1図(d))するとともに、その上に絶
縁層を重ねて(第1図(C))他の導体を重ねるといっ
た工程にて多層HICを製造していた。
FIG. 1 shows the process of conventional multilayer printing. After printing a conductor 20 on a ceramic substrate 1 shown in FIG. 1(a) (FIG. 1(b)), an insulating layer 30 is printed. After that, the conductor 21 is further stacked and printed on it (Fig. 1 (d)), and an insulating layer is overlaid on it (Fig. 1 (C)). Multilayer HICs were manufactured using a process of stacking layers.

しかし、この方法によると印刷された膜厚の部分におい
て段差が生じる為、積み重ねた場合第2図に示すように
段差のエッヂ部分において回路が切れたシ、又極めて薄
くなるなどの原因による断線故障(P)、”ターンのシ
ョー) (Q)が生じ、信頼性劣化となる欠点があった
However, with this method, there is a step difference in the thickness of the printed film, so when stacked, the circuit breaks at the edge of the step, as shown in Figure 2, or the circuit becomes extremely thin, resulting in disconnection failures. (P), "turn show" (Q) occurs, which has the disadvantage of deteriorating reliability.

(発明の目的) 本発明の目的は、厚膜HICの印刷におめて発生する段
差を解消して従来発生しがちでおつ7z断線。
(Object of the Invention) The object of the present invention is to eliminate the level difference that occurs when printing thick film HIC, and to eliminate the 7z disconnection that tends to occur conventionally.

ショートをなくして歩留シならびに信頼性を向上するこ
とにある。
The objective is to eliminate short circuits and improve yield and reliability.

(発明の構成) 本発明は、配線回路を多層に重ねた厚膜HICの製造方
法であって、導体パターン等を有する層において導体な
らびに抵抗体等の厚さによって生ずる戸凸、を埋込絶縁
層にて平坦化した後、上層を順次形成することを特徴と
する厚膜HICの製造方法である。
(Structure of the Invention) The present invention is a method for manufacturing a thick film HIC in which wiring circuits are stacked in multiple layers, and in which a door protrusion caused by the thickness of a conductor, a resistor, etc. in a layer having a conductor pattern, etc. is embedded and insulated. This method of manufacturing a thick film HIC is characterized by sequentially forming upper layers after planarization.

(実施例) 第3図は本発明の製造方法を示す説明図′であシ、1は
セラミック基板、2oは第1導体、2ノは第2導体、4
0は焼成前の絶縁層、40ae41mは焼成後の絶縁層
、50.51は中間絶縁層である。
(Example) Fig. 3 is an explanatory diagram showing the manufacturing method of the present invention, where 1 is a ceramic substrate, 2o is a first conductor, 2 is a second conductor, 4
0 is an insulating layer before firing, 40ae41m is an insulating layer after firing, and 50.51 is an intermediate insulating layer.

まず、セラミック基板1上に第1導体2oを印刷する(
第3図(b))。次に第1導体20間の周辺領域の凹部
(へこみ部)に印刷によって埋込絶縁層40を第1導体
2oと同一の厚さに作る(第3図(C))。埋込絶縁層
4oは約8oo℃近辺において流動性を持たせることが
でき、第1導体2oとの接着ならびに平坦化が容易に行
なえる厚膜に一ストを用いている。この厚膜に一ストは
樹脂を有機溶媒に溶かしたビヒクルにガラスフリットを
分・ 散混練したものである。第3図(、)の状態にて
焼成することによって、埋込絶縁層4oは第3図(、)
に示す焼成後の絶縁層40aのように第1導体20間を
埋めて平坦化される。埋込絶縁層40の形成方法は印刷
忙よる方法が一般的であシ、印刷パターンは第1導体2
0のパターンのネガノ9ターンであるようにし、かつ3
〜5μmの間隔を開けた印刷A’ターンが望ましい。こ
の間隔が第3図(c)の第1導体20と埋込絶縁層40
との間隔である。そしてこの微小間隔は焼成による溶融
によって埋められ、第1導体20との接合部において高
低差は生じないものとなる。又その結果、マスクツ母タ
ーンの持つ精度誤差を許容することにもなる。
First, the first conductor 2o is printed on the ceramic substrate 1 (
Figure 3(b)). Next, a buried insulating layer 40 is formed to have the same thickness as the first conductor 2o by printing in the recessed portion (dented portion) in the peripheral area between the first conductors 20 (FIG. 3(C)). The buried insulating layer 4o is made of a thick film that can have fluidity at around 80° C. and can be easily bonded to the first conductor 2o and flattened. This thick film is made by dispersing and kneading glass frit into a vehicle in which resin is dissolved in an organic solvent. By firing in the state shown in Fig. 3(,), the buried insulating layer 4o is formed as shown in Fig. 3(,).
The space between the first conductors 20 is filled and flattened like the insulating layer 40a after firing shown in FIG. The buried insulating layer 40 is generally formed by printing, and the printed pattern is formed on the first conductor 2.
Make it a negative 9 turn with a pattern of 0, and 3
Printed A' turns spaced ~5 μm apart are preferred. This distance is between the first conductor 20 and the buried insulating layer 40 in FIG. 3(c).
This is the interval between This minute gap is filled by melting during firing, and no difference in height occurs at the joint with the first conductor 20. Moreover, as a result, the accuracy error of the master turn of the mask can be tolerated.

次に、中間絶縁層56(流動性の小さいもの)を印刷形
成する(第3図(e))。この時の焼成温度は800℃
を20〜50℃下廻ることが必要である。続いて第3図
(f) K示すように、第2導体21を印刷し、以後同
様に埋込絶縁層41a、中間絶縁層5ノを順に印刷する
。この場合、上層へいくに従って焼成温度が1層毎に2
0〜50℃低くなるペースト材料を選ぶことが必要であ
る。
Next, an intermediate insulating layer 56 (of low fluidity) is formed by printing (FIG. 3(e)). The firing temperature at this time is 800℃
It is necessary to keep the temperature below 20 to 50°C. Subsequently, as shown in FIG. 3(f)K, the second conductor 21 is printed, and thereafter, the buried insulating layer 41a and the intermediate insulating layer 5 are sequentially printed in the same manner. In this case, the firing temperature increases by 2% for each layer as you go to the upper layer.
It is necessary to choose a paste material that is 0-50°C lower.

又、絶縁ペーストにて埋込絶縁層ならびに中間絶縁層を
作る場合、上述のように印刷によって行なう以外に、ス
ピン塗布又はホイラー塗布による方法を使用することも
できる。この方法は回転体上にペーストを載せた基板を
置き、遠心力によってイーストを塗布するものであシ、
絶縁ペーストの粘度、固形含有率を適正条件とすること
で膜厚をコントロ°−ルするものである。
Further, when forming the buried insulating layer and the intermediate insulating layer using an insulating paste, in addition to printing as described above, spin coating or wheeler coating can also be used. This method involves placing a substrate with paste on a rotating body and applying yeast using centrifugal force.
The film thickness is controlled by adjusting the viscosity and solid content of the insulating paste to appropriate conditions.

(発明の効果) 本発明に係わる厚膜HICの製造方法においては、従来
の絶縁層一層に加えて埋め込み層を設けて各層における
回路印刷面を平坦化している為、上層に重ねて回路印刷
を行なうにあたって、回路パターンの重な多部分におい
て段差を生ずることがなく1厚膜HICの断線の発生、
ショートをなくして信頼性を向上できる利点がある。
(Effects of the Invention) In the thick film HIC manufacturing method according to the present invention, in addition to the conventional single insulating layer, a buried layer is provided to flatten the circuit printing surface of each layer, so the circuit printing is performed by overlapping the upper layer. In this process, there is no step difference in many overlapping parts of the circuit pattern, and the occurrence of disconnection of one-thick film HIC.
This has the advantage of eliminating short circuits and improving reliability.

又平坦面が得られる為、精細ノ4ターンの印刷。Also, since a flat surface can be obtained, fine 4-turn printing is possible.

細線の焼付を容易に行なうことができ、実装密度の高い
回路配線が可能となる利点を有する。
It has the advantage that fine wires can be easily printed and circuit wiring with high packaging density is possible.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来における多層化印刷の過程を示す説明図、
第2図は従来において断線、ノ母ターンショートを生じ
て信頼性が低下することを示す説明図、第3図は本発明
の製造方法を示す説明図である。 1・・・セラミック基板、20・・・第1導体、21・
・・、゛ 第2導体、40・・・焼成前の絶縁層、40m、41a
・・・焼成後の絶縁層、50.51・・・中間絶縁層。 特許出願人 沖電気工業株式会社 第1図 第2図 20 〜1 (0)ロニ==二二=上1 0
Figure 1 is an explanatory diagram showing the process of conventional multilayer printing;
FIG. 2 is an explanatory diagram illustrating that reliability is lowered due to wire breakage and short-circuiting in the prior art, and FIG. 3 is an explanatory diagram illustrating the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 20... First conductor, 21.
..., ``Second conductor, 40... Insulating layer before firing, 40m, 41a
... Insulating layer after firing, 50.51 ... Intermediate insulating layer. Patent applicant Oki Electric Industry Co., Ltd. Figure 1 Figure 2 20 ~ 1 (0) Roni = = 22 = Top 1 0

Claims (1)

【特許請求の範囲】[Claims] 配線回路を多層に重ねた厚膜HICの製造方法であって
、導体ノ4’ターン等を有する層において導体ならびに
抵抗体等の厚さによって生ずる凹凸を埋込絶縁層にて平
坦化した後、上層を順次形成することを特徴とする厚膜
HICの製造方法。
A method for manufacturing a thick film HIC in which wiring circuits are stacked in multiple layers, in which unevenness caused by the thickness of conductors, resistors, etc. in a layer having 4' turns of conductors, etc. is flattened with a buried insulating layer, and then A method for manufacturing a thick film HIC, characterized in that upper layers are sequentially formed.
JP7184284A 1984-04-12 1984-04-12 Method of producing thickn film hic Granted JPS60216599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7184284A JPS60216599A (en) 1984-04-12 1984-04-12 Method of producing thickn film hic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7184284A JPS60216599A (en) 1984-04-12 1984-04-12 Method of producing thickn film hic

Publications (2)

Publication Number Publication Date
JPS60216599A true JPS60216599A (en) 1985-10-30
JPH0248156B2 JPH0248156B2 (en) 1990-10-24

Family

ID=13472193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7184284A Granted JPS60216599A (en) 1984-04-12 1984-04-12 Method of producing thickn film hic

Country Status (1)

Country Link
JP (1) JPS60216599A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185398A (en) * 1986-01-31 1987-08-13 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Thick film circuit device containing ceramic substrate
JPS6353995A (en) * 1986-08-22 1988-03-08 株式会社東芝 Manufacture of wiring board
JPH02156596A (en) * 1988-12-08 1990-06-15 Matsushita Electric Ind Co Ltd Manufacture of thick multilayered substrate
JPH05218605A (en) * 1992-09-25 1993-08-27 Matsushita Electric Works Ltd Circuit board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60102763A (en) * 1983-11-09 1985-06-06 Hitachi Ltd Multilayer thick film hybrid integrated circuit substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60102763A (en) * 1983-11-09 1985-06-06 Hitachi Ltd Multilayer thick film hybrid integrated circuit substrate

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62185398A (en) * 1986-01-31 1987-08-13 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Thick film circuit device containing ceramic substrate
JPS6353995A (en) * 1986-08-22 1988-03-08 株式会社東芝 Manufacture of wiring board
JPH02156596A (en) * 1988-12-08 1990-06-15 Matsushita Electric Ind Co Ltd Manufacture of thick multilayered substrate
JPH05218605A (en) * 1992-09-25 1993-08-27 Matsushita Electric Works Ltd Circuit board

Also Published As

Publication number Publication date
JPH0248156B2 (en) 1990-10-24

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