JPS60216581A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To miniaturize the base region, and to reduce the base resistance by a method wherein each electrode region, each active region, and the like are formed in self-alignment. CONSTITUTION:An SiO2 film 13, an Si3N4 film 14, a B-doped polycrystalline Si film 15, and an SiO2 film 16 are formed on a p<-> type Si substrate 11 on which an n type active region 11A and a field insulation film 12 have been formed. Next, an aperture 15A is formed in the films 16 and 15, and the SiO2 film 16 is formed by oxidizing the film 15 exposed in the aperture 15A. Then, a polycrystalline film 17 filling the aperture 15A is formed. After removal of the film 16, an aperture 13A is formed by etching the films 14 and 13 by using the films 15 and 17 as a mask. The film 17 is removed, and a polycrystalline Si film 18 is formed. The film 18 is left only on the side wall of the film 15 in the aperture 15A by etching. An SiO2 film 19 is formed by heat treatment, and the p<+> base- contact regions 20 are formed by B diffusion to the region 11A from the film 15 via film 18.

Description

(Detailed Description of the Invention) Technical Field of the Invention The present invention relates to high-speed bipolar semiconductor devices or MIs (
metal 1nsulator semiconductor
ctor) This invention relates to a method of manufacturing a semiconductor device suitable for use in miniaturizing a field effect semiconductor device.

Prior Art and Problems FIG. 1 is a cross-sectional side view of essential parts of a conventional high-speed bipolar semiconductor device having a field insulating film formed by applying a selective oxidation method.

In the figure, 1 is a p-type silicon (Si) semiconductor substrate;
2 is an n+ type buried layer, 3 is an epitaxially grown n-type silicon semiconductor layer which partially acts as a collector layer, 4 is a field insulating film made of silicon dioxide (SiOz), and 5 is a thin insulator made of silicon dioxide that covers the active region. 6 is a p-type base layer, 7 is a p+-type base contact region, 8 is an n+-type emitter region, 9 is an n+-type collector contact f+Ji region, and rb is a base resistance.

When forming the p+ type base contact region 7 and the n+ type emitter region 8 in this bipolar semiconductor device, the steps explained with reference to FIG. 2 are necessary.

FIG. 2 is a cutaway side view of the main parts of the semiconductor device at key points in the process for manufacturing the bipolar semiconductor device shown in FIG. 1, and the same parts as those explained in FIG. It is.

In the figure, 10 is the photoresist film and L is the base film.
The width of the base layer 6 including the contact region 7 is shown.

Using this photoresist film IO as a mask, the silicon dioxide film 5 is patterned to form openings, through which electrode contacts for the p+ type base contact region 7 and the n+ type emitter region 8 are made.

By the way, in order to improve the operating speed of a bipolar semiconductor device, it is effective to reduce the parasitic capacitance, that is, to downsize the transistor, and to reduce the base resistance rb, that is, to reduce the base resistance. It is effective to shorten the distance between contact region 7 and emitter region 8.

However, the photoresist film 10 seen in FIG.
If the current photolithography technology is used, the width will be 1.5 μm or more.

Furthermore, if the width of the base layer 60 shown in FIG. 2 is made smaller, the area of the transistor becomes smaller, leading to higher speed, but it is necessary to include a predetermined positioning margin in determining the width. , which will be explained in more detail with reference to FIG.

FIG. 3 is an explanatory diagram showing the relationship between various dimensions when forming the photoresist film 10 shown in FIG. 2.

That is, in order to form a photoresist film IO with a width of 1.5 [μm], the alignment margin A is 0.5 [μm] on both sides of the photoresist film 10, and the base electrode is placed on the outside of them. Width of contact window and emitter electrode contact window 1
It is necessary to take 0.5 [μm] for each of 2, and the total value is 3.5 [μm], which is close to the limit of current photolithography technology.

As mentioned above, in order to form the photoresist film 10 with a width of 1.5 [μm], the alignment margin is 27!
, = 1 (μm) is also taken. If the margin is not sufficient and the photoresist film 10 is displaced beyond the margin, in the illustrated structure, the base This is because the area of the contact region 7, emitter region 8, etc. will be directly affected, and the transistor operation will be hindered.

Therefore, with the conventional techniques described above, it is impossible to miniaturize this type of bipolar semiconductor device, reduce the value of the base resistance, or reduce the alignment margin.

In addition to the bipolar semiconductor device described above,
It goes without saying that even in a Mis field effect type semiconductor device, if the area can be reduced and the channel can be shortened, the speed can be increased.

Purpose of the Invention The present invention provides a method for forming a base/contact region, forming an extraction electrode therefrom, forming a base region and an emitter region, or forming a source region and a drain region, forming an extraction electrode therefrom, etc. The self-alignment method can be used to make the base region smaller and the base resistance smaller, or the M
Provided is a method for manufacturing a semiconductor device that makes it possible to downsize an IS field effect semiconductor device.

Structure of the Invention In the method for manufacturing a semiconductor device according to the present invention, a first insulating film, a first polycrystalline silicon film containing a -conductivity type impurity, and a second insulating film are sequentially formed on a silicon semiconductor substrate. forming an opening in the second insulating film and the first polycrystalline silicon film on a predetermined portion of the active region to expose a part of the surface of the first insulating film; Next, the first polycrystalline silicon film exposed as a sidewall in the opening is oxidized to form an insulating film continuous to the second insulating film, and then a second polycrystalline silicon film is formed to fill the opening. A silicon film is formed, and then the second insulating film and the insulating film connected thereto are removed, and then the second insulating film is removed.
etching the first insulating film using the polycrystalline silicon film and the first polycrystalline silicon film as a mask to expose a part of the surface of the active region;
removing the second polycrystalline silicon film and then forming and etching a third polycrystalline silicon film to form the desired sidewall of the opening; Then, heat treatment is performed to form the conductive layer from the first polycrystalline silicon film to the active region through the third polycrystalline silicon film. The method is characterized in that it includes a step of diffusing a type impurity to form an impurity diffusion region of one conductivity type and electrically connecting the first polycrystalline silicon film and the active region, and , the negative conductivity type impurity diffusion region is used as a base contact region or a source region and a drain region.

By adopting this configuration, when manufacturing a bipolar semiconductor device, the formation of the base contact region, the formation of the lead electrode therefrom, and the formation of the base region and emitter region can be performed using self-alignment. Furthermore, in the case of manufacturing an MIS field effect semiconductor device, formation of source and drain regions, formation of lead electrodes therefrom, etc. can be performed by a self-alignment method.

Embodiment of the Invention FIGS. 4 to 16 are cross-sectional side views of essential parts of a bipolar semiconductor device at key points in the process for explaining an embodiment of the present invention. explain. still,
Here, for the sake of simplicity, the description will focus on the formation of the base region and emitter region that are relevant to the present invention.

Refer to FIG. 4 <11> By applying a selective oxidation method to the n-type silicon semiconductor layer 11A (active region) epitaxially grown on the
A field insulating film 12 made of silicon dioxide with a thickness of about 0.000 (person) is formed, and the field insulating film 12 separates the n-type silicon semiconductor layer 11A as an n-type collector layer of l element silver, making each one independent. In the bipolar semiconductor device of the present invention, unlike the conventional example explained with reference to FIGS. 1 and 2, the base contact region and the emitter region are not arranged in a plane, so The mold collector layer may be smaller than conventional ones.

However, although not shown in the figure, an n+ type buried layer as seen in FIGS. 1 and 2 is formed to enable the formation of a collector electrode.

(b) After removing the mask, such as silicon nitride (SisN4) JIQ, used when carrying out the selective oxidation method to expose the surface of the active region, a thermal oxidation method is applied to reduce the thickness to a thickness of, for example, 500 mm. ) is formed.

(C) Chemical vapor deposition.

Silicon nitride IIQ1 with a thickness of, for example, about 1000 (people) is applied by applying the ur deposition (CVD) method.
4 (first insulating film) is formed.

(d) A polycrystalline silicon film 15 (first polycrystalline silicon film 15) doped with boron (B), for example, about 1 x 10''(cm-'') by applying the same CVD method and having a thickness of, for example, about 5000 cm. A polycrystalline silicon film) is formed.

(e) Same < Thickness by applying CVD method, e.g. 300
0 [person] silicon dioxide film 16 (second insulating film)
form.

Refer to FIG. 5(f) After forming a suitable mask having an opening in the portion where the base region is to be formed, a side etching process with a small amount of side etching, such as reactive ion etching (reactive ion etching) is performed.
Using a ton etching (RIE) method, the silicon dioxide film 16 and the polycrystalline silicon film 15 are patterned to form an opening 15A. In addition, opening 15A
As the width a, for example, 1.5 [μm] may be selected.

By the way, in order to carry out this step, it is necessary to align the mask, but even if the alignment is slightly deviated, considering the structure of the bipolar semiconductor device according to the present invention, it is necessary to align the mask as shown in FIGS. 1 and 2. As with the conventional example explained above, there are few places where the base contact area and emitter area are crushed, so there is no problem, and if alignment is to be performed with the same degree of accuracy as in the conventional example, This means that fewer methods are required.

Refer to FIG. 6 (g) A thermal oxidation method is applied to form a silicon dioxide film having a thickness of, for example, about 3000 (people) on the polycrystalline silicon film 15 exposed in the opening 15A in the step (f). Note that this newly formed silicon dioxide film is continuous with the silicon dioxide film 16, so for convenience, it is indicated by the same symbol 16.

Referring to FIG. 7(h), a non-doped polycrystalline silicon film 17 (second polycrystalline silicon film) is formed by applying the CVD method.

The thickness of this polycrystalline silicon film 17 is as follows:
It is assumed that the silicon nitride film 14 exposed therein is sufficiently buried. Now, for example, opening 15A
If the width a (see Fig. 5) is 1.2 [μm] due to the formation of the silicon dioxide film 16, the thickness of the polycrystalline silicon film 17 is approximately 6000 [μm]. do.

See Figure 8 (1) Applying the RIE method, without forming a mask,
Etching of the polycrystalline silicon film 17 is continued until the silicon dioxide film 16 is exposed.

In this way, on the part where the base region is to be formed, that is,
Polycrystalline silicon film 17 remains only within opening 15A.

See Figure 90) As an etchant, for example, HzO(10)+HF
A wet etching method using (1) is applied to remove silicon dioxide 11A16.

Refer to FIG. 1O +klRIE method is applied to form
7 as a mask, the silicon nitride film 14 is etched, and then the silicon dioxide film 13 is etched by wet etching to form an opening 13A. expose a part of the surface.

See Figure 11 (1) As an etchant, for example, potassium hydroxide (
The polycrystalline silicon film 17 is etched and removed using a KOH solution.

In this case, the polycrystalline silicon film 17 is non-doped, and the polycrystalline silicon film 15 is doped with boron, so
There is a difference in etching rate of about 1:4O, and the polycrystalline silicon film 15 is hardly etched.

(See Figure 12) Applying the CVD method, a non-doped polycrystalline silicon film 1B (third polycrystalline silicon film) is deposited to a thickness of, for example, 30 mm.
Form to about 00 (persons).

Refer to FIG. 13 (the non-doped polycrystalline silicon film 18 is etched by applying the fllRIE method without forming a mask).

Since the RIE method has anisotropy, when the etching is performed, the non-doped polycrystalline silicon film 18 becomes the boron-doped polycrystalline silicon film 1 exposed in the opening 15A.
It remains only on the side wall of 5.

Refer to FIG. 14 (0) A thermal oxidation method is applied to oxidize the polycrystalline silicon films 15 and 18 to form a silicon dioxide film 19.

Depending on the heat treatment at this time, the n-type silicon semiconductor layer 11
With respect to A, boron is diffused from the boron-doped polycrystalline silicon film 15 through the polycrystalline silicon film 18, and a p+ type base contact region 20 is formed.

Refer to FIG. 15 1p) Apply the RIE method to etch and remove a portion of the silicon nitride film 14 exposed within the opening 15A.

(Q) Subsequently, a wet etching method is applied to etch and remove a portion of the silicon dioxide film 13.

(r) Applying an ion implantation method to the exposed n-type silicon semiconductor layer 11A, implanting boron ions at a dose of, for example, I x 10''[cm-''),
A heat treatment is performed to activate the boron ions, and a p-type base region 21 is formed.

Refer to FIG. 16 (by applying the SICVD method, a polycrystalline silicon film 22 doped with arsenic (As) is grown to a thickness of, for example, about 3000 μm).

(1) Applying photolithography technology, pattern the polycrystalline silicon film 22 to form an emitter electrode shape.

(The n+ type emitter region 23 is formed by applying the 01 heat treatment method and diffusing arsenic contained in the polycrystalline silicon film 22 into the base region 21.

(Vl Photolithography technology is applied to pattern the silicon dioxide film 19 to form electrode contact windows.

←) For example, a sputtering method is applied to form an aluminum (AN) film.

(x) Applying photolithography technology, the aluminum film is patterned to form a base electrode 24 and an emitter electrode 25.

As can be seen from the above description, in this embodiment, the mask process required for forming the base contact region, base region, emitter region, base extraction electrode, etc. is performed using the opening 15A described in connection with FIG. This is only the case when forming a position, and there is no need to provide a large positioning margin as in the conventional case.

Although the above description exemplifies the case where the present invention is applied to the manufacture of a bipolar semiconductor device, if the present invention is applied to the manufacture of a Mis field effect semiconductor device, it is possible to similarly obtain effects such as miniaturization. It is. However, in that case, both side walls of the opening 15A in the direction perpendicular to the plane of the paper in FIG. 5 need to be present on the field insulating film 12.

FIG. 17 is a plan view of a main part to show the pattern and position of the opening 15A when manufacturing a Mis field effect semiconductor device, and the same parts as those explained with reference to FIGS. 4 to 16 have the same symbols. This is the instruction.

As can be seen, sidewalls 26 and 26' of opening 15A are on field insulating film 12.

If this is not done, it will not be possible to divide the base contact region 20 described with reference to FIG. 14 and use one of them as a source region and the other as a drain region.

Incidentally, the pattern and position of the opening 15A in the case of manufacturing a bipolar semiconductor device are shown in FIG.
The same parts as those described with reference to FIGS. 4 to 17 are indicated by the same symbols.

As can be seen from the figure, since the opening 15A is formed in the active region, it is easily understood that when the base contact region 20 is formed therewith, it will be in a continuous pattern surrounding the opening 15A. .

Effects of the Invention In the method for manufacturing a semiconductor device according to the present invention, a first insulating film, a first polycrystalline silicon film containing a -conductivity type impurity, and a second insulating film are each sequentially formed on a silicon semiconductor substrate. forming an opening in the second insulating film and the first polycrystalline silicon film on a predetermined portion of the active region to expose a part of the surface of the first insulating film; Next, the first polycrystalline silicon film exposed as a sidewall in the opening is oxidized to form an insulating film continuous to the second insulating film, and then a second polycrystalline silicon film is formed to fill the opening. A silicon film is formed, and then the second insulating film and the insulating film connected thereto are removed, and then the second insulating film is removed.
By etching the first insulating film using the polycrystalline silicon film and the first polycrystalline silicon film as a mask, a part of the surface of the active region is exposed, and then the second polycrystalline silicon film is etched. removing the crystalline silicon film and then forming and etching a third polycrystalline silicon film deposited on the first polycrystalline silicon film forming the desired sidewalls of the opening; Then, heat treatment is performed to diffuse the - conductivity type impurity from the first polycrystalline silicon film into the active region through the third polycrystalline silicon film. The structure includes a step of forming an impurity diffusion region of one conductivity type and electrically connecting the first polycrystalline silicon film and the active region; The impurity diffusion region is used as a base contact region or a source region and a drain region.

By adopting such a configuration, when manufacturing a bipolar semiconductor device, the base contact region, base region, base extraction electrode, etc. can be formed using a self-alignment method with just one mask process. Furthermore, the emitter region can also be formed using a self-alignment method. In addition to reducing the size of the entire transistor, the base region is also reduced in size and the base resistance is reduced, thereby achieving even higher speeds.

Furthermore, when a Mis field-effect semiconductor device is manufactured, it can also be made smaller and have a short channel, and can operate at higher speeds than conventional devices.

[Brief explanation of drawings]

1 and 2 are cutaway side views of essential parts for explaining a conventional bipolar semiconductor device, and FIG. 3 shows the dimensional relationship when manufacturing the bipolar semiconductor device shown in FIGS. 1 and 2. 4 to 16 are cross-sectional side views of essential parts of a bipolar semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIGS. 17 and 18 are side views of an opening. 2A and 2B are plan views of main parts showing patterns and positions, respectively. In the figure, 11 is a p-type silicon semiconductor substrate, 11A
1 is an n-type silicon semiconductor layer (active region), 12 is a field insulating film, 13 is a silicon dioxide film, 13A is an opening, 1
4 is a silicon nitride film (first insulating film), 15 is a polycrystalline silicon film (first polycrystalline silicon film), 15A is an opening,
IC is a silicon dioxide film (second insulating film), 17 is a polycrystalline silicon film (second polycrystalline silicon film), 18 is a polycrystalline silicon film (third polycrystalline silicon film), 19 is a silicon dioxide film , 20 is a p+ type base contact region,
21 is a p-type base region, 22 is a polycrystalline silicon film, 23
24 represents an n+ type emitter region, 24 represents a base electrode, and 25 represents an emitter electrode. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Figure 3 Figure 0 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 7 Figure 9 Figure 17 Figure 10 Figure 12 Figure 13 Figure 8 Figure 14 Figure 15 Figure 16 Figure 5

Claims (1)

[Claims] (1) A first insulating film, a first polycrystalline silicon film containing -conductivity type impurities, and a second polycrystalline silicon film on a silicon semiconductor substrate.
insulating films are sequentially formed, and then an opening is formed in the second insulating film and the first polycrystalline silicon film on a predetermined portion of the active region to close the first 1!1 edge. ]
A part of the surface thereof is exposed, and then the first polycrystalline silicon film exposed as a side wall in the opening is oxidized to form an insulating film continuous to the second insulating film, and then, A second polycrystalline silicon film is formed to fill the opening, and then the second C insulating film and the peripheral film connected thereto are removed to form the second polycrystalline silicon film and the first polycrystalline silicon film.
Using the polycrystalline silicon film as a mask, the first insulating film 4
etching to expose a portion of the surface dividing the active region, and then forming and etching the second crystalline silicon film to define the desired sidewalls of the opening. The active layer is removed from the first polycrystalline silicon film through the third polycrystalline silicon film by heat treatment. (2) a step of diffusing the - conductivity type impurity into the region to form a one conductivity type impurity diffusion region and electrically connecting the first polycrystalline silicon film and the active region; 2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity diffusion region serves as a base contact region. A method for manufacturing a semiconductor device according to claim 1.