JPS6021620A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS6021620A
JPS6021620A JP58130021A JP13002183A JPS6021620A JP S6021620 A JPS6021620 A JP S6021620A JP 58130021 A JP58130021 A JP 58130021A JP 13002183 A JP13002183 A JP 13002183A JP S6021620 A JPS6021620 A JP S6021620A
Authority
JP
Japan
Prior art keywords
switching
drain
load
resistor
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58130021A
Other languages
Japanese (ja)
Inventor
Kenichi Kikuchi
健一 菊地
Tomihiro Suzuki
富博 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP58130021A priority Critical patent/JPS6021620A/en
Publication of JPS6021620A publication Critical patent/JPS6021620A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To improve the switching speed by using a resistor as a load of a switching transistor (TR) in a basic circuit using a normally-on field effect TR. CONSTITUTION:The resistor RL is used as a load of the switching TRQ1, the value of the resistor RL is decreased sufficiently, a power supply voltage Vdd is increased sufficiently and a point P of a load line is set within the saturating region of the drain characteristic of the switching TRQ1. When the field effect REQ1 is in the saturating region, the drain end of a depletion layer under a gate electrode spreads to the entire thickness of the operating layer. Thus, a capacitance between the drain and gate is remarkably small in the saturation region and the switching speed is improved.

Description

【発明の詳細な説明】 〔背景技術〕 集積回路の動作速度を向」ニする手段の一つとして、半
導体旧材にＧａＡｓを用いた電界効果トランジスタによ
って集積回路を構成することが、広く研究されている。[Detailed Description of the Invention] [Background Art] As one means of increasing the operating speed of integrated circuits, the construction of integrated circuits using field effect transistors using GaAs as the old semiconductor material has been widely studied. ing.

ノーマリオン型の電界効果トランジスタを用いた場合の
基本回路としては図−１のようなものが用いられている
。ここでＱｌはスイッチングトランジスタ、Ｑ２は負荷
トランジスタである。The basic circuit shown in Figure 1 is used when normally-on field effect transistors are used. Here, Ql is a switching transistor and Q2 is a load transistor.

このときの負荷特性は図−２に示すごとくなり、トラン
ジスタＱ０のドレイン電圧はほぼ０■からほぼ電源電圧
までの間の値を変動する。トランジスタＱ１のドレイン
・ゲート間のキャパシタンスはドレイン電圧がゲート電
圧に比較して充分高い値であれば、充分に小さな値とな
るが、従来の方法では、ドレイン電圧は０■近くまでの
値をとるため、ドレイン・ゲート間容量は比較的大きな
値となり、これがスイッチング速度の一つの制約となっ
ていた。The load characteristics at this time are as shown in FIG. 2, and the drain voltage of the transistor Q0 fluctuates between approximately 0 and approximately the power supply voltage. The capacitance between the drain and gate of transistor Q1 will be a sufficiently small value if the drain voltage is sufficiently high compared to the gate voltage, but in the conventional method, the drain voltage takes a value close to 0. Therefore, the capacitance between the drain and gate becomes a relatively large value, which is one of the constraints on the switching speed.

〔発明の開示〕[Disclosure of the invention]

本発明は上記の困難を克服するためになされたものであ
る。The present invention has been made to overcome the above-mentioned difficulties.

以下本発明を一実施例につき説明する。The present invention will be explained below with reference to one embodiment.

図−３は本発明による基本回路である。図−４・は基本
回路のトランジスタＱ１の負荷特性である。Figure 3 shows a basic circuit according to the present invention. Figure 4 shows the load characteristics of the transistor Q1 in the basic circuit.

図−３に示したようにスイノチングトランジスタＱ、の
負荷として図−１の負荷トランジスタＱ、の替りに、抵
抗Ｒ５を用いる。この時、図−４に示したごと＜、ＲＬ
の値を充分小さくし、電源電圧Ｖｄｄを充分に大きな値
とすることによって、Ｑｌがオンとなったときのドレイ
ン電圧が充分に大きく、図−４・に示した負荷線のＰ点
が、スイッチングトランジスタＱ１のＦレイン特性の飽
和領域内となるように設定する。As shown in FIG. 3, a resistor R5 is used as a load for the switching transistor Q in place of the load transistor Q in FIG. At this time, as shown in Figure 4, <, RL
By making the value of Vdd sufficiently small and the power supply voltage Vdd sufficiently large, the drain voltage when Ql is turned on is sufficiently large, and the point P of the load line shown in Figure 4 is at the switching point. It is set so that it is within the saturation region of the F-rain characteristic of the transistor Q1.

本発明の回路においては、電界効果トランジスタＱ１が
飽和領域にあるときは、ゲート電極下の空乏層のドレイ
ン端は、動作層全体厚さまで拡っているため、飽和領域
ではドレイン・ゲート間キャパシタンスは、トランジス
タが非飽和領域にあるときに比較して著しく小さいもの
となり、ｈ〜１７゜程度となる。そのためスイッチング
速度は著しく向上される。In the circuit of the present invention, when the field effect transistor Q1 is in the saturation region, the drain end of the depletion layer under the gate electrode extends to the entire thickness of the active layer, so in the saturation region, the drain-gate capacitance is , which is significantly smaller than when the transistor is in the non-saturation region, and is approximately h~17°. Therefore, the switching speed is significantly improved.

〔産業上の利用可能性〕[Industrial applicability]

以上述べたように本発明は集積回路のスイッチング速度
を著しく改善するものであり産業上有用なものである。As described above, the present invention significantly improves the switching speed of integrated circuits and is industrially useful.

【図面の簡単な説明】[Brief explanation of drawings]

図−１及び図−２は従来のノーマリオン型電界効果を用
いた時の基本回路及びそれを用いた時のＶｃｌ−１ｄ　
特性を示す図である。図−３及び図−４・は本発明の基
本回路及びそれを用いた時のＶｄ−１ｄ特性を示す図で
ある。 代理人　弁理士　上　代　哲　司　ｅ Ｓｆ 図−１ ｄ 図−２ 図−３ ｄ 図−４Figure-1 and Figure-2 show the basic circuit when using the conventional normally-on field effect and the Vcl-1d when using it.
FIG. 3 is a diagram showing characteristics. FIG. 3 and FIG. 4 are diagrams showing the basic circuit of the present invention and the Vd-1d characteristics when using the same. Agent Patent Attorney Tetsuji Udai e Sf Figure-1 d Figure-2 Figure-3 d Figure-4

Claims (1)

【特許請求の範囲】[Claims] （１）スイッチング用電界効果トランジスタのドレイン
と電源との間に抵抗を接続して負荷となし、ドレイン出
力端にはレベルシフト回路が接続された回路において負
荷抵抗と電源電圧との値をスイッチング用電界効果ｌ・
ランジスクが常に飽和領域であるように設定したことを
特徴とする基本回路本発明は集積回路の動作速度向上に
関するものである。(1) A resistor is connected between the drain of the field effect transistor for switching and the power supply as a load, and a level shift circuit is connected to the drain output terminal.The value of the load resistance and the power supply voltage is used for switching. Electric field effect
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improving the operating speed of integrated circuits.
JP58130021A 1983-07-16 1983-07-16 Integrated circuit Pending JPS6021620A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58130021A JPS6021620A (en) 1983-07-16 1983-07-16 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58130021A JPS6021620A (en) 1983-07-16 1983-07-16 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS6021620A true JPS6021620A (en) 1985-02-04

Family

ID=15024200

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58130021A Pending JPS6021620A (en) 1983-07-16 1983-07-16 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS6021620A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0400372A2 (en) * 1989-05-30 1990-12-05 Siemens Aktiengesellschaft CMOS/ECL converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0400372A2 (en) * 1989-05-30 1990-12-05 Siemens Aktiengesellschaft CMOS/ECL converter

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