JPS6021554A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent current breakdown by a method wherein the width of contact of the first semiconductor layer with the second semiconductor layer is formed larger than that of either one semiconductor layer of the first and second ones. CONSTITUTION:The rectangular region of the second semiconductor layer 14 formed under a contact hole 11 is formed by extension from under a polycrystalline Si layer 8 toward the first conductive layer 13. The width W2 of a region 15 etched at the time of etching the polycrystalline Si layer on the second semiconductor layer 14 is formed sufficiently larger than W1. This increase of area causes the decrease of resistance of the region 14 and has the strong property to current breakdown. Therefore, this device is endurable to the current breakdown when an over current is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a technique that is effective for improving the breakdown voltage of a semiconductor device.

[Background technology]

The gate barrier circuit, which exists between the bonding pad and the input stage circuit, consists of a resistor and a diode to clamp unexpected overcurrent.

This resistor is made of a semiconductor layer of a conductivity type opposite to that of the semiconductor substrate, and is in ohmic contact with aluminum wiring extending from the bonding pad through a contact hole around the bonding pad. The conductor layer resistor, which has a conductivity type opposite to that of the substrate, is formed with the same concentration from this contact hole part to the other end, so that the patterned semiconductor layer directly under the contact hole has other regions of the semiconductor layer. Higher voltage is applied compared to . Therefore, when a high voltage is temporarily applied, only the skeleton semiconductor layer under the contact hole is voltage-destructed, and the device cannot be regenerated.

As a technique for preventing voltage breakdown of the semiconductor layer under the contact hole, a polycrystalline silicon layer containing impurities is provided in the contact hole portion, impurities are introduced into the substrate from the polycrystalline silicon layer, and the impurity is placed under the contact hole at a low concentration. The present inventor has developed a method for forming a second semiconductor layer consisting of a diffusion layer. By forming a second semiconductor layer with a low impurity concentration under the contact hole, the impurity concentration gradient under the contact hole becomes gentle, increasing the breakdown voltage and preventing voltage breakdown of the semiconductor layer directly under the contact hole. There are advantages. This technique will be specifically explained using FIGS. 1 and 2.

FIG. 1 is a circuit diagram schematically showing a portion of a gate protection circuit and an input stage circuit extending from a bonding pad.

The wiring 2 extending from the bonding pad has a conductivity 1 opposite to that of the board.
is connected to a resistor 3 made of a type of semiconductor layer, and the resistor 3 extends to an input stage circuit 5.

FIG. 2 shows a contact hole portion where the wiring 2 and the resistor 3 are bonded. m 21MI (a) is a plan view, Fig. 2 (b) u Fig. 2 (true) sectional view along line AA',
FIG. 2(a) is a sectional view taken along line BB' in FIG. 2(a). The first semiconductor I@13 has a conductivity type opposite to that of the P-type substrate.
, and the second semiconductor layer 14 functions as the resistor 3 shown in FIG. ) is formed by thermal diffusion into the substrate. In this structure, the input signal that is not inputted from the aluminum wiring 10 (corresponding to the wiring 2 in FIG. 1) passes through the polycrystalline silicon layer 8 and then passes through the second semiconductor layer 14.
However, since the second semiconductor layer 14 has a low concentration, the breakdown Φ down voltage increases, and voltage breakdown at the contact hole portion is less likely to occur, which is advantageous.

However, the inventor has revealed that when this method is used to prevent voltage breakdown of the protective resistor, it has the following serious drawbacks. The second semiconductor 14 having a low impurity concentration is formed as follows. A field insulating film 7 and a gate oxide film (not shown) are selectively formed, and a portion of the gate oxide film is removed by etching the oxide film inside the two-dot chain line. As a result, a portion of the semiconductor substrate is exposed inside the two-dot chain line. In this state, a polycrystalline silicon layer into which impurities have been introduced is formed over the entire surface 2, and the impurities in the polycrystalline silicon layer are introduced into the exposed portion of the substrate by heat treatment. However, when the polycrystalline silicon layer is etched into a desired pattern after forming the second semiconductor layer 14, during this etching process, the areas where the gate insulating film and the field insulating film 7 are likely to exist and are etched are etched. In a region where no polycrystalline silicon layer remains, that is, in FIG. 2(a), the silicon substrate in the region indicated by the diagonal line between the two-dot chain line and the polycrystalline silicon IWt 8 is also etched. Therefore, in the second semiconductor N114, as shown in FIG.
2 is formed. After etching the polycrystalline silicon l-, for example, arsenic is implanted to form the first conductor layer 13 connected to the second conductor layer 14.

The second conductor layer 14 and the first semiconductor layer 13 overlap,
The formed groove 12 is physically weak and causes current breakdown when excessive current is input. In particular, in the region $14m having the same width as the formation width of the first semiconductor layer 13, the first semiconductor layer 13 formed by implanting arsenic is separated as shown in the figure, and only the low concentration m2 semiconductor layer remains. Current concentration occurs and it becomes easy to break down.

As described above, the technology that prevents voltage breakdown of the protective resistor has a serious drawback in that current breakdown is likely to occur.

[Purpose of the invention]

An object of the present invention is to provide a structure of a semiconductor impurity layer that can withstand high current to prevent current breakdown.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

A first semiconductor layer having a conductivity type opposite to that of the semiconductor substrate, and a second semiconductor layer connected to the first semiconductor layer formed using a deposited layer, for example, a polycrystalline silicon layer as a mask, selectively formed on the first semiconductor layer. When a series of semiconductor layers are formed by This prevents current breakdown.

〔Example〕

FIG. 3(a) is a plan view of a contact hole at the end of a protective resistor according to the present invention;
A sectional view taken along the line c' in FIG. 3 (cl is a sectional view taken along the line DD' in FIG. 3 (at).

Similar to Fig. 2, Fig. 3 shows the bonding pad 1 of Fig. 1.
It shows a contact portion where a wiring 2 (corresponding to the aluminum wiring 10 in FIG. 3) extending from the bottom and a protective resistor 3 are joined. The resistor 3 in FIG. 1 is the first semiconductor layer 13 in FIG. 3(b). and a second semiconductor layer 14. 1st
The four diodes shown in the figure are formed by the PNN contact pressure between the P- type silicon substrate 6 and the semiconductor layers 13 and 14 shown in FIG. 3(b). On the extension of the first semiconductor layer 13, a first
There is an input role 5 in the figure.

Figure 3 is different from Figure 2, 21st! The first semiconductor layer 13 and the second conductor layer 14 shown by diagonal lines in ¥4Hal overlap, and the region 12 that is simultaneously etched when forming the polycrystalline silicon layer 8 by etching is a wider area 15 (in the figure, the diagonally shaded region It is located in this area, which is formed as a 1-area). In FIG. 2 (al), the surface of the region 12 where the first semiconductor layer 13 and the second semiconductor layer 14 overlap is etched together with the polycrystalline silicon layer to be removed during the etching process for forming the polycrystalline silicon layer. This $12 is the width W of the first semiconductor layer 13.

Because it has the same width W1 as the first semiconductor layer 13, it is more susceptible to current destruction than other regions of the first semiconductor layer 13, and is easily destroyed when a temporary high current flows in. . In the present invention shown in FIG. 3(,), the rectangular region of the second conductor layer 14 formed under the contact hole 11 is extended from under the polycrystalline silicon layer 8 toward the first conductive layer 13. The width W of the region 15 formed and etched when etching the polycrystalline silicon dove on the second semiconductor layer 14 is Wl.
Yosho is also formed sufficiently large. The increase in area of the region 12 shown in FIG. 2(a) reduces the resistance of the region 14a, making it resistant to current breakdown.

Therefore, it can withstand current breakdown when excessive current is input.

The method for manufacturing region #215 where the wide first semiconductor layer 13 and second semiconductor layer 14 overlap, which is the key point of the present invention, is as follows.

First, a P-type silicon substrate 6 is deposited, and a field insulating film 7 made of silicon oxide is formed on the substrate. The field insulating film 7 in the region where the contact hole 11 is to be formed, one side of the region defined by the field insulating film 7, one side of the polycrystalline silicon layer 8 to be formed later, and the gate oxide film to be described later are removed.

The shape W is made so that it extends beyond one side of the rectangular region.

In FIG. 3 (at), the area surrounded by dotted lines is the part where the surface of the substrate is exposed in sections by the field insulating film 7. After forming the field insulating film 7, the thin gate oxide film is exposed. The gate oxide film on the region where the polycrystalline silicon layer 8f is formed on the silicon substrate (the region demarcated by the two-dot line a in FIG. 3) is replaced with an unnecessary gate oxide film not shown in the figure. At the same time, it is removed. After this, a polycrystalline silicon layer is formed on the entire surface, and in order to obtain relatively high conductivity, for example, phosphorus (p) 1- is introduced. The phosphorus (p) introduced into this polycrystalline silicon layer is Area where gate oxide film and field insulating film are present (Fig. 3)
Diffusion is introduced from the polycrystalline silicon layer into the region surrounded by the dotted line and the two-dot chain line (in the 凾). The polycrystalline silicon layer forms gates, etc., and is etched as shown in FIG. 3 (bl) at the end of the protective resistor shown in FIG. However, in Figure 2 (at area [compared to 12, 3rd area
The area of the region 15 in the figure (at) is large, especially in the direction perpendicular to the current flow direction, so the resistance and current density are reduced and current breakdown can be prevented. After this, the polycrystalline silicon layer 18 is masked. As, the first semiconductor following the second semiconductor #14
The semiconductor layer 13 is formed by implanting arsenic or the like.

Then, a first passivation film 9 made of a phosphosilicate glass film and an aluminum wiring 11 are formed to form a waist-retaining resistance portion connected to the bonding pad.

〔effect〕

When the two semiconductor layers overlap and the deposited layer on one semiconductor layer is etched, the width of the etched region is wide, which reduces the resistance and current density of the region and makes it resistant to current breakdown. have a property. In other words, the breakdown voltage is improved because the cross-sectional area of the plane perpendicular to the current flow direction is increased. Therefore, it is possible to prevent damage caused by temporary large currents caused by static electricity or the like.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, the P- type silicon substrate may be an N- type silicon substrate, and in this case, the cod impurity layer is a P+ impurity layer, which does not impair the effects of the present invention. The first layer of silicon silicate glass film may be formed from a silicon oxide layer.

[Application field]

In the above description, we will mainly explain the case where the invention made by the present inventor is applied to the gate protection circuit of a semiconductor device, which is the background field of application. It can be applied to snow making having a series of semiconductor layers formed by connecting semiconductor layers.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of the gate protection circuit extending from the bonding pad, Figure 2 (, ) is a plan view of the contact hole at the end of the protection resistor, and Figure 2 (b) is the same as Figure 2 (a). FIG. 2(c) is a sectional view taken along line AA' of FIG. Plan view, Figure 3 (bl is a sectional view taken along line cc' in Figure 3(a), Figure 3 (cl is a sectional view taken along line DD' in Figure 3(al). 1. ...Ponding pad, 2...Aluminum wiring extending from the bonding pad to the protective resistor, 3.
...Main! I resistor, 4... Diode formed by the substrate and resistor, 5... Input stage circuit, 6... P-type silicon semiconductor substrate, 7... Film with a feel from silicon oxide , 8... Polycrystalline silicon layer, 9... First batch film made of phosphorus silicate glass film, 1
0... Aluminum wiring layer, 11... Contact hole, 12... First semiconductor layer 13 and second semiconductor layer 14
13... a first semiconductor layer formed using the polycrystalline silicon layer 8 as a mask; 14... an impurity contained in the polycrystalline silicon layer 8; a second semiconductor layer formed by penetrating into the substrate, 14a...area where current breakdown particularly occurs, 15...area of the above 12 improved by the present invention; Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. A first region in which a semiconductor region of a second conductivity type formed on a semiconductor substrate of a first conductivity type has a first width, and a second width larger than the width of the w connected to the first region; the second with
A polycrystalline silicon layer is formed by direct liquid deposition on a surface portion of the second region excluding a portion connected to the first region W, and the polycrystalline silicon layer is formed by direct liquid contact with the second region.
A semiconductor device characterized by being connected to an aluminum layer on a region ψ.