JP3148979B2 - ESD protection circuit and method of forming the circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an electrostatic discharge (ES) which causes an electrostatic breakdown.
The present invention relates to a circuit for protecting a device from D) and a method for forming the circuit.

[0002] In general, device destruction due to electrostatic discharge can be thought of as destruction of one of a wiring film and an oxide film, but is generally considered to be thermal destruction. What is joint failure?
The application of static electricity causes a current to flow through the junction, thereby increasing the temperature and lowering the resistance of the junction, causing thermal runaway, and the pn junction is partially melted and destroyed. Wiring film destruction is a defect in which the wiring of an aluminum (Al) film is melted and disconnected due to a thermal cause, or is bridged by the melted Al. Therefore, a protection circuit is usually formed so that the internal circuit is not destroyed by electrostatic discharge. However, in an ESD protection circuit using an NPN bipolar transistor, when the well bias is connected to the ground line Vss through a low resistance, There is a problem that the gain of the NPN bipolar transistor increases and latch-up occurs.

[0003] The following describes the prior art ES based on the attached drawings.
The D protection circuit will be described. FIG. 1 is a layout diagram showing a conventional ESD protection circuit, and FIG. 2 is a sectional view taken along the line II of FIG. As shown in FIGS. 1 and 2, a p-well region 12 is formed at a predetermined depth in an n-type semiconductor substrate 11, and the n-type semiconductor substrate 11 having the p-well region 12 is formed. A field oxide film 13 is formed in an element isolation region
Are formed. N-type first and second impurity diffusion regions 14 and 15 are formed in a slender and parallel manner with a gap in an active region defined by the field oxide film 13,
A p-type impurity diffusion region 16 of the internal circuit is formed at a position away from the first and second impurity diffusion regions 14 and 15. A pad 17 for receiving an input signal is formed to be connected to the first impurity diffusion region 14, and a ground line Vss18 is formed to connect the second impurity diffusion region 15 to the p-type impurity diffusion region 16. Therefore, when a negative input signal is applied via the pad 17, the N-type first impurity diffusion region 14 becomes the emitter, the P-well region 12 becomes the base,
A bipolar transistor in which the N-type second impurity diffusion region 15 serves as a collector constitutes a potential difference of 0.7 V between the emitter and the base, whereby the bipolar transistor starts operating in the forward direction. And pad 1
7, when a positive input signal in the opposite direction is applied, coupling breakdown occurs from a portion adjacent to the pad, and the closer the pad 17 is, the higher the voltage of the base (P-well region) becomes, and
The closer to the s-line, the lower the voltage. Therefore, the voltage between the base and the emitter adjacent to the pad 17 becomes 0.7 V or more. As a result, the current is concentrated near the Vss line having a large voltage difference, and a portion where the current is concentrated is destroyed.

[0004] The conventional ESD protection circuit, as described above,
The contact for controlling the well bias is eliminated in the ESD protection circuit itself, and the p-well region 12 of the internal circuit is eliminated.
Is used to control the bias voltage of the NPN bipolar transistor.

[0005]

However, in this type of conventional ESD protection circuit, a part of the NPN bipolar transistor, that is, a part of the NPN bipolar transistor shown in FIG. Since the current is concentrated only on the C part, C
There was a problem that the part was destroyed first. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has been made to prevent a current concentration phenomenon from occurring in any part thereof.
It is an object to provide an SD protection circuit and a method of manufacturing the same.

[0006]

In order to achieve the above object, an ESD protection circuit according to the present invention comprises first and second conductive type first and second conductive type semiconductor substrates arranged at predetermined intervals in a semiconductor substrate of the first conductive type. 2
An impurity region is formed, and a third impurity region of the first conductivity type is formed so as to be adjacent to and surround the first and second impurity regions.

The ESD of the present invention having the above structure
In a method of manufacturing a protection circuit, first, second, and third element isolation films are formed on a surface of a semiconductor substrate of a first conductivity type, and between the first and second element isolation films and between the second and third elements. First and second impurity regions of two conductivity type are formed between the isolation films, and the first and third impurity regions are further formed.
A third impurity region of the first conductivity type is formed to extend from a side surface of the element isolation film where the first and second impurity regions are not formed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an ESD protection circuit according to an embodiment of the present invention and a method of forming the circuit will be described in detail with reference to the accompanying drawings. FIG. 3 is a layout diagram showing the ESD protection circuit of the present invention, and FIG. 4 is a sectional view taken along line II-II of FIG.
As shown in FIGS. 3 and 4, a p-well region 22 is formed at a predetermined depth from the surface of the n-type semiconductor substrate 21, and an elongate shape is formed at a predetermined interval on the surface of the p-well region 22. N-type first and second impurity diffusion regions 24 and 25
Are formed in parallel with the element isolation film 23 interposed therebetween. Then, the first and second impurity diffusion regions 24, 2
5, p-type guard ring region 26 is formed on the surface of semiconductor substrate 21 where p-well region 22 is formed. As shown in FIG. 4, the guard ring 26 is separated from the second impurity diffusion regions 24 and 25 by an element isolation film 23.
In isolation. Further, a p-type impurity diffusion region 27 of an internal circuit for controlling a bias of the p-well region 22 is formed at a position away from the first and second impurity diffusion regions 24 and 25. p-type guard ring region 26
-P-type well region 2 between silicon and p-type impurity diffusion region 27
An element isolation film 23 is also formed on the surface of the second element. In the p-type guard ring region 26, impurities are diffused to a higher concentration than in the p-well region 22. The pad 28 for receiving an input signal is formed in contact with the n-type first impurity diffusion region 24, and the ground line Vss29 is in contact with the n-type second impurity diffusion region 25 and the p-type impurity diffusion region 27. Is formed. With this configuration, a bipolar transistor is formed by the n-type first and second impurity diffusion regions 24 and 25 and the p-well region 22.

A method of manufacturing the ESD protection circuit according to the embodiment of the present invention configured as described above will be described below. Figures 5 and 6
FIG. 4 is a process cross-sectional view illustrating a method for forming the ESD protection circuit of the present embodiment. As shown in FIG. 5A, an n-type semiconductor substrate 2
1. A p-well region 22 is formed at a certain depth from the surface of the substrate 1. A field oxide film 23 is formed on the element isolation region on the surface of the n-type semiconductor substrate 21 on which the p-well region 22 is formed.
To form As shown in FIG.
After a photoresist is applied to the entire surface including No. 3, the photoresist PR1 is patterned by exposure and development steps. The patterning shape is the region 24 shown in FIG.
It goes without saying that it is 25. Next, using the patterned photoresist as a mask, n-type impurity ions are implanted into the entire surface to diffuse the n-type first and second impurity diffusion into the surface of the n-type semiconductor substrate 21 in which the p-well region 22 is formed. Regions 24 and 25 are formed.

[0010] As shown in FIG.
1 to remove the n-type first and second impurity diffusion regions 24,
After applying a photoresist PR2 to the entire surface of the n-type semiconductor substrate 21 including the photoresist 25, the photoresist PR2 is patterned by an exposure and development process. The patterning shape is the region of the guard ring 26 and the third impurity region 27 in FIG. Next, using the patterned photoresist PR2 as a mask, impurity ions are implanted into the entire surface, so that the first and second n-type first and second impurity diffusion regions 24 and 25 are surrounded.
The bias between the p-type guard ring region 26 and the p-well region 22 on the surface of the n-type semiconductor substrate 21 formed so as to extend from the periphery of the field oxide film 23 adjacent to the impurity diffusion regions 24 and 25. Is formed with the p-type impurity diffusion region 27 of the internal circuit for controlling the impurity concentration.

Then, as shown in FIG. 6D, the photoresist is removed, an interlayer insulating film (not shown) is formed on the entire surface of the n-type semiconductor substrate 21, and then a contact hole is formed at a necessary place. Then, a metal layer is formed, a photoresist (not shown) is applied on the metal layer, and the photoresist is patterned by exposure and development processes. Next, the metal layer is selectively patterned using the patterned photoresist as a mask to form a pad 28 connected to the n-type first impurity diffusion region 24, an n-type second impurity diffusion region 25, Type impurity diffusion region 2
7 is connected to the ground line 29.

[0012]

As described above, the ESD protection circuit and the method of forming the same according to the present invention employ a low-resistance guard ring around a transistor formed by the first and second impurity regions and the p-type well. Since the equipotential surface is formed to control the bias of the well of the adjacent circuit, it is possible to prevent the concentration of current regardless of the shape and position of the contact. Therefore, there is an effect that the transistor is efficiently protected.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a conventional ESD protection circuit.

FIG. 2 is a cross-sectional view showing a conventional ESD protection circuit on the line II in FIG. 1;

FIG. 3 is a layout diagram showing an ESD protection circuit according to the embodiment of the present invention.

FIG. 4 is a sectional view taken along line II-II of FIG. 3;

FIG. 5 is a process sectional view illustrating the method for forming the ESD protection circuit according to the embodiment of the present invention.

FIG. 6 is a sectional view showing a step of the method for forming the ESD protection circuit according to the embodiment of the present invention.

[Explanation of symbols]

21 n-type semiconductor substrate 22 p-well region 23 field oxide film 24 n-type first impurity diffusion region 25 n-type second impurity diffusion region 26 p-type guard ring region 27 p-type impurity diffusion region 28 pad 29 Ground line

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-151732 (JP, A) JP-A-5-129530 (JP, A) JP-A-60-167348 (JP, U) JP-A-3-167 21858 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/822 H01L 27/04

Claims (5)

(57) [Claims] A first conductive type semiconductor substrate; and a first conductive type semiconductor substrate formed at a predetermined depth in the first conductive type semiconductor substrate.
A second conductivity type wells, first having formed so as to be aligned at a predetermined interval in the well
Conductivity type first and second impurity regions, said first, third impurity regions of a second conductivity type formed in the well so as to surround them adjacent to the second impurity region, said first A pad connected to the first impurity region of the conductivity type; and a ground line connected to the second impurity region of the first conductivity type , wherein the ground line is separated from the first and second impurity regions.
Position and control the well bias
ESD connected to an internal circuit area
Protection circuit. Wherein said first, said web between the second impurity region
ESD protection circuit according to claim 1, characterized in that the surface of the Le further comprising a device isolation film. 3. The ESD protection circuit according to claim 1, further comprising an element isolation film on a surface of the well between the first and second impurity regions and the third impurity region. 4. A predetermined depth in a semiconductor substrate of the first conductivity type
The first, second, and second surfaces of the well of the second conductivity type formed in
Forming a third device isolation film, the first in the well, said a between the second device isolation layer second, first the first conductivity type between the third device isolation film, the second impurity forming a step of forming a region, the first, the first, third impurity region of the second conductivity type to extend from the side did not form a second impurity region of the third device isolation film, the pad and the second impurity region of the first conductivity type connected to the first impurity region of the first conductivity type, said first, second
At a position distant from the impurity region and in the well
Forming a ground line connected to an internal circuit region for controlling the ground. 5. The ESD protection circuit according to claim 4 , wherein an interlayer insulating film is formed between the second conductivity type well and the pad and the ground line. Production method.