JPS6021532A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6021532A
JPS6021532A JP12771183A JP12771183A JPS6021532A JP S6021532 A JPS6021532 A JP S6021532A JP 12771183 A JP12771183 A JP 12771183A JP 12771183 A JP12771183 A JP 12771183A JP S6021532 A JPS6021532 A JP S6021532A
Authority
JP
Japan
Prior art keywords
pellet
mount
substrate
gold
gold foil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12771183A
Other languages
Japanese (ja)
Inventor
Takayuki Okinaga
隆幸 沖永
Hiroshi Tate
館　宏
Kanji Otsuka
寛治 大塚
Masayuki Shirai
優之 白井
Ken Okuya
謙 奥谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP12771183A priority Critical patent/JPS6021532A/en
Publication of JPS6021532A publication Critical patent/JPS6021532A/en
Pending legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To improve bonding characteristic between a substrate and a pellet by foming a metal foil in such a size as larger than pellet size on a substrate. CONSTITUTION:A gold foil 12 in such a size as is larger than a pellet 1 is deposited on the surface of pellet mount 4 and the lower surface of pellet 1 where the Au plated layer is formed slidingly on the upper surface of gold foil 12 while the base 3 is heated. Thereby, an eutectic layer 14 of Au and silicon is formed between the pellet 1 and mount 4 and the pellet 1 is die-bonded to the mount 4. In this case, since the gold foil is flatened, air bubble does not easily enter the area between gold foil and silicon and the Au-Si eutectic layer 14 is wetted uniformly in the entire part up to the periphery of pellet. Accordingly, the pellet 1 is strictly bonded to the mount 4 of base 3 and reliability is improved.

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、半導体技術、特に、半導体ペレットをダイボ
ンディングする技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor technology, and in particular to a technology for die bonding semiconductor pellets.

［背景技術］ 半導体ペレットをセラミックパッケージ上あるいは、プ
ラスチックパッケージのタブリード（以下、これを基板
と称する）上に金箔を用いてダイポンディングすること
が知られている（たとえば日本マイクロエレクトロニク
ス協会編ＩＣ化実装技術Ｐ１００など）。この場合、金
はその表面が平坦でないため、接着時にペレットと下地
の基板との間に気泡が入り、金−シリコン共晶が均一に
形成されず、ペレットと基板との密着性が悪いという問
題が本発明者によって明らかにされた。[Background Art] It is known to die-bond a semiconductor pellet onto a ceramic package or onto a tab lead (hereinafter referred to as a substrate) of a plastic package using gold foil (for example, in IC Mounting, edited by the Japan Microelectronics Association). Technology P100, etc.). In this case, since the surface of gold is not flat, air bubbles enter between the pellet and the underlying substrate during adhesion, and the gold-silicon eutectic is not formed uniformly, resulting in poor adhesion between the pellet and the substrate. was revealed by the present inventor.

閏 また、金箔は、接着に干与しない金粉がペレットに付着
するという理由から半導体ペレ７）よりも小さく形成す
るため、ペレットと基板との接着領域は半導体ペレット
よりも小さく、上記問題と合わせて、より密着性が悪く
なるという問題が本発明者によって明らかにされた。特
に、この問題は、超大規模集積回路（ＶＬＳＩ）等を形
成された大きいサイズのペレットにおいて顕著になる傾
向がある。In addition, since gold foil is formed smaller than semiconductor pellets 7) because gold powder that does not affect adhesion adheres to the pellets, the adhesive area between the pellets and the substrate is smaller than that of semiconductor pellets. The inventor of the present invention has revealed that the adhesion becomes worse. In particular, this problem tends to become more pronounced in large-sized pellets formed into very large scale integrated circuits (VLSI) and the like.

［発明の目的］− 本発明の目的は、半導体ペレソｌ−と基板との接着性が
十分に確保できる半導体技術を提供することにある。[Object of the Invention] An object of the present invention is to provide a semiconductor technology that can ensure sufficient adhesion between the semiconductor Pelesol and the substrate.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

し発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。Summary of the Invention] A brief summary of typical inventions disclosed in this application is as follows.

すなわち、サイズがペレットサイズ以」二の金属箔を基
板上に形成してペレットをダイボンディングすることに
より、基板とペレットとの接着性を向上させるものであ
る。That is, the adhesion between the substrate and the pellet is improved by forming a metal foil with a size equal to or larger than the pellet size on the substrate and die-bonding the pellet.

［実施例］ 第１図は本発明の一実施例である半導体装置を示す縦断
面図、第２図、第３図および第４図はペレットボンディ
ング作業の各工程を示す各拡大部分縦断面図および斜視
図である。[Example] Fig. 1 is a vertical cross-sectional view showing a semiconductor device as an example of the present invention, and Figs. 2, 3, and 4 are enlarged partial vertical cross-sectional views showing each step of pellet bonding work. and a perspective view.

本実施例において、この半導体装置はＶ　Ｓ　Ｌ　Ｉが
形成されたシリコン基板からなるペレットｌを備えてお
り、このペレット１は複数列のビン配列を持ったパッケ
ージ２に、このパンケージ２のベース３にボンディング
されたうえで、気密封止されている。In this embodiment, this semiconductor device is equipped with a pellet 1 made of a silicon substrate on which V S L I is formed, and this pellet 1 is attached to a base 3 of this pan cage 2 in a package 2 having a plurality of rows of bins. It is bonded to and hermetically sealed.

パッケージ２のベース３はセラミック等の絶縁材料から
平板形状に形成され、その上面にはほぼ中央に複数の金
属層からなるペレットマウント４が、その周方に複数の
り−ド５がそれぞれ形成されている。ペレットマウント
４とリード５とは第２図に示されるように、タングステ
ン＜Ｗ）ペースト等を印刷されてなるメタライズ層６と
、メタライズ層６の表面のニッケル（Ｎｉ）メ・ツキＭ
７−と、Ｎｉメッキ層７表面の金（Ａｕ）メッキ層８と
から構成されている。ベース３の下面には、複数のピン
９が各リード５にそれぞれ電気的に接続されて突設され
ている。The base 3 of the package 2 is formed into a flat plate shape from an insulating material such as ceramic, and on its upper surface, a pellet mount 4 made of a plurality of metal layers is formed approximately in the center, and a plurality of leads 5 are formed around the periphery of the pellet mount 4. There is. As shown in FIG. 2, the pellet mount 4 and the lead 5 include a metallized layer 6 printed with tungsten<W) paste, etc., and a nickel (Ni) plated M on the surface of the metallized layer 6.
7-, and a gold (Au) plating layer 8 on the surface of the Ni plating layer 7. A plurality of pins 9 are electrically connected to each lead 5 and protrude from the lower surface of the base 3.

ペレットマウント４の上面には、ペレット１のサイズよ
りも大きいサイズの金箔１２が添着される。第２図に示
されるように、金箔１２をマウント４に載置してからロ
ーラ１３等を転勤させて圧着させると、金箔１２の作業
中の剥離が防止でき、さらに、金箔１２の長面が平坦化
される。Gold foil 12 having a size larger than the size of the pellet 1 is attached to the upper surface of the pellet mount 4. As shown in FIG. 2, by placing the gold leaf 12 on the mount 4 and then transferring the rollers 13 etc. to press it, it is possible to prevent the gold leaf 12 from peeling off during the work, and furthermore, the long side of the gold leaf 12 is Flattened.

ベース３を加熱しながら、第３図に示されるように１．
Ａｕメッキ層を形成されたペレット１下面を金箔１２の
上面に摺接させると、ペレット１とマウント４との間に
は、第４図に示されるように、Ａｕとシリコン（Ｓｉ）
との共晶層１４が形成され、ペレット１はマウント４に
グイボンディングされる。このとき、金箔はローラで平
坦化されているため、金箔とシリコンの間に気泡が入り
にくく、ペレット１と基板の間にはＡｕ−３ｉ共晶屓１
４が全体的にペレットの周辺部まで均一に濡れる。なお
、このときペレットの側面下部も濡れる。While heating the base 3, as shown in FIG.
When the bottom surface of the pellet 1 on which the Au plating layer is formed is brought into sliding contact with the top surface of the gold foil 12, Au and silicon (Si) are formed between the pellet 1 and the mount 4, as shown in FIG.
A eutectic layer 14 is formed, and the pellet 1 is firmly bonded to the mount 4. At this time, since the gold foil is flattened by a roller, it is difficult for air bubbles to enter between the gold foil and the silicon, and the Au-3i eutectic layer 1 is placed between the pellet 1 and the substrate.
4 is evenly wetted to the entire periphery of the pellet. In addition, at this time, the lower side of the pellet also gets wet.

したがって、ペレットｌはベース３のマウント４に強固
にボンディングされ、その信頼性は良好になる。Therefore, the pellet 1 is firmly bonded to the mount 4 of the base 3, and its reliability is improved.

さらに、金箔１２がペレット側面より遠←離れている部
分においても、ペレットとマウンド表面を移動させて接
着させるため、シリコンと下地の金Ｎ８と化合し、実質
的に飛散し易い金箔はなくなる。したがって、金箔の飛
散による不良の発生をふせぐことができる。Furthermore, even in the part where the gold foil 12 is far away from the side surface of the pellet, the pellet and the mound surface are moved and bonded, so that the silicon and the underlying gold N8 are combined, and the gold foil that easily scatters is virtually eliminated. Therefore, it is possible to prevent defects caused by scattering of gold foil.

たとえば、第５図に示されるように、ペレット１のサイ
ズよりも小さい金箔１５を用いて、ペレット１がマウン
ト４上にボンディングされ、ペレット１の下面全体に形
成されなかったり、ボイドが形成される等接着不足が発
生した場合、ペレットｌの接着することがなかった箇所
にクランク１６が発生する等の障害が起こる。この障害
はペレットｌのサイズが大きいときに顕著になる傾向が
ある。これは次のような理由によると考えられる。For example, as shown in FIG. 5, the pellet 1 is bonded onto the mount 4 using a gold foil 15 smaller than the size of the pellet 1, and the entire lower surface of the pellet 1 is not formed or a void is formed. If insufficient adhesion occurs, problems such as cranks 16 will occur where the pellets 1 were not adhered. This problem tends to become more pronounced when the size of the pellet l is large. This is thought to be due to the following reasons.

大きいサイズのペレットは周辺部が接着しにくい。周辺
部の歪量は大口径化に比例して大きくなる。したがって
、周辺部に接着不足の境界線が発生すると、拡大された
歪による応力がその境界線に集中するため、クラック１
６が発生される。Large pellets have difficulty adhering around the edges. The amount of distortion in the peripheral area increases in proportion to the increase in diameter. Therefore, if a boundary line with insufficient adhesion occurs in the periphery, stress due to expanded strain will concentrate on that boundary line, resulting in a crack.
6 is generated.

前述のように、ペレット１の下面全体に均一にＡｕ−３
ｉ共晶層１４が形成されている場合には、濡れ不足の境
界線が発生することがないので、万一、大サイズのペレ
ット１が歪変形したとしても、応力築すゴが発生するこ
とは未然に回避され、したがって、クラック発生等の障
害が起こるおそれは全くない。As mentioned above, Au-3 is uniformly distributed over the entire lower surface of pellet 1.
If the eutectic layer 14 is formed, there will be no boundary line due to insufficient wetting, so even if the large pellet 1 is distorted, stress-building particles will not occur. Therefore, there is no risk of problems such as cracks occurring.

ペレット１がボンディングされたベース３上には、セラ
ミック等の絶縁材料から断面凹字形状に形成されたキャ
ップ１０がガラス等の封止材層１１を挟設されて被せら
れる。このようにして、ペレット１がパッケージ２によ
り気密封止される。A cap 10 made of an insulating material such as ceramic and having a concave cross section is placed over the base 3 to which the pellet 1 is bonded, with a sealing material layer 11 such as glass sandwiched therebetween. In this way, the pellet 1 is hermetically sealed by the package 2.

［効果］ （１）、ペレットを基板上にペレソ］・サイズ以上のサ
イズを有する金属箔によってダイボンディングすること
により、ペレットの下面全体をダイボンディング層に濡
れさせることができるため、クラソ７゛イ ク発生等濡れ不足による障害が回避でき、吐ト〒奈ボン
ディングにつき信頼性の高い半導体装置が得られる。[Effects] (1) By die-bonding the pellet with a metal foil having a size larger than that of the pellet on the substrate, the entire bottom surface of the pellet can be wetted with the die-bonding layer, so it is possible to wet the entire bottom surface of the pellet with the die-bonding layer. Problems caused by insufficient wetting, such as generation, can be avoided, and a highly reliable semiconductor device can be obtained with respect to the adhesive bonding.

（２）、金属箔として金箔を用いると、金−シリコン共
晶層が形成されるため、信頼性の高いボンディング性が
得られる。(2) When gold foil is used as the metal foil, a gold-silicon eutectic layer is formed, resulting in highly reliable bonding.

（３）、ペレットが接着する以外のマウント１恰金箔は
、ペレットと接着する際、ペレットをマウント金面上を
移動させるので、同様に金−シリコン共晶ができ金箔の
飛散が生じない。(3) When adhering the gold foil to the pellet, the mount 1 moves the pellet over the surface of the mount gold foil, so a gold-silicon eutectic is formed in the same way, and the gold foil does not scatter.

（４）、金箔の表面をローラで平坦化することによって
、ペレットをスクラブしたときに均一に濡れ金−シリコ
ン共晶が形成されペレットボンディングの信頼性をさら
に高められる。(4) By flattening the surface of the gold foil with a roller, when the pellet is scrubbed, a wet gold-silicon eutectic is formed uniformly, further improving the reliability of pellet bonding.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.

たとえは、ペレットボンディングされる基板はセラミッ
ク基板に限らず、リードフレーム等であってもよく、ボ
ンディング媒体としての金属箔も金箔に限らない。パッ
ケージの構造等に何ら限定がないことはいうまでもない
。For example, the substrate to be pellet-bonded is not limited to a ceramic substrate, but may be a lead frame, etc., and the metal foil used as a bonding medium is not limited to gold foil. Needless to say, there are no limitations on the structure of the package.

また、ペレットマウント４の材料はモリブデン層６、ニ
ッケルメッキ層７、銅メッキ層８に限られるものでなく
、上層の金属箔と合金可能なものであればなんでもよい
。たとえば、アルミニウム層でもよく、この場合、金属
箔が金箔であるとシリコン、金およびアルミニウムの合
金が形成される。Further, the material of the pellet mount 4 is not limited to the molybdenum layer 6, the nickel plating layer 7, and the copper plating layer 8, but any material may be used as long as it can be alloyed with the upper layer metal foil. For example, it may be an aluminum layer, in which case if the metal foil is gold foil, an alloy of silicon, gold and aluminum is formed.

【図面の簡単な説明】 第１図は本発明の一実施例を示す縦断面図、第２図、第
３図および第４図はペレットボンディング作業の各工程
を示す拡大部分断面図、斜視図および拡大部分断面図、 第５図は作用を説明するための拡大部分断面図である。 １・・・ペレット、２・・・パッケージ、３・・・ベー
ス、４・・・ペレットマウント、５・・・リード、６・
・・メタライズ層、７・・・Ｎｉメッキ層、８・・・Ａ
ｕメッキ層、９・・・ピン、ＩＯ・・・キャップ、１１
・・・封止材層、１２・・・金箔、１３・・・ローラ、
１４・・・Ａｕ−３ｉ共晶、１５・・・小サイズの金箔
、１６・・・クラック。 第　１　図 第　３　図 、♀ 第　４　図 グ 第　５　図 小平市上水本町１４５０番地株式会 社日立製作所デバイス開発セン タ内 ■出　願　人　株式会社日立製作所 東京都千代田区丸の内−丁目５ 番１号[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a longitudinal sectional view showing one embodiment of the present invention, and FIGS. 2, 3, and 4 are enlarged partial sectional views and perspective views showing each step of pellet bonding work. and an enlarged partial sectional view; FIG. 5 is an enlarged partial sectional view for explaining the operation. 1... Pellet, 2... Package, 3... Base, 4... Pellet mount, 5... Lead, 6...
...Metallized layer, 7...Ni plating layer, 8...A
u plating layer, 9... pin, IO... cap, 11
... Sealing material layer, 12... Gold foil, 13... Roller,
14...Au-3i eutectic, 15...Small gold foil, 16...Crack. Figure 1 Figure 3, ♀ Figure 4 Figure 5 Inside Hitachi, Ltd. Device Development Center, 1450 Josui Honmachi, Kodaira-shi Applicant Hitachi Ltd. 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo

Claims (1)

【特許請求の範囲】 １、　”゛′導体ペレットを付着する パンケージの基板上にペレットの大きさ以上の大きさを
有する金属シリコン共晶領域があり、前記金属シリコン
共晶によって半導体ペレットが基板に接着されであるこ
とを特徴とする半導体装置。 ２、金属シリコン共晶が、金シリコン共晶であることを
特徴とする特許請求の範囲第１項記載の半導体装置。 ３、基板が、セラミック基板であることを特徴とする特
許請求の範囲第１項記載の半導体装置。 ４、基板がタブリードであることを特徴とする特許請求
の範囲第１項記載の半導体装置。[Claims] 1. There is a metal-silicon eutectic region having a size larger than the size of the pellet on the substrate of the pancage to which the conductor pellet is attached, and the metal-silicon eutectic allows the semiconductor pellet to adhere to the substrate. 2. The semiconductor device according to claim 1, wherein the metal-silicon eutectic is gold-silicon eutectic. 3. The substrate is a ceramic substrate. 4. The semiconductor device according to claim 1, characterized in that the substrate is a tab lead.
JP12771183A 1983-07-15 1983-07-15 Semiconductor device Pending JPS6021532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12771183A JPS6021532A (en) 1983-07-15 1983-07-15 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12771183A JPS6021532A (en) 1983-07-15 1983-07-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6021532A true JPS6021532A (en) 1985-02-02

Family

ID=14966814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12771183A Pending JPS6021532A (en) 1983-07-15 1983-07-15 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6021532A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201286A (en) * 2006-01-27 2007-08-09 Kyocera Corp Surface-mounting module, and method of manufacturing same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5149681A (en) * 1974-10-26 1976-04-30 Narumi China Corp Handotaisoshino tosaihoho

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5149681A (en) * 1974-10-26 1976-04-30 Narumi China Corp Handotaisoshino tosaihoho

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007201286A (en) * 2006-01-27 2007-08-09 Kyocera Corp Surface-mounting module, and method of manufacturing same

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