JPS60214140A - Waveform shaping device - Google Patents

Abstract

PURPOSE:To apply waveform shaping to input signals of both positive/negative logic states by retarding an input sampling data by one sample time and confirm ing the presence of coincidence between the data before one sample and the sampling data to apply processing. CONSTITUTION:The sampling data A inputted to a delay circuit 14 is applied to each input of an AND circuit 15 and an OR circuit 16. An output signal B passing through the circuit 14 is fed to othe input of the circuits 15, 16. An output signal C of the circuit 15 is inputted to one input of the OR circuit 17 and an output signal D of the circuit 16 is fed to one input of the AND circuit 19. Then a signal E completing the waveform shaping before one sampling is subjected to delay by a 1-sampling delay circuit 18, the delayed signal is ORed (17) with the signal C, its output and the signal D are ANDed (19) to output the waveform shaping signal E. Thus, the waveform shaping is applied to the input signal to both positive logic and negative logic signals.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to binary data sampled at equal intervals (1
Alternatively, the present invention relates to a waveform shaping device used for data shaping.

Configuration of conventional example and its problems FIGS. 1 and 2 show a conventional waveform shaping device and a waveform shaping flowchart. 1 is a sampling circuit, and this sampling circuit 1 is connected to a delay circuit 2 and an AND circuit 3 via a signal line 6. Reference numeral 4 denotes a timing generation circuit, which controls the sampling timing of the sampling circuit 1 and the delay timing of the delay circuit 2 through a signal line 9. The AND circuit 3 calculates the AND of the result sampled by the sampling circuit 1 and the result delayed by one sampling through the delay circuit 2, and outputs this result to the signal line 8. In this way, the waveform of the input signal is shaped.

In FIG. 2, 10 is a data input routine;
The input data is stored in memory A. 11 is a delay routine, which waits for the next input. 12 is a data input routine, and the input data is stored in memory B. The logical product of these input data is calculated in step 13.

This series of flowcharts results in waveform shaping.

The conventional waveform shaping method described above is for positive logic signals (high level signals are active signals).
Negative logic signal (low level signal is active signal)
In this case, the AND circuit 3 in FIG. 1 is replaced with an OR circuit, and the AND routine 13 in FIG. 2 is replaced with an OR routine.

Next, the operation of the above conventional example will be explained. The timing generation circuit 4 shown in FIG. 1 generates the timing signal shown in FIG. 3A, and the waveform shaping circuit shown in FIG. 1 operates in synchronization with the rising edge of the timing signal A.

FIG. 3B shows an example of an input signal input to the sampling circuit 1 from the signal line 5. When this input signal is input to the sampling circuit 1, a sampling result synchronized with the timing signal A is output from the sampling circuit 1 to the signal line 6 as shown in FIG. This sampling data (
3C) is sent to the 1-sampling delay circuit 2 and the AND circuit 3 via the signal line 6. The delay circuit 2 inputs the sampling data C, delays it by one sampling time, and outputs the signal shown in FIG. 3D to the signal line 7. The AND circuit 3 performs an AND operation on the sampling data C thus obtained and the sampling data D delayed by one sample, thereby shaping the waveform of the input signal. The output waveform of the waveform shaping circuit is shown in FIG. 3E.

However, the conventional example described above has the disadvantage that different circuits or procedures are required for each of the positive logic signal and the negative logic signal, making the circuit and procedure complicated.

Purpose of the Invention The present invention eliminates the drawbacks of the above-mentioned conventional example, and aims to enable waveform shaping of an input signal using the same simple circuit for both positive logic signals and negative logic signals. That is.

Structure of the Invention In order to achieve the above object, the present invention outputs the sampled data as a waveform shaping output when the data one sample before and the sampled data match, and when they do not match, the waveform is shaped one sample before. The results are output as waveform shaped output.

DESCRIPTION OF EMBODIMENTS The configuration of an embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, 14 and 18 are 1 sampling delay means;
15 and 19 are logical product means, and 16 and 17 are logical sum means. Sampling data A (
5A) is applied to one of the inputs of the AND means 15 and the OR means 16, respectively. The sampling data A is also an input signal to the delay means 14, and the output signal B (FIG. 5B) that has passed through the delay means 14 is applied to the remaining input of the AND means 15 and the OR means 16. Ru.

As a result, the output signal of the AND means 15 becomes a signal as shown in FIG. 5C, and similarly the output signal of the OR means 16 becomes a signal as shown in FIG. 5D.

Next, the result of waveform shaping completed 1 sampling ago is 1
Delayed by sampling delay means 18, and logical product means 1
A logical sum operation is performed with the result of step 5 in the logical sum means 17.

This operation result and the output of the logical sum means 16 are combined in the logical product means 1.
9, and performs waveform shaping. The waveform shaped signal thus obtained is shown in FIG. 5E.

In FIG. 5, when compared with the input signal A, it can be seen that the waveform-shaped signal E is shaped at the signal change point.

FIG. 6 shows the waveform shaping routine. In Figure 6,
20 is a routine for sampling and inputting the input signal to be waveform-shaped. The sampled input data is stored in memory A. 21 is a delay time that determines the sampling time.

22 is a routine for sampling and inputting.

The sampled input data is stored in memory B. 23 is a routine that performs an AND operation between two pieces of data sampled and input after a delay time, and stores the result in memory C. 24 is a routine that performs an OR operation between two sampled input data and stores it in memory D; 25 is a routine that combines the result of the AND operation in routine 23 and the result of waveform shaping using the data sampled one sample before. A routine 26 performs a logical sum operation and stores the result in the memory E. A routine 26 performs a logical AND operation on the result calculated in the routine 25 and the result calculated in the routine 24, and stores the result in the memory F.

Reference numeral 27 denotes a routine that outputs the result of the calculation in the routine 26, that is, the result of waveform shaping the input sampling data, to the outside. 28 is a routine that moves the contents of memory B to memory A and prepares for the next sampling input;
9 is a delay time for the next sampling input.

Incidentally, FIG. 7 shows the input/output characteristics of the above embodiment.

Effects of the Invention The present invention has the above-described configuration, and provides the following effects.

(a) The input signal can be shaped into a positive logic signal and a negative logic signal.

(b) Chattering can be easily prevented by using it for key input using a microcomputer or the like.

(c) It has advantages such as being able to be used as an external noise removal circuit in NRZ signal transmission.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram of a conventional waveform shaping device, FIG. 2 is a flowchart of the same device, FIG. 3 is an explanatory diagram of the operation of the device, and FIG. 4 is a diagram of a waveform shaping device in an embodiment of the present invention. Functional block diagram, Fig. 5 is an explanatory diagram of the operation of the device, Fig. 6
The figure is a flowchart of the same device, and FIG. 7 is an input/output characteristic diagram of the same device. 14, 18... Delay means, 15, 19... AND means, 16, 17... OR means. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Claims] means for sampling the input signal; means for delaying the sampled data of the input signal by one sampling time; and means for outputting the sampled data as a waveform shaping output when the data one sample before and the sampled data match; A waveform shaping device comprising means for outputting a result of waveform shaping one sampling before as a waveform shaping output when data before sampling and sampled data do not match.