JPS60213150A - Code system - Google Patents

Abstract

PURPOSE:To prevent erroneous collation of an information code string while frames are in out-of-synchronization by dividing the information code string into two parts, inserting check bits consisting of two bits between the divided codes, and inverting the logical values of the check bits alternately in each frame. CONSTITUTION:A frame is constituted of a frame synchronizing bit F, an information code string I1-IK consisting of K bits, the check bits C1, C2, and an information code string of N-K bits; and the logical values of the check bits C1, C2 are alternately inverted. If out-of-synchronization is generated in case of comparing the information code strings between the succeeding two frames and deciding the correctness/incorrectness of the information code strings, unmatching is detected at the existence of the check bits C1, C2, so that overlock errors which may be generated in the period from the generation of out-of-synchronization to its detection can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is used in data communication systems and the like to transmit relatively short binary information code strings such as frame synchronized control signals in a constant cyclic manner using a synchronous transmission path. This relates to the coding system used when transmitting data to a computer.

Conventional technology Conventionally, this type of coding system has the following characteristics in a normal synchronization state:
As shown in Figure 1, 1 bit and 5 frame synchronization bits are assigned to 1 frame and transmitted, and on the receiving side, a synchronization pattern P consisting of frame synchronization bits of multiple frames is transmitted.
,,P,... ◇In Figure 1, frame synchronization positions A, A, T, and F are respectively Fs.
, Fs, Ps, and F4. In addition, a line comparison method is adopted to determine whether the information code string is correct or incorrect, and the received code is determined to be a storm only when there is a match between adjacent frames. For each N-bit correct information code string shown in FIG.

It is judged to be good.

In the case of synchronization position detection, forward protection is used to stabilize the synchronization against code errors in the transmission path.In other words, it takes several frames from when the synchronization actually occurs until the circuit detects the synchronization loss. It takes time, and during this time, information code strings are extracted at incorrect synchronization positions. FIG. 2 shows this out-of-synchronization state, where the frame synchronization positions (errors) S, S, S, and SE are shifted by one bit from FllF, F, F4, respectively. In the comparison to determine whether the information code strings listed in i are correct or incorrect, for example, in the comparison judgment operation, for example, the frames included in the information code strings If the synchronization bits F and F3 are the same, there is a match, and the erroneous information code string is determined to be good and sent to the subsequent circuit. The probability of this missed error depends on the configuration of the synchronization pattern, but assuming randomness, it is 0.5, which is quite high.

As described above, the conventional coding system has the disadvantage that the false identification by the matching system is susceptible to out-of-synchronization. To provide a coding system which solves the above drawbacks and prevents missed mistakes in checking and determining the comparison of information code strings that occurs during the period from when an out-of-synchronization occurs to when a circuit detects an out-of-synchronization. It is in.

Structure of the Invention In order to achieve the above-mentioned object, the present invention has a frame structure of one frame that is constantly transmitted cyclically, and includes a frame synchronization signal of 1 bit, 1 bit, N bit, 5 information code string, 2 bits, The N-bit information code string t-
Divide into two bits, y bit (K>1) and N- bit, and insert the 2 check bits between them, and alternately invert the logical values of the check and qu bits every frame. This method adopts a method that allows

Example Next, embodiments of the present invention will be described with reference to the drawings.

In FIG. 3, which shows the operation of the coding system of the present invention in a normal synchronization state, the frame structure of the embodiment of the present invention includes frame synchronization, F, K-bit information code strings 11 to Ix, y) Ot, 0! and an information code string of bits in N−, Che, fired 0+, Ot
The logical value of is alternately inverted every frame.

Frame synchronization position detection is the same as in the conventional coding system, consisting of a synchronization pattern P, consisting of the synchronization bits of each frame.
This is done by detecting F, . In addition, the correctness of the information code string is judged by +1~IN for the two divided parts, ~Ix and
The received code is determined to be good when the information code strings in the following frames match. Please check again ) O
The reversibility of r and Ot is checked for each frame. In other words, the frame synchronization positions A, A, and F are F, respectively.
, F, , F, and the correct information code string of K bits O1. For Car 1 and N-, the information code string O21 and Car 2 have correct bits, and the matching judgment operations Case 1 and Che 2 are judged to be good.

Figure 4 shows an example of when p-frame synchronization occurs due to some reason, and similarly to Figure 2, the frame synchronization position (
Incorrect C), S, and S are each shifted by one bit from FllF, , F, respectively. This indicates that the information code string at the erroneous synchronization position is extracted and a comparison determination is performed. In the K-bit collation judgment check 1, the check bit 01 is included in the bits in the incorrect information code string, and the bits are reversed to 0 and 1 between the previous and subsequent frames, so there is no mismatch in the collation judgment. Missing errors such as those in the conventional collation/judgment test shown in FIG. 2 do not occur.

Therefore, an erroneous information code string is not sent to the subsequent circuit.

Note that if the check and qubit t'' are set to only one 0., the synchronization will be greatly deviated, and if the incorrect frame synchronization position happens to coincide with the 01 position, matching will be performed if the successive frame signals are the same, as in the conventional case. It can be seen that there is a risk of a missed judgment, and two che and qubits of 0.0t are required.

Effects of the Invention As explained above, according to the present invention, two checks,
Since the configuration is configured so that the logic value is inverted and inserted for each frame, no matter where the synchronization occurs and the incorrect frame synchronization position is located,
When the information code strings are compared, it is determined that they do not match, which has the effect of preventing missed errors.

Claims (1)

[Scope of Claims] In a system that constantly cyclically transmits an information code string of N bits (N>2), the code structure of the S17 frame consists of a frame synchronization signal of 1 bit and the information code of the N bits and bits. The information code string of N bits is made up of a string, 2 bits, 2 bits, 2 bits, 2 bits, and 2 bits. ) (IC> 1) and N-, and insert the 2 bits, che and qubits between them, and alternately invert the logical values of che and qubits every frame. A coding system characterized by