JPH0312499B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an automatic identification level control circuit, and particularly to a transmission error correction circuit for a signal in a format in which data 1 or 0 is determined depending on the level of an identification result, and the present invention relates to a PCM including error-correctable data such as a Hamming code.
This invention relates to an automatic identification level control circuit for communication. Conventionally, code errors in data transmission including data in an error-correctable code system are caused by noise in the transmission path, unevenness in signal identification level on the receiving side, and deviation in sampling timing. Since the effects of transmission path noise and sampling timing deviations on code identification on the receiving side are random, in error-correctable coding systems as shown in Table 1 below, unless the error rate is extremely high, The probability that two bits will be wrong at the same time in the same Hamming code is extremely small.

[Table] Since it is impossible for conventional error correctors to classify the details of the error, it is difficult to determine whether the code error is due to bias in the identification level, a difference in sampling timing, or the S/N of the received signal. Something or something undetectable. The rate at which "0" in data is mistaken for "1" If the rate at which "1" is mistaken for "0" in data is almost equal, the error is caused by noise in the signal or a difference in sampling timing, and the error rate If there is a difference between the two, it is considered that the error is caused by an imbalance in the discrimination level. An object of the present invention is to provide an automatic discrimination level control circuit that can maintain the optimum discrimination level of data by classifying and counting error-corrected codes according to the cause of discrimination level and correcting the discrimination level based on the counted value. is to provide. The present invention includes a first counter for counting the amount of received codes, and a second counter and a third counter for counting the number of times error correction has been performed by classifying the number of times error correction is performed according to the cause of the identification level. The count value of each counter is calculated by an arithmetic circuit, then processed by a conversion circuit to obtain a predetermined DC voltage, and the reference DC voltage is corrected with this DC voltage in an attempt to obtain the optimum discrimination level for the data. It is. An embodiment of the present invention will be described below with reference to the drawings. Note that the same parts in FIG. 1 and FIG. 2 are given the same reference numerals. In FIG. 1, 1 is a signal input terminal, 2 is a voltage comparison circuit, 3 is a shift register, 4 is a shift clock circuit, and 5 is an error correction circuit. This error correction circuit 5 is provided with error output terminals 6 and 7, a multiple error output terminal 8, and a correct data output terminal 9. “0” to error output terminals 6 and 7
The number of times when "1" is mistaken for "1" and the number of times "1" is mistaken for "0" are output, and these numbers are counted by the second counter 10 and the third counter 11, respectively. From shift lock circuit 4 to shift register 3
The shift lock C sent to the first counter 13 is simultaneously supplied to the first counter 13 via the multiple error gate circuit 12. When the multiple error gate circuit 12 receives a signal indicating a multiple error from the multiple error output terminal 8 of the error correction circuit 5, the shift lock C is switched to the first counter 13 in the section corresponding to this series of codes.
prohibited from being sent to first counter 1
3, a constant clock pulse C was counted in order to divide the calculation result of the subtraction circuit 14, which subtracts the count value of the third counter 11 from the count value of the second counter 10, by the count value of the division circuit 15. At the same time, the count value returns to "0", and the division circuit 15 is activated with this count value, and the calculated value obtained by subtracting the count value of the third counter 11 from the count value of the second counter 10 is calculated as the constant clock pulse C. Divide by the count value.
Also, at this time, the second counter 10, the third counter 11, and the subtraction circuit 14 are initialized. The division circuit 15 sends the calculation result to the DA conversion circuit 16. The DA converter circuit 16 outputs a predetermined DC voltage based on the numerical value, and sends this DC voltage output to the adder circuit 17. The adder circuit 17 corrects the reference voltage 18 using the DC voltage and applies it to the corrected DC voltage comparison circuit 2. As shown in FIG. 2, the error correction circuit 5 is composed of a syndrome generation circuit 19, a multiple error detection circuit 20, and an error classification circuit 21. The error classification circuit 21 is composed of an error bit designation circuit 22, an information bit correction circuit 23, an error check bit classification circuit 24, a 0-1 error bit circuit 25, and a 1-0 error bit circuit 26. The error bit designation circuit 22 receives the syndrome generated by the syndrome generation circuit 19 and sends information bits compiled from the syndrome to the information bit correction circuit 23. The error bit specifying circuit 22 outputs the error bit to the error check bit classification circuit 24 when the error bit is included in the check bits shown in the table. The information bit correction circuit 23 obtains the information bit a from the shift register 2 via the information bit terminal 5a, and outputs the error bit designation circuit 2.
It has a function of comparing with the information bits organized in 2, and when the comparison results in a match, the correct answer data is sent to the correct answer data output terminal 9. If there are bits that do not match in the above verification, the bits that do not match are corrected, the corrected correct data is sent to the correct data output terminal 9, and 0 is output according to the content of this correction.
-1 error bit circuit 25 or 1-0 error bit circuit 26 is activated. Further, the 0-1 error bit circuit 25 is connected to the error check bit classification circuit 2.
4 and the information bit correction circuit 23, which is activated when "0" is mistaken as "1", and outputs the error output terminal 6.
The 1-0 error bit circuit 26 similarly outputs the number of errors to the output terminal 7. Here, the signal is applied from the signal input terminal 1 to the voltage comparison circuit 2, where it is compared with the comparison voltage 18a passed through the addition circuit 17. The output of the voltage comparison circuit 2 is (+) from the comparison voltage 18a.
When it is, it is set as "1", and when it is (-), it is set as "0" and sent to the shift register 3. Therefore, when the comparison voltage 18a is not biased with respect to the signal,
The counts of the second counter 10 and the third counter 11 are approximately the same. Therefore, since the calculated value obtained by the subtraction circuit 14 is 0, the DA conversion circuit 16
The output of is also 0, and stable signal identification is performed. Syndrome and parity based on Table 1 listed above as an example are calculated as follows. S ₁ = _{1 2 3} b ₇ − S ₂ = _{1 2 4} b ₆ − S ₃ = _{1 3 4} b ₅ − P=b ₁ b ₂ b 3 b ₄ b ₅ b ₆ b _{7 b 8 −} 1 bit error The relationship between syndrome and parity is shown in Table 2 below.

[Table] The syndrome of S ₁ to _{S 2} is 0 when there is no error, and the parity P is 1 when there is no error or when the error is an even number of bits. Here, the signal identification circuit 1 receives, for example, the second bit _b2 of the 8-bit Hamming code data "10101011" corresponding to the code number _a5 in the Hamming code table mentioned above.
Suppose that "11101011" is entered by mistake, assuming that "0" is "1". This input signal is sequentially applied to the shift register 3, and a code of "11101011" is formed in the shift register 3. 1st bit from shift register 3 via 5a
Information bit “1110” from b ₁ to 4th bit b ₄ and
The check bit “1011” from the fifth bit _B5 to the second bit _B8 is sent to the syndrome generation circuit 1 via
9 is applied. The syndrome generating circuit 19 executes the logical operations described above, so that S ₁ S ₂ becomes 1 and S ₃ becomes 0. The syndrome obtained by the syndrome generation circuit 15 is applied to the error bit designation circuit 22. Furthermore, a signal indicating the occurrence of an error bit obtained from the syndrome generation circuit is applied to the multiple error detection circuit 20, and the multiple error detection circuit 20 executes the above-mentioned logical operation, and P becomes 0, and the shift register is It is possible to identify that the data obtained contains an odd number of errors, and unless the error rate is extremely high, it can be identified as a 1-bit error. The error bit designation circuit 22 designates the bit in which the error has occurred based on the relationship between the error bit, syndrome, and parity shown in Table 2. In this example, S ₁ S ₂ is 1 and S ₃ is 0, so P is 0, so the second
Bit _b2 can be identified as an error bit. This error bit designation signal is applied to the information bit correction circuit 23, which inverts the bits that require correction in the data obtained from the shift register 3, and outputs a correction output via 9. The signal obtained from the error bit designation circuit 22 is applied to the error check bit classification circuit 24, and the circuit 2
Compare the data from the shift register applied to 4 and classify whether 1 was mistaken as 0 or 0 was mistaken as 1.
Applied to the error bit circuit, ER _Z via 7 or 6
Or output the ER _P signal. Further, when an uncorrectable multiple error is detected from the circuit 20, the _ERM signal is outputted through the circuit 8 as in the conventional case. In this example, since "0" is mistaken as "1" when true, the second counter 10 is incremented via the 0-1 error bit circuit 25. In this way, the count value of the second counter 10 becomes greater than the count value of the third counter 11, and the result of the subtraction circuit 14 becomes positive. Since the discrimination level applied to the voltage comparator circuit 2 is lower than the optimum level, the D/A conversion circuit 16 generates a positive correction DC voltage that increases the discrimination level, and this DC voltage is used to increase the discrimination level by the addition circuit 17. Then, the discrimination level is corrected and maintained at the optimum level. Similarly, if there is a large percentage of errors in "0" when "1" is true, the calculated value of the third counter will be larger than the counted value of the second counter, and the result of the subtraction circuit 14 will be negative, and the D/A conversion result will also be negative. Since it is negative, adder circuit 17
The result is a voltage obtained by subtracting the correction amount from the reference voltage 18, and if the above-mentioned mistake of "0" to "1" can be corrected to the optimum level. As described above, the automatic identification level control circuit according to the present invention can change the data to 1 or 0 depending on the level of the identification result.
This is an automatic identification level control circuit that uses a signal in a format in which an error correction circuit that outputs a signal indicating the number of errors and a multiple error, respectively; and a first counter that counts the number of error-free codes and the amount of codes that have undergone error correction based on the signal indicating the multiple error. , a second counter that counts the number of times a 0 is mistaken for a 1 according to an output when a 0 supplied from the error correction circuit is mistaken for a 1; A third counter counts the number of times 1 is mistaken for 0 according to the output when 1 is mistaken for 0, and the difference between the counts of the second counter and the third counter is compared, A conversion circuit that obtains a DC voltage that is inversely proportional to the count value of the counter is provided, and if the rate of mistaking 0 as 1 and the rate of mistaking 1 as 0 are approximately equal, it is assumed that an error has occurred due to noise in the signal or a difference in sampling timing. and correcting the reference DC voltage with the DC voltage in response to detecting that a deviation in the identification level has occurred if there is a difference in the error rate,
Since this is an automatic discrimination level control circuit that obtains the optimum discrimination level of the code, it has the advantage that the discrimination level of the signal always maintains the optimum value and can prevent the generation of erroneous codes due to bias in the discrimination level.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an automatic discrimination level control circuit according to the present invention, and FIG. 2 is a block diagram of the error correction circuit of FIG. 1. 1... Signal input terminal, 2... Voltage comparison circuit, 3
...Shift register, 4...Shift clock circuit, 5...Error correction circuit, 6, 7...Error output terminal, 8...Multiple error output terminal, 9...Correct data output terminal, 10...Second counter , 11
... Third counter, 12 ... Multiple error gate circuit, 13 ... First counter, 14 ... Subtraction circuit, 15 ... Division circuit, 16 ... D-A conversion circuit, 17 ... Addition circuit , 18...Reference voltage, 19
... Syndrome generation circuit, 20 ... Multiple error detection circuit, 21 ... Error classification circuit, 22 ... Error bit designation circuit, 23 ... Information bit correction circuit, 24 ... Error check bit classification circuit, 25
...0-1 error bit circuit, 26...1-0 error bit circuit.

Claims (1)

[Scope of Claims] 1. An automatic identification level control circuit using a signal in a format in which 1 or 0 of data is determined depending on the level of the identification result, which includes data in transmitted data including error-correctable coding system data. an error correction circuit that outputs a signal indicating the number of times a 0 is mistaken for a 1 and a number of times a 1 is mistaken for a 0, and a signal indicating multiple errors; a first counter that counts the amount of error-corrected codes; and a first counter that counts the number of times a 0 is mistaken for a 1 according to an output when a 0 is mistaken for a 1 supplied from the error correction circuit. a third counter that counts the number of times a 1 is mistaken for a 0 according to an output when a 1 is mistaken for a 0 supplied from the error correction circuit; The counter is provided with a conversion circuit that obtains a DC voltage that is proportional to the difference between the count value of the third counter and inversely proportional to the count value of the first counter, and the rate of mistaking 0 as 1 and the rate of mistaking 1 as 0 are provided. If the error rates are substantially equal, it is detected that an error has occurred due to noise in the signal or a difference in sampling timing, and if there is a difference in the error rate, it is detected that a deviation in the discrimination level has occurred. An automatic discrimination level control circuit characterized in that an optimum discrimination level of a code is obtained by correcting a reference DC voltage with a DC voltage.