JPH01317042A - Data transmission system - Google Patents

Abstract

PURPOSE:To detect a data error without deteriorating the transmission efficiency by adding check bits in 2-bit inverted to each other and for each word period to the end of a serial data for each word period. CONSTITUTION:Two check bits CHECK1, CHECK2 inverted mutually and for each word period are added to the end of a serial data SDATA for each word period and the result is sent. Then whether the two check bits CHECK1, CHECK2 inverted mutually and for each word period are added to the end of a serial data SDATA for each word period or not is confirmed to detect the data error. Thus, the data error is detected by a simple circuit and the data is sent without much deteriorating the transmission efficiency.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Field of industrial application B. Overview of the invention C. Conventional technology D. Problem to be solved by the invention E. Means for solving the problem (Figures 1 and 2) F
Effect G Embodiment G1 Description of the transmitting side circuit G2 Description of the receiving side circuit H Effect of the invention 8 Industrial application field The present invention relates to a data transmission system for converting parallel data into serial data and transmitting the same.

B. Summary of the Invention The present invention provides a data transmission method in which parallel data is converted into serial data in word periods and transmitted, in which serial data is inverted at the end of each word period,
Furthermore, by adding and transmitting 2 check bits, each of which is inverted every word period, it is possible to eliminate data errors without significantly reducing transmission efficiency or requiring complicated circuits. It is designed to be detectable.

C. Prior Art FIG. 5 shows an example of a system control system for a multi-channel PCM recorder.

In the same figure, (10) is the main CPU, (20)
is the keyboard CPU, (30) is the transport C
It is PU.

The main CPU (10) manages the entire main system. This main CPU (10) also controls the edit board (ED board) and clock board (CK
(substrate), recording substrate (RFC substrate), etc., and controls which channel to put into the recording state, what sampling frequency to set, etc. Furthermore, this main CP
U (10) has a remote control transmitter (
11) is connected via the terminal (12). Also, (1
3) is a terminal for supporting communication protocols.

Further, the keyboard CPU (20) detects keys on the keyboard and controls display using light emitting diodes and the like. Note that (21) is a terminal to which control data indicating which channel is to be put into a recording state is supplied, and is sent to, for example, a mixing console. (22) is an interface. Further, (23) is a terminal to which control data for playback, recording, stop, etc. is supplied, and is connected to, for example, a system controller.

Further, the transport CPU (30) controls the transport (tape drive mechanism) such as playback, recording, and stopping. Also, this transbo)
The CPU (30) performs 11NiD on the CTL board, and performs functions such as recording and reproducing absolute addresses of hours, minutes, seconds, and sectors on a control track (not shown), and auto-punch to start recording or reproducing at a certain predetermined timing. controlled. Also, this transport) CPU (30)
The time code TC (for example, SMPTE time code) generator and reader are controlled by the time code TC (for example, SMPTE time code) generator and reader. This time code TC generator and reader are provided in relation to the video signal.

In addition, the main CPU (10) and transport C
Status information is communicated with the PU (30). For example, system controller key information is sent from the main CPU (10) to the transport CPU (30);
30), the main CPU (10) has playback, recording,
Transport information such as stop, tape time information, etc. are transmitted.

In addition, the main CPU (10) and keyboard CPU
Status information is also communicated with (20). Such communication is performed, for example, in 8-bit parallel.

By the way, in such a system control system, since the main CPU (10) and the recording board are arranged separately, control data is transmitted from the main CPU (10) to the recording board using a cable. In this case, there is a lot of control data, and if it is transmitted as parallel data, the number of cable lines will increase, so the parallel data is converted into serial data and transmitted.

For example, FIG. 6A shows the master clock CLK.

B in the figure is the word synchronization signal WS, and the parallel data is serial data 5DAT at the cycle of the word synchronization signal WS.
It is converted to ^ and transmitted. C in the figure shows serial data 5DATA. - As an example, the frequency of the master clock CLK is 9.216 MHz, the frequency of the word synchronization signal is 48 kHz, and the SN is 24.

Now, as mentioned above, from the main CPU (10)
If the data transmitted to the C board turns out to be incorrect due to a break in the transmission line, etc., there will be problems such as incorrect recording, so data transmission methods have been devised to detect this error. ing. For example, methods have been proposed that provide redundancy to data. In this method, one piece of data is placed in two slots; for example, data A is placed in the first slot as data A, and in the second slot as inverted data W.

Then, on the receiving side, the exclusive OR of the data of these two slots is performed, and the
The data error is detected by confirming that the two data are A and A.

Furthermore, for example, a method of adding a CRC code to data has been proposed.

D Problems to be Solved by the Invention However, these conventional methods have the following disadvantages. That is, according to the former method, only half of all slots can be used for data transmission, resulting in low transmission efficiency. On the other hand, according to the latter method, the detection is almost completely established, but the circuit configuration becomes complicated and the transmission efficiency decreases due to the addition of the CRC code.

Therefore, it is an object of the present invention to (1) make it possible to detect data errors without significantly reducing transmission efficiency and without requiring a complicated circuit.

E. Means for Solving the Problems The present invention is a data transmission method that converts parallel data into serial data in a word cycle and transmits the data. is inverted every word period2
Bit check bit CHIECK1. CHECK
2 is added and transmitted.

F Function In the above configuration, the 2-bit check bit C) IEIC added to the end of the serial data 5DATA for each read cycle is 1. Since data errors are detected by checking whether CI (εC) and 2 are inverted with each other and each is inverted every word period, data errors can be detected with a simple circuit. Since 1.CHECK2 is only added to the 2-bit check bit CHBC at the end of the serial data 5DAT^ for each cycle, data can be transmitted without significantly reducing transmission efficiency.

G. Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

G1 Description of the transmitting circuit FIG. 1 shows the transmitting circuit arranged in the main CPU (10).

In the figure, (41) is a timing generator, and this timing generator (41) has a frequency of 9.216.
MHz master clock CLK (illustrated in Figure 3A)
and a word synchronization signal WS (shown in the same figure) having a frequency of 48 KHz. The word synchronization signal WS is at a low level "0" for one period of the master clock CLK.

From the timing generator (41), the master clock C
Based on LK and word synchronization signal WS, load signal SLD (illustrated in Figure 3C) and frequency 1.152
A MHz shift clock 5CLK (shown in the same figure) is generated. And the load signal SLD is parallel/
It is supplied to a load terminal LOAD of a 24-stage shift register (42) constituting a serial conversion circuit. In this case, the load signal SLD changes from high level “1” to low level “1”.
0”, the parallel input terminals PIO~P
123 is taken into each stage of the shift register (42). Further, the shift clock 5CLK is supplied to the clock terminal CK of the shift register (42). In this case, the data in each stage of the shift register (42) is sequentially shifted to the next stage at the timing when the shift clock 5CLK changes from a low level "0" to a high level "1".

In addition, the parallel input terminal pr of the shift register (42)
o to PI21 have data DATAO to DAT, respectively.
A21 is supplied.

Further, (43) is a D flip 70 tube, whose clock terminal CK is supplied with a word synchronization signal WS, and the output signal of its input terminal is supplied to its D terminal. and,
The output signals of the Q terminal and the input terminal of this D flip 70 tube (43) are supplied to the parallel input terminals PI22 and PI23 of the shift register (42) as check bits CHECKI and CH1liCK2, respectively.

In the above configuration, the serial data 5DATA obtained by converting the data DATAO to DATA21 supplied to the parallel input terminals PIO to PI21 at a word cycle is output to the terminal of the shift register (42). Also, D
The Q terminal and Q terminal of the flip-flop (43) are
Since signals are output that are mutually inverted and each inverted every word period, the above-mentioned shift register (4
At the end of the serial data 5DATA output to the input terminal 2), 2-bit check bits CHBCKI and CIIBCK2, which are inverted with each other and each inverted every word period, are added. Therefore, serial data 5DATA as shown in FIG. 3G is output to the terminal of the shift register (42), and this serial data AT^ is transmitted to the receiving side via the buffer (44). .

In addition, the master clock CLK and the word synchronization signal W
S are transmitted to the receiving side via buffers (45) and (46), respectively.

G2 Description of Receiving Side Circuit Next, FIG. 2 shows the receiving side circuit arranged on the REC board.

In the figure, (51) is a timing generator, and this timing generator (51) includes a master clock CLK (shown in Figure 3A) and a word synchronization signal WS (shown in Figure 3A) transmitted from the transmitting side. (shown in FIG. 1) are supplied via buffers (52) and (53), respectively. The timing generator (51) generates a shift clock 5CLK' (shown in E of the same figure) based on the master clock CLK and the word synchronization signal WS.

This shift clock 5CLK' is placed in a phase-inverted relationship with the shift clock 5CLK (shown in the same figure) described above. And this shift clock 5CLK' is
The signal is supplied to a clock terminal CK of a 24-stage shift register (54) constituting a serial/parallel conversion circuit. In this case, shift clock 5CLK' is at low level "
At the timing when the level changes from "0" to high level "1", the data in each stage of the shift register (54) is sequentially shifted to the next stage, and the data supplied to the serial input terminal SIN is sequentially taken into the register. .

Also, the serial input terminal SI of the shift register (54)
N contains serial data 5DAT transmitted from the transmitting side.
A is supplied through a series circuit of a buffer (55) and an inverter (56). The inverter (56) is arranged to return what is transmitted in negative logic to positive logic.

Further, (57) is a D flip-flop whose clock terminal CK is supplied with the shift clock SCL from the timing generator (51), and whose D terminal is supplied with serial data from the output side of the buffer (55). 5DATA is supplied. The signal output to the Q terminal of this D71J tube prop (57) is supplied to the D terminal of the D flip-flop (58), and the shift clock 5CLK' is supplied from the timing generator (51) to its clock terminal CK. Ru. And the Q of the D flip-flop (57)
The signal output to the terminal and the terminal of the D flip 70 tube (58) is supplied to the input side of the exclusive OR circuit (59).
) is supplied to the input side of the NOR circuit (60).

Further, (61) is a D flip-flop whose clock terminal CK is supplied with the master clock CLK from the output side of the buffer (52), and whose D terminal is supplied with the word synchronization signal WS from the output side of the buffer (53). is supplied. The signal output to the terminal of this D flip-flop (61) is supplied to the clock terminal CK of the D flip-flop (62), and the signal is output to the Q terminal of the D flip-flop (57). A signal is provided. The signals output to the right Q terminal of the D flip-flop (57) and the left terminal of the D flip-flop (62) are supplied to the input side of the exclusive OR circuit (63).
The output signal of this exclusive OR circuit (63) is supplied to the input side of the NOR circuit (60).

The output signal of the NOR circuit (60) is then supplied to the load terminal LO^0 of the hexadecimal counter (64). In this case, the signal supplied to one load terminal An is at a low level “
When it becomes 0'', the hexadecimal counter (
64), the data of each pit is input to its data input terminal A-
It is assumed that the data is supplied to D. Note that the data input terminals A to D are grounded, and therefore, a low level "0" signal is supplied to each of the data input terminals A to D.

Further, the signal output to the ripple carry output terminal RCO of the hexadecimal counter (64) is supplied to the count enable signal input terminal P via the inverter (65). In this case, the hexadecimal counter (64) is configured such that the signal supplied to the count enable signal input terminal P is at a high level "1".
”, it is in a counting state, while when it is at a low level “0”, it is in a hold state.

Furthermore, the signal output to the ripple carry output terminal RCO of the hexadecimal counter (64) is
) is supplied to the reset terminal π. In this case, when a low level “0” signal is supplied to the reset terminal π,
The shift register (54) is reset.

Further, the signal output to the ζ terminal of the D flip-flop (61) is supplied to the latch terminal of the shift register (54). In this case, when the signal supplied to the latch terminal changes from a low level "0" to a high level "1", the data in the first to 22nd stage registers of the shift register (54) is latched and the output terminal Q0 - Derived from Q21.

Further, (66) is a one-shot circuit, and its trigger terminal TRG is supplied with the master clock CLK from the output side of the buffer (52). In this case, when the time constant is adjusted and there is no master clock CLK,
A high level "1" signal is output from the Q terminal. Further, (67) is also a one-shot circuit, and the word synchronization signal WS is supplied to the trigger terminal TRG from the output side of the buffer (53). In this case, the time constant is adjusted so that when there is no word synchronization signal WS, a high level "1" signal is output from the ζ terminal.

And ζ of one-shot circuits (66) and (67)
The signal output to the terminal is supplied to the input terminal of a NOR circuit (68), and the output signal of this NOR circuit (68) is supplied to the clear terminal CLR of the hexadecimal counter (64).

In this case, when a low level "0'" signal is supplied to the clear terminal CLR, the hexadecimal counter (64) is cleared.

Note that the clock terminal CK of the hexadecimal counter (64) is supplied with a signal output to the ζ terminal of the D flip-flop (61).

In the above configuration, the clock terminal CK of the shift register (54) has a shift clock 5CLK' (third
(shown in Figure E) is supplied with a shift register (54
) is sequentially shifted to the next stage, and data supplied to the serial input terminal SIN is sequentially taken into the register.

Here, the signal output to the ζ terminal of the D flip-flop (61) is as shown in FIG. 3F. therefore,
After the data in the 1st to 24th stage registers of the shift register (54) are respectively transferred to DAT80 and C) IBCK2, the signal supplied to the latch terminal becomes low level "0".
# becomes a high level "1" and the data of the first to 22nd stage registers are latched, so the output terminals QO to Q21
, data D^TAO to DATA21 are sequentially taken out in word cycles.

In addition, the data of the first to 24th stage registers of the shift register (54) are respectively DATAO~(:HECK2
, the D flip-flops (57) and (58
), the check bits C)IBC2 and C11EiCK1 are output to the Q terminals of the IBC and C11EiCK1, respectively. When these check bits CI (1 in EC and 2 in CHBC are inverted, the exclusive OR circuit (59)
The output signal is low level “0”, and at other times,
It becomes a high level "l".

Also, the clock terminal CK of the D flip-flop (62)
is supplied with the signal output to the ζ terminal of the D flip-flop (61) (shown in FIG. Check bit CHECK2 is output.

When the current check bit CHECK2 and the check bit C)lEcK2 from l word period ago are inverted, the output signal of the exclusive OR circuit (63) is low level "0"; otherwise, it is high. The level becomes “1”.

Therefore, check bits CHECK1 and CI(
2 is reversed to EC and current check bit C
Check bit CH 2 and 1 word period before HεC
When ECK2 are inverted each other (serial data 5
When it is considered that there is no error in DATA), the output signal of the NOR circuit (60) is at high level "l", so 1
The hexadecimal counter (64) does not take in the data supplied to the data input terminals AD, and a high level "1" signal continues to be output to the ripple carry output terminal RCO. Therefore, the hexadecimal counter (64) is placed in a hold state, and the shift register (54) is not reset.

On the other hand, check bit C) IBcKI and CHECK
2 are not inverted with respect to each other, or the current check bit CHEiCK2 and the check pick of one word period ago). The output signal of the circuit (60) is low level "0"
”, the low level “0” data supplied to the data input terminals A-D is taken into the hexadecimal counter (64), so the ripple carry output terminal RC○ receives a low level “0” signal. is output, and therefore the shift register (54) is reset.

As a result, erroneous data DATAO to DATA21 are not output to the output terminal QO-Q21. Also, 16
The advance counter (64) is placed in a counting state. Therefore, when the output signal of the NOR circuit (60) becomes high level "1" at the timing when the signal output to the circuit terminal of the D flip-flop (61) changes from low level "0" to high level "1", The count is sequentially counted up, and when this state continues 16 times, a high level "1" signal is output to the ripple carry output terminal RCO, and the shift register (
54) is released from the reset state.

Furthermore, when there is no master clock CLK or word synchronization signal WS, the output signal of the NOR circuit (68) becomes low level "0'" and the hexadecimal counter (64) is cleared, so the ripple carry output terminal RCO is A low level "0" signal is output, so that the shift register (54) is reset.

As a result, erroneous data DATAO to DATA21 are not output to the output terminals QO to Q21.

In this way, according to this example, it is checked whether the 2-bit check bits (CHECK1 and CHECK2) added to the end of the serial data 5DATA for each word period are inverted with each other and each word period is also inverted. This is used to detect errors in the data DATAO~TA21, and this error is detected by the D flip-flop (5
7), (58), (61), (62), exclusive OR circuit (59), (63), NOR circuit (
60) can be detected with a simple circuit consisting of: Note that since the check picks CHtICKl and CHBCK2 are added to the end of the serial data SO^TA for each word cycle, an error in the serial data 5DAT^ is
E2 in Figure 4B. Things that fall on the check bits, as shown in E3, can be reliably detected, but things that do not fall on the check bits, such as El, cannot be detected. Note that A in the figure shows the word synchronization signal WS.

Also, at the end of the serial data 5DATA for each word period, there is a 2-bit check (1.') in the qubit CIIEIC.
Since 2 is only added to CHBC, data can be transmitted without reducing transmission efficiency.

According to the above embodiment, when the output signal of the NOR circuit (60) becomes low level "0", the shift register (54)
), the signal supplied to the latch terminal is gate-controlled, and the output terminal QO~
It is also possible to output the same data DATAO to DATA21 as before to Q21.

H Effects of the Invention As described above, according to the present invention, the two check bits added at the end of the serial data in each word period are mutually inverted, and it is possible to determine whether or not each of them is inverted in each word period. Data errors can be detected with a simple circuit. Further, since only two check bits are added to the end of the serial data for each word period, data can be transmitted without significantly reducing transmission efficiency.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing one embodiment of the present invention, FIGS. 3 and 4 are diagrams for explaining the same, and FIG. 5 shows an example of the system control system of a multi-channel PCM recorder. 6 are diagrams for explaining a conventional example. (41) and (51) are timing generators, (42)
and (54) is a shift register, (43) (57)
(58) (61) and (62) are D flip-flops, (56) is an inverter, (59) and (63)
are exclusive OR circuits, (60) and (68)
is a NOR circuit, (64) is a hexadecimal counter, and (66) and (67) are one-shot circuits. Agent Mamukai Ito
Hidemori Matsukuma Figure 1 (WS) Figure 4 Figure 5

Claims (1)

[Claims] In a data transmission method in which parallel data is converted into serial data in a word period and transmitted, two check bits that are mutually inverted and each inverted in each word period are inserted at the end of the serial data in each word period. A data transmission method that is characterized by the fact that data is added and transmitted.