JP2013059029A - Signal conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal conversion device that can detect an error in converting a serial signal to a parallel signal.SOLUTION: In an embodiment, the signal conversion device includes first conversion means, second conversion means and determination means. The first conversion means converts a parallel signal group including a fixed signal group logically invariable during energization in a predetermined signal position to a serial signal. The second conversion means samples the serial signal to convert the serial signal to the parallel signal group. The determination means determines that the conversion by the second conversion means is successful when detecting the fixed signal group in the predetermined signal position of the parallel signal group converted by the second conversion means.

Description

  Embodiments described herein relate generally to a signal conversion apparatus.

  An I / O expansion technique using parallel / serial conversion is known. In order to control I / O in CPUs, ASICs, etc., in order to increase the number of I / Os that can be handled while reducing the number of terminals and reducing the package of the CPU itself, it is equipped with a serial / parallel conversion function inside, There is known a technique for reducing the size and securing the number of I / Os by connecting a parallel / serial conversion circuit outside the CPU.

JP 2005-225237 A

  Usually, data transfer after parallel / serial conversion is often performed in synchronization with CLK. However, the CLK and SFT / LD may contain noise in the transmission path, which may cause the data to shift and not be read correctly. Alternatively, the data may be processed as correct data even though the data is shifted.

  An object of the present invention is to provide a signal converter capable of detecting a conversion error from a serial signal to a parallel signal.

  The signal conversion apparatus according to the embodiment includes a first conversion unit, a second conversion unit, and a determination unit. The first conversion means converts a parallel signal group including a fixed signal group that does not change logic at a predetermined signal position into a serial signal during energization. The second conversion means samples the serial signal and converts the serial signal into the parallel signal group. The determination unit determines that the conversion by the second conversion unit is successful when the fixed signal group is detected from the predetermined signal position of the parallel signal group converted by the second conversion unit.

It is a figure which shows an example of the signal converter which concerns on 1st Embodiment. It is a figure which shows an example of the signal converter which concerns on 2nd Embodiment. It is a figure for demonstrating the example of the sampling by CLK signal which does not contain noise. It is a figure for demonstrating the example of the sampling by CLK signal containing noise in 16-bit transfer. It is a figure for demonstrating the example of the sampling by CLK signal containing noise in 17-bit transfer. It is a figure for demonstrating the example of the sampling by the Shift / Load signal containing noise in 17bit transfer. It is a figure which shows that either one of the data input terminal for cascade connection of a shift register and two option connection signals becomes logic different from another signal by a NOR circuit.

  The first and second embodiments will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a signal conversion apparatus according to the first embodiment. As shown in FIG. 1, the signal conversion apparatus includes a serial / parallel conversion circuit SP1, a first shift register SR1, a second shift register SR2, and a control circuit C1.

  In order to expand the input, information such as sensor signals is assigned to the parallel inputs A to H of the first shift register SR1 and the second shift register SR2 connected to the serial / parallel conversion circuit SP1. Among these, combinations of predetermined input terminals that are output as continuous data during parallel / serial conversion by the first shift register SR1 and the second shift register SR2 (for example, parallel inputs A and B of the second shift register SR2, ie, predetermined Assign a fixed signal to (Signal position). A fixed signal is an invariable value of logic during energization. As the fixed signal, for example, destination information of a device including a shift register, model information (model identification information), or board information can be used. Hereinafter, a case where the model information A2, B2 (fixed signal group) is used as a fixed signal will be described.

  The model information is for determining which control is to be used when the control is different depending on the destination, the specification, etc. in the machines controlled by the common firmware. The model information usually consists of a combination of digital signals. Since the signal level is basically fixed at H or L when the power is turned on, the signal level changes while the power is on (energized). Never do. For this reason, if the serial data sent from the first shift register SR1 is correctly restored to parallel data by the serial / parallel conversion circuit SP1, the same value is always entered in a specific bit (predetermined signal position) of the parallel data. . In the case of FIG. 1, the data states A2 and B2 corresponding to the parallel inputs A and B (predetermined signal positions) of the second shift register SR2 are stored (see FIG. 3).

  Therefore, after the power is turned on, the control circuit C1 first specifies the value of the model information from the predetermined signal position of the parallel signal group obtained by sampling several times based on the sampling signal, as shown in FIGS. Thereafter, if the data is excessively shifted due to noise or the like with respect to the CLK signal, or the sequence is shifted between the control circuit C1 side and the shift register due to noise or the like with respect to the Load signal as shown in FIG. A value different from the model information is detected from the position (predetermined signal position). That is, the control circuit C1 determines a conversion error (serial / parallel conversion error) when a value different from the model information is detected from the position where the model information should be, and handles all converted data as invalid. Further, when the same value as the model information is detected from the position where the model information should be, the control circuit C1 determines that the conversion is successful (serial / parallel conversion is successful) and treats the converted data as valid. Thereby, malfunction due to noise can be reduced.

  Note that in such an extension, as shown in FIGS. 4 and 5, the detection of the case where the shift register shifts extra data due to the noise to the CLK, the cascade of the second shift register SR2 shown in FIG. It is desirable that the data input terminal for connection is fixed to H or L, and the model information 1 and 2 are combined so that the logic is not the same as the terminal processing of the data input terminal for cascade connection. Further, information necessary for the determination (for example, model information) can be assigned to the most upstream side of the second shift register SR, and the detection rate of data corruption can be improved. For example, the model information is assigned to a fixed signal group composed of N fixed signals from the head signal position constituting the parallel signal group to the N (N: integer, N ≧ 2) -th signal position. Although the model information is given here as input information, it may be substrate identification information.

  FIG. 2 is a diagram illustrating an example of a signal conversion apparatus according to the second embodiment. As shown in FIG. 2, the signal conversion apparatus includes a serial / parallel conversion circuit SP1, a first shift register SR1, a second shift register SR2, a control circuit C1, and a NOR circuit 2.

  In the signal conversion apparatus shown in FIG. 1, the case where model information is used as an example of a fixed signal group has been described. However, in the signal conversion apparatus shown in FIG. 2, an option connection detection signal is used as an example of a fixed signal group. As shown in FIG. 2, option connection detection signals 2 and 1 are input to parallel inputs A and B of the second shift register SR2.

  Options whose connection is detected by the option connection detection signals 2 and 1 are limited to options that are not removed while the power is on. That is, the optional connection detection signals 2 and 1 that do not change the logic are used while the power is on. The NOR circuit 2 determines the logic when the option detection signals A and B are not connected by a pull-up resistor or the like, and inverts the logic when connected. When the NOR logic signal of the option connection detection signals 2 and 1 is input to the data input terminal for cascade connection of the second shift register SR2, any combination of options (all options are not connected, Even if all the options are connected), the NOR circuit 2 always inputs one of the data input terminals for cascade connection of the shift register and the option connection signals A and B, which is different in logic from the other signals. (See FIG. 7). Therefore, it is possible to easily detect when data shift by the shift register is excessively performed due to noise.

  As shown in FIGS. 4 and 5, the case where 16-bit and 17-bit transfers are set to one cycle has been described. However, the transfer cycle is not limited to this and may be any number of bits. Further, in FIG. 2, transfer control including 1-bit input terminal for the most upstream cascade of the second shift register SR2 is performed, but there are combinations in which all combinations of signals used for determination are the same level. If it is not, there is no need to control the sequence including the 1-bit input terminal for cascade.

  The present embodiment will be summarized below.

  (1) Parallel / serial conversion control that generates various signals necessary for parallel / serial conversion in an I / O expansion method using parallel / serial conversion and restores the input serial signal to a parallel signal. An I / O expansion circuit having a circuit and a shift register that sequentially converts parallel data into serial data based on the above-described control signal, and outputs a signal group whose logic does not change while the circuit is energized When the serial data signal is restored to a parallel signal, the bit group in which the corresponding signal is stored is sampled multiple times after turning on the power to specify the logic, and then restored to parallel data for the subsequent parallel / serial conversion Sometimes it is determined whether restoration is successful or not based on whether the value of the signal group matches the specified value.

  (2) In the I / O expansion method of (1) above, model discrimination information and board information are input as a signal group whose logic does not change during energization of a circuit to be input as an input signal.

  (3) In the I / O expansion method of (1) above, an optional connection signal is input as a signal group whose logic does not change during energization of a circuit that inputs the input signal.

  (4) In the I / O expansion method of (1) above, the signal group whose logic does not change during the energization of the circuit that inputs the input signal is input to the most upstream side of the shift register (finally in the control sequence, to the control circuit). Assigned to the data input terminal of the shift register.

  As described above, when I / O is expanded by parallel / serial conversion using a shift register outside the CPU or ASIC, any bit (multiple bits) placed at a predetermined position in the parallel input (parallel signal group) ) Is fixed, and the level fixing itself uses a plurality of bits and is performed based on information unique to the machine such as board information and model information. At this time, for the plurality of bits whose levels are fixed, when a code is assigned, all are set to L and all are set to H. As a result, when all the data of the corresponding bit group is read and all are H, it is possible to detect that a disconnection or a short circuit has occurred in the serial transfer signal. Since the information of the corresponding bit group does not change while the power is on, it is possible to prevent erroneously taking in other extended input information by judging NG when a different logic is detected. In addition, since the bit group used for fixing the level is information necessary for performing the initial setting of the machine, the input group is not used unnecessarily, and the bit group used for fixing the level is effectively used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  SP1 ... serial / parallel conversion circuit, S1 ... first shift register, S2 ... second shift register

Claims (6)

First conversion means for converting a parallel signal group including a fixed signal group that does not change logic during energization at a predetermined signal position into a serial signal;
Second conversion means for sampling the serial signal and converting the serial signal into the parallel signal group;
A determination unit that determines that the conversion by the second conversion unit is successful when the fixed signal group is detected from the predetermined signal position of the parallel signal group converted by the second conversion unit;
A signal conversion device comprising:   The signal conversion apparatus according to claim 1, wherein the determination unit determines a conversion error when the fixed signal group is not detected.   3. The signal conversion apparatus according to claim 1, wherein the conversion unit includes an input unit that inputs the fixed signal group corresponding to destination information, model information, or board information of a device including the first conversion unit.   The signal conversion apparatus according to claim 1, wherein the conversion unit includes an input unit that inputs the fixed signal group corresponding to an option detection signal that detects an option of a device including the first conversion unit.   The input means inputs the fixed signal group constituted by N fixed signals from a head signal position constituting the parallel signal group to an N (N: integer, N ≧ 2) -th signal position. Any one of the signal converters 1 to 4.   The determination means stores N fixed signals constituting the fixed signal group, and N signals from the head signal position of the parallel signal group converted by the second conversion means to the signal position of the N program. 6. The signal conversion apparatus according to claim 5, wherein the signal conversion apparatus determines that the conversion by the second conversion means is successful based on a match between the fixed signal of N and the N fixed signals constituting the stored fixed signal group.

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