JPS60212025A - Master-slave type level converting circuit - Google Patents

Abstract

PURPOSE:To realize low-power, high-speed operation and a wide power supply voltage range by applying signals with different phases to the combination of master and slave level converters. CONSTITUTION:When signals phiM, phiS' are at a Vdd level, signals phiM', phiS are at a VQQ level, outputs QM, QS' are at the Vdd level and signals QM', QS are at the VSS level at the initial state, NMOSTs 11, 12, 18, 20 are turned on, NMOSTs 14, 15, 17, 21 are turned off PMOSTs 10, 19 are turned off and PMOSTs 13, 16 are turned on. When the signal phiS changes to the Vdd level and the signal phiS' changes to a VQQ level, the T16 is turned off, the T19 is turned on, the output QS rises to the Vdd level from the VSS, the T17 is turned on and the output QS' falls down from the Vdd to the VSS level. As a result, the T12 is turned off and the T15 changes to the on-state. When the signal phiM changes to the VQQ level and the phiM' changes to the Vdd level, the T10 turns on and the T13 turns off, the output QM' rises to the Vdd level, the T14 changes to the on-state, and the output QM falls down to the VSS. As a result, the T18 is turned off and the T21 changes to the on-state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to small amplitude circuits that are composed of complementary field effect transistors (hereinafter abbreviated as CMO5) and in which different signal levels coexist. This invention relates to a level converter that converts a signal to a large amplitude.

[Background of the invention]

The development of CMO8 circuits has been remarkable in recent years, and the first feature of CMO8 is low power consumption. The second reason is that the operating voltage range is wide.

For these reasons, CMO5 is mostly adopted in micro-sized devices that operate on batteries, but low-power liquid crystal 1 display devices are often used as display devices in these micro-sized devices. Since this liquid crystal display device requires a driving voltage of 3 to 5 µm, most of the circuit usually operates at the battery voltage (1 µm).
, 5V), and the liquid crystal drive circuit is often operated with a high voltage power source obtained from a booster circuit, but in this case
A level converter is required to supply signals from the V system to the high voltage system. In addition to LCD drives, for example, in electronic watches, to achieve even lower power consumption, a step-down circuit is used to create a voltage lower than the battery voltage, and parts that operate at a relatively high frequency are operated at a low voltage. In some cases, the remaining part is driven by battery voltage, and in this case, a level converter is also required to supply a signal from the low voltage part to the battery voltage part. Level converters used in this way must be able to operate with sufficiently low power.

[Prior art and problems]

FIGS. 1(a) and 16(b) are circuit diagrams and waveform diagrams showing typical examples of level conversion circuits according to the prior art,
First P-channel/I/MOS transistor (hereinafter PMO
The sources of the first PMO8T1 and the second PMO8T2 are connected to the high potential side dd of the power supply, and the drain of the first PMO8T1 is connected to the drain of the first ON channel yuMO8) run lister (hereinafter referred to as NMO8T) 3 and the second PMO8T2. NMOS of
connected to the gate of the second PMOS T4;
The drain of the second NMOS T 4 is connected to the drain of the second NMOS T 4 and the gate of the first ONMO 8T, and the sources of the first and second NMOS T 6.4 are connected to the low potential side Vas- of the power supply. Ru. the first and second PMs;
The gate of O8T1.2 has Vad and a level ■ threat higher than Vmm. Signals φ, φ moving between Vad and V are applied to the drain of the first or second PMO8T[,2.
ss to obtain an output signal. The operation of this circuit is as follows.

When the intervention force signal φ is at the vdd level, and therefore φ is at the vQQ level, the first PMO 8T1 is off and the second Ω PMO 8T2 is on. 1st and 2nd l)
Connect the drains of M OS T 1.2 to A and B, respectively.
Then, the potential at point A is XX, and the potential at point B is Vdd, so that the tenth NMO8T3 is on and the second NMO8T4 is off. In this state, there is no current path between Vad and Hatake s, and no power is consumed.

Next, the signal φ changes from Vad to the VQQ level, and therefore the signal φ
Suppose that the level changes from VQQ to ■dd level. Said second
The PMO 8T2 is turned off, but since there is a stray capacitance at the point B, the potential at the point B is maintained at Vad, and therefore the first ONMO 8T3 remains on. Therefore, the first PMO8T1, which has turned from off to on, competes with the first NMO8T5, which is also in the on state, and the on-resistance of the first PMO8T10 increases
If it is sufficiently smaller than the on-resistance of O8T6, the potential of the point A will go to vdd, so the second ONMO8T4 will be turned on, the point B will be at the Van level, and the first N
MO8T3 is turned off and the point A becomes completely at the vdd level, completing the inversion operation.

As is clear from the above explanation of the operation, there is a competition between PMO8T and NMO8T, both of which are in the on state, during the inversion operation, and if the divided voltage appearing at the drains of both at this time is not large enough, the inversion operation will not be performed. It takes a long time to complete the inversion operation, and power consumption increases. Therefore, in the competitive state, the on-resistance of PMO8T is N
It is necessary to design the on-resistance to be sufficiently smaller than the on-resistance of MO3T. However, the amplitude of the signal that drives PMO8T is small, and the amplitude of the signal that drives NMO8T is large, so the on-resistance of MO8T is inversely proportional to the square of the gate-source voltage minus the threshold voltage. If you think about it, PMO8T must be designed to have a sufficiently large channel width and gm, and NMO8T must be designed so that the channel length is sufficiently long and gm is small.

There are four possible problems that arise here. For one thing, the above design tends to increase the size of both PMO8 and I'JMO8T, which results in poor layout consistency with other logic circuit parts, and at the same time, the use of a large number of them also affects the chip size. give.

Second, as the size of PMO8T increases, its input capacity also increases. Therefore, unless the size of the transistor that drives the PMO8T is increased, the delay time will increase, the high speed will be lost, and the power consumption will increase. Furthermore, an increase in the input capacitance of PMO8T causes an increase in the power required to charge and discharge this input capacitance, which becomes a problem when the signal cycle is fast.

Next, if the size of NMO8T is increased, the input capacity will also increase, which will lead to an increase in power. Moreover, this input capacitance will drop to points A and B in FIG. 1, causing an output delay.

Especially when points A and B fall, NMO8T has a high on-resistance.
Since the discharge occurs through the , the fall time becomes extremely poor and high speed performance cannot be expected. Fourth, essentially PMO8T and NM
Since there is a competition state of O8T, it is inevitable that a direct current (DC) current will occur during reversal, and a transient current will flow.

Therefore, when designing the circuit shown in Figure 1, the optimal design must be carried out after considering the above items.
It is difficult to satisfy all requirements for high speed. Furthermore, even if an optimal design is made for a given set of conditions, it will be completely meaningless if the usage conditions change. For example, V@(1, Vss
Even if optimal operation is guaranteed under certain conditions, if ■■ changes, the operation is no longer guaranteed. On the other hand, if we try to guarantee operation over a wide range of operating voltages, we will probably have to significantly degrade other performance.

OBJECT OF THE INVENTION As mentioned above, the prior art has many drawbacks and has had to be used under limited conditions and with limited performance.

An object of the present invention is to provide a level converter that eliminates the drawbacks of the prior art and makes full use of the inherent characteristics of 5CMO8, such as low power consumption, high-speed operation, and a wide power supply voltage range.

[Structure of the invention]

The configuration of the present invention is such that signals having different phases are applied to the combination of the mask and slave level converters.

[Embodiments of the invention] A detailed description will be given below based on the drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention, in which the first P
The source of MO8T10 is connected to ■dd, and the drain is connected to the drain of the first NMO8T11 and the third ONMO3T1.
It is connected to the gate of No. 4 and the gate of No. 8 ONMOS T21. The source of the first NMO8T11 is the second NM
connected to the drain of O8T12, and the second NMO8T
The gate of No. 12 is the third PMO8T, the drain of No. 16, the drain of No. 5 ONMO8T17, and the drain of No. 7 NMO8T20.
connected to the gate. The source of the fifth NMO8T17 is the NMO8T shown in FIG.

Connected to the drain of 18. NMO8T1 in FIG.
The gate of No. 8 is connected to the drain of the second PMO8T13, the gate of the first ONMO8T11, and the drain of the third NMO8T14.

The sheath of the third NMO8T14 is the fourth ONMO8T
15, and the gate of the fourth ONMO8T15 is connected to the drain of the fourth -PMO8T19 and the fifth ONMO8T19.
The gate of the NMO8T17 and the seventh NMO8T20
The source of the seventh NMO8T20 is connected to the drain of the eighth NMO8T21. Said second, third and fourth PMO8T13.16.19
The source of is connected to ■dd, and the second, fourth, sixth -
; the source of the eighth NMO8T12.15.18.21 is connected to Vss. The first PMO, 5T10, the second PMO8T13, the third PMO8T16, the fourth PMO
Input signals φ0, φ8, φ8, and φ8 are applied to the gate of MUSTM9, respectively.

Note that the connection of the substrates of each of the above transistors is not particularly specified, but in the case of PMO8T, it is generally connected to Vda, and in the case of NMO8T, it is connected to Vl.

FIG. 3 shows the operation of the embodiment shown in FIG. 2. The wave is Vdd.
and VQQ, and the phase of φ8 and stone is 180° behind that of φ and 7τ, respectively. Except in special cases, flip-flops are recognized to exist in parts that operate at VQQ level in most circuits, and most CMOS flip-flops are master-srap type, so it is easy to obtain signals related to the above. be.

To explain the operation of the circuit shown in FIG. 2 with reference to FIG. 3, first, in the initial state, the signals φ0 and φ8 are at the ■dd level,
77, φ6 is VQQ level, and output Q M s Qs
Power VddL/to #, Q M s Q m Power Vss
level. In this state, the first
2nd, 6th, 7th NMO8T11.12.18.20
are in the on state, and the third, fourth, fifth, and eighth NMs
O8T14.15.17.21 is off. Further, the first and fourth PMO8j10.19 are off, and the second and third PMO8T13.16 are on. Here, the signal φ8 changes from the VQQ level to the ■dd level, and the signal φ8 changes from Vda V4 pv to V. If the level changes, the third PMO8T16 will be turned off and the fourth PMO8T19 will be turned on. At this time,
Since the eighth ONMO 8T21 is in the off state, the output Q rapidly rises from Vsa to the dd level.

Then, the fifth NMO3T17 turns on, and the sixth NMO8T18 remains on, so the output Qll rapidly falls from Vaa to the Vss level. As a result, the second ONMO8T12 turns off and the fourth NMO8T15 turns on. At this time, the signal Q is in a floating state, but the Vsm state is maintained due to the memory effect due to the stray capacitance. The output QM remains at the problematic (Va,i level).

Next, when the signal φyo changes from Vda to VQQ level and G changes from VIIQ to ■dd level, the first P
MOSTlo from off to on, said second PMO8T
I6 turns from on to off. At this time, the second ONM
Since O8T12 is in the off state, the output Qa quickly rises to the ■dd level, and therefore the third ONMO8T1
4 turns on.

At this time, since the fourth ONMO 8T15 is in the on state, the output Q rapidly falls to Vga. As a result, the sixth ONMO8T13 changes from on to off.
NMO8T21 turns from off to on. At this time, the output terminal Qll becomes a floating state, but the Vsi level is maintained due to the memory effect due to the stray capacitance that falls on Qll. Thereafter, the same operation is repeated, and when the signal φ falls from Vda to VQQ, the output Q changes from Vdd to Vas.
, Q changes from Vss to Vda, and then the signal φ
When YO rises from VQQ to Vda, the output, QM
changes from Vas to Vda, K Q M changes from Vda to Van, and returns to the initial state.

As is clear from the above description, there is no contention condition at any point, so there is no need for the size of each transistor to be significantly different from normal ones. Therefore, the stray capacitance in each part is sufficiently small, ensuring high-speed operation and at the same time ensuring sufficiently low power. Also, since there is no race condition, VQQ and ■■
The relationship provides a wide degree of freedom, and there are no limitations on the voltage range that can be used.

Although the circuit shown in FIG. 2 can be used satisfactorily for input signals having a relatively fast period, if the input signal period becomes slow, there is a risk that the limit of the memory effect due to stray capacitance will be exceeded. Of course, a large capacitor may be added to each output terminal, but a more aggressive method is also possible. The invalidation of the memory effect described above is due to the following reason.

For example, in the initial state of FIG. 3, it is the output Q8 whose potential is maintained due to the memory effect. That is, the fourth PMO8T19 is off because the input signal φ8 is at the ■dd level. Also, the 7th ONMO8T20
is on because the output Q is at the ■dd level, but the eighth ONMO8T21 is turned on because the output Q is at the ■dd level.
It is turned off because of the I level, so the output Q is maintained at Vllll+ due to the memory effect of the capacitance.

On the other hand, since leakage exists in semiconductors, and MO8T has an exponential current region called the so-called tail phenomenon,
The charge on the memory capacitor changes over time.

In the case of this embodiment, the problem is the inflow of current from ■dd, which causes the potential that should be at the Vsi level to become
The problem is that it rises in the dd direction. The magnitude of this current is extremely small, ranging from picoamperes to several nanoamperes. Therefore, it is sufficient to provide a current path to offset this current.

FIGS. 4(a) and 4(b) are circuit diagrams of embodiments in which the above points are improved, and only the output Q is shown for simplicity, but other output terminals are also shown. Similar means are provided. FIG. 4(a) shows the simplest case, in which a large resistance component 61 (but sufficient to overcome leakage) is inserted between the output terminal and ViaO. In this case, current flows through the resistor component 31 even when the output terminal is at the dd level, resulting in an extremely small increase in current consumption. Therefore, FIG. 4(b) shows an embodiment that improves this point, and a resistance component 62 is inserted between the connection point of NMo8T20 and NMo8T21 and Vsa. In this way, when the output Qll is at the ■dd level, the output Q8 will be at Vg.
Because of the s level, NMOS T20 is in the off state,
Wasted current will no longer flow.

Figure 5 shows an embodiment of the present invention that is different from Figure 4 in that it requires four large resistance components, but this has been reduced to two. It is something. Said PMO8T19.

When both NMo5T21 are off, NMOS T18 is on, so the output Q8 is fixed to Vss via NMOS T20, the resistance component 33, and NMo5T18. On the contrary, the PMO8T16 and NMo8T18 are both K,
t 7 (1') Time Hatm Note N M OS T21
is turned on, so the output Q8 is in the on state NMo8
It is fixed to Via via T17.21 and the resistance component 36. Similar means may also be provided on the mask side.

FIG. 6 is a circuit diagram of an embodiment of a high resistance component that has been improved differently from FIGS. .

Next, when it is necessary to convert the levels of two or more different signals, depending on the conditions, it may be possible to omit the circuit for signals with a slow period. For example, when level converting the two signals φ1 and φ2 in the waveform diagram shown in FIG.
When the level is converted by the master rape type level conversion circuit shown in the figure, the QMI shown in Fig. 7 is SQMI, Q, □, Q, □.
is obtained.

In the circuit shown in Fig. 8, which has been improved differently from the younger brother Figs. Q□ (not shown) rises rapidly without entering into a contention state, and since this fNMosTs2 is in the on state, the output Q yo.

falls rapidly. Conversely, when the signal φ2 rises, the NMO8T51 is on and the NMO8T52 is off, so the output QM2 rises rapidly. Output QM2,
Q+B is brought into a floating state every time the signals Qll and QH reach the Vsa level, but this point is as described above, and if necessary, the steps shown in FIGS. 4 to 6 may be carried out.

Further, if there is a sufficient delay between the signals φ and φ2 as shown by the broken line, the input terminals CK QMI and DK
QMI may also be applied.

Note that FIG. 9 is a modification of the embodiment shown in FIG. 2, and in this embodiment, the first, second, third, and fourth PMO8T1Q
, PMO8T61.62.6 in parallel with 16.16.19
6.64 are connected, and these PMO8T61.
The gate sides of 62, 66, and 64 are PMO8T1, respectively.
It is connected to the drain side of 3.10.19.16 as shown.

Effects of the Invention] As is clear from the above explanation, according to the present invention, low power consumption,
It is possible to obtain high performance in all aspects such as high speed, consistency, and power supply voltage characteristics that could not be obtained with conventional technology, and the implementation effect is extremely large.

In the above explanation, the symbols V@(1, Vss) were used, but
For example, it should be noted that veo may be the battery voltage and vl may be the boosted voltage. Furthermore, in the above explanation, the high potential side of the power supply is used as a reference, but if the low potential side of the power supply is used as a reference, PMO8T and NMOST should be replaced [
It is obvious that it would be better to reverse the power supply relationship. It is also clear from FIG. 3 that φY, φ1, φ8, and φS do not necessarily have to have a phase of 180''.

4. Brief explanation of the drawings Figures 1(a) and 1(b) are circuit diagrams and waveform diagrams showing the prior art, Figure 2 is a circuit diagram showing an embodiment of the present invention, and Figure 3 is a circuit diagram showing the prior art. The operating waveform diagram of one circuit shown in Fig. 2, Fig. 4 (a), Fig. 4 (b), Fig. 5, Fig. 6, and Fig. 8 are each further improved versions of the embodiment shown in Fig. 2. 7 is a waveform diagram of FIG. 8, and FIG. 9 is a circuit diagram showing an embodiment of the present invention according to a modification of FIG. 2.

Figure 2 Figure 3 Figure 6 Figure 8 Figure 7

Claims (1)

[Claims] Four MO8Ts of the first type, Pl, P2, P6, P4 and eight MO8Ts of the second type, N1, N2, N6, N4,
N5, N6, NZ, N8, and the MO8T(Pl)
and means for connecting the drains of the MO8Ts (N1) and the gates of the MO8Ts (N3) and (N8);
2) and the drain of (N5) and the MO8T (N1)
and means for connecting the gates of (N6); The drain of MO3T (P3.> and (N4) and the M
means for connecting the gates of the MO8Ts (N2) and (N7); means for connecting the drains of the MO8Ts (P4) and (N7); and the gates of the MO8Ts (N5) and (N4); source and (N2)
means for connecting the drain of the MO8T (N3) and the drain of the MO8T (N4); means for connecting the source of the MO8T (N5) and the drain of the MO8T (N6); ) source and (N
8) and means for connecting the drain of the MO8T (Pl
), (P2), (P6), (P4) to the first power supply line;
), (N6), (N8) to the second power supply line, and the MO8T(Pl), (P2), (
An input signal having the level of the first power line and the level of the third power line is applied to the gates of each of the MO8Ts (Pl), (P2), (P3), (P4). 1. A master rape type level conversion circuit configured to obtain an output signal having the first power supply line level and the second power supply line level at the drain of the master rape type level conversion circuit.