JPS60217723A - Level converting circuit - Google Patents

Abstract

PURPOSE:To improve the matching with other circuit parts with low power and high speed operation by combining logical circuits to a CMOS constitution level converter so as to control the converter thereby eliminating the contention state of the converter without requiring considerable change of element size. CONSTITUTION:An MOS13 is turned on when an MOS11 is turned on, but since an MOS15 is turned off, no contention is caused. Further, the MOS13 is turned off when the MOS15 is turned on and no contention is caused. On the other hand, both MOS14, 16 are turned on when an MOS12 is turned off and the potential at a point Q falls down rapidly to Vss. Since an output X of a NAND17 rises when the MOS16 is turned off, the potential at the point Q falls down sufficiently. When the MOS16 is turned off, the point Q reaches the floating state and the low potential is kept by the floating capacitance at the point Q. Thus, the desired operation with no contention is attained in this way.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to small amplitude signals in a circuit that is composed of complementary field effect transistors (hereinafter abbreviated as CMO8) and in which different signal levels coexist. It is related to a level converter that converts a signal to a large amplitude.

[Background of the invention]

Although the development of CMO8 circuits has been remarkable in recent years, the first feature of 0MO3 is low power consumption. The second reason is that the operating voltage range is wide. For these reasons, most of the CMO8 devices are used in ultra-small devices that operate on batteries, but low-power liquid crystal display devices are often used as display devices in these ultra-small devices. Since a liquid crystal display device requires a driving voltage of 3 to 5V, most of the current gamma circuit is operated by battery voltage (about 1.5V), and the liquid crystal drive circuit is sometimes operated by a high voltage power source obtained from a booster circuit. In most cases, a level converter is required to supply the signal from the 1.5 V system to the high voltage system. Furthermore, in order to achieve even lower power consumption not only in LCD drives but also in electronic watches, for example, a step-down circuit is used to create a voltage lower than the battery voltage, and parts that operate at a relatively high frequency are operated at a low voltage. , the remaining part may be operated by battery voltage, and in this case also a level converter is required to supply a signal from the low voltage part to the battery voltage part. Level converters used in this way must operate with sufficiently low power.

[Prior art and problems]

FIG. 1 is a circuit diagram showing a typical example of a level conversion circuit according to the prior art, in which a first P-channel MOS transistor (hereinafter referred to as PMO8T) 1 and a second PMOS T
The source of the first PMO8T1 is connected to the high potential side vdd of the power supply, and the drain of the first PMO8T1 is connected to the first ON channel MO
8) The drain of the transistor (hereinafter referred to as NMO8T) 6 is connected to the gate of the 29th NMOS T4, and the drain of the second PMO8T2 is connected to the second ONMO8T4.
The drain of the ONMOS T3.4 is connected to the gate of the first NMO8T, and the sources of the first and second ONMOS T3.4 are connected to the low potential side Vllll+ of the power supply.

Signals φ, φ that move between VDD and a level VQQ higher than 88 are applied to the gates of the first and second PMOS T1.2, and the first and second PMOS T1.
At the drain of 1.2 we get an output signal that moves between Vdd and Vms. The operation of this circuit is as follows. When the gold input signal φ is at Vdd level, therefore, φ is at VQQ level, the first PMOS T1 is off and the second PMOS T1 is off.
PMO8T2 is on. First and second PMOS
If the drains of T 1.2 are Q and Q, respectively, the point Q
The potential at point Q is VI+8, and the potential at point Q is vdd.
Therefore, the first ONMOS T 6 is on and the second NMOS T 4 is off. In this state v
There is no current path between dd and V, and no power is consumed. Next, assume that the signal φ changes from the Vdd level to the vQQ level, and therefore the signal φ changes from the ■, Q level to the ■dd level. The second PMOS T2 is turned off, but since there is a stray capacitance at the point Q, the potential at the point Q is maintained at Vdd, and therefore the first ONMO 8T3 remains on. Therefore, the first PMO8T1, which has turned on from off, competes with the first NMO8T5, which is also in the on state, and the on-resistance of the first PMO3T1 increases.
If it is sufficiently smaller than the on-resistance of NMOS T3, the potential of the point points to Vdd, and therefore the second ONMO8T
4 is turned on, the point Q becomes the Vgg level, the first ONMOS T 3 is turned off, and the point Q becomes completely the Vdd level, completing the inversion operation.

As is clear from the above explanation of the operation, there is a competition between PMO8T and NMO8T, both of which are in the on state, during the inversion operation, and if the divided voltage appearing at the drains of both at this time is not large enough, the inversion operation will not be performed. It takes a long time to complete the inversion operation, and power consumption increases. Therefore, in the competitive state, the on-resistance of PMO8T is NM
It is necessary to design the on-resistance to be sufficiently smaller than the on-resistance of the OST. However, the amplitude of the signal that drives PMO8T is small, and the amplitude of the signal that drives NMO8T is large, so the on-resistance of MOS T is inversely proportional to the square of the gate-source voltage minus the threshold voltage. If you think about it, PMO8T must be designed to have a sufficiently large channel width and gm, and NMO8T must be designed so that the channel length is sufficiently long and gm is small. There are four possible problems that arise here. One is that the above design tends to increase the size of both PMO8 and NMO8T, so the layout consistency with other logic circuit parts becomes poor, and at the same time, the use of a large number of them also affects the chimp size. . Second, as the size of PMO8T increases, its input capacity also increases. Therefore P
The size of the transistor that drives the MO8T is also large (otherwise, the delay time will be longer, high speed will be lost, and the power consumption will also increase. Also, the increase in the input capacitance of the PMO8T is due to the need for charging and discharging this input capacitance. The power increases,
This becomes a problem when the signal period is fast. Next, NMO8T
Increasing the size of will also increase the input capacity,
The direction is that the power increases. Moreover, this input capacitance will drop to points Q and Q in FIG. 1, causing an output delay. Especially when the collapse Q and Q fall, NMO8 has high on-resistance.
Since the discharge occurs via T, the fall time becomes extremely poor and high speed cannot be expected. Fourth, essentially PMO8T and N
Since there is a MO8T competition state, a DC-like path is always created during inversion, and it is inevitable that a current will flow in the transient 1.

Therefore, when designing the circuit shown in Figure 1, the optimal design must be carried out after considering the above items.
It is difficult to satisfy all requirements for high speed. Furthermore, even if an optimal design is made for a given set of conditions, it will be completely meaningless if the usage conditions change. For example, even if optimum operation is guaranteed under certain conditions of ■QQ, ■, the operation is no longer guaranteed if Vss changes. On the other hand, if you try to guarantee operation over a wide range of operating voltages, you will probably have to significantly degrade other performances.

[Purpose of the invention]

As mentioned above, the conventional technology has many drawbacks and has to be used under limited conditions and with limited performance.

An object of the present invention is to eliminate the drawbacks of the prior art and provide a level converter that fully utilizes the inherent characteristics of 5CMO8, such as low power consumption, high speed operation, and wide power supply voltage range.

[Embodiments of the invention]

Hereinafter, a detailed explanation of the present invention based on the drawings will be given.
The figure shows one embodiment of the present invention, in which the first PMO8T11
The drain of the second PMO8T12 is connected to the drain of the first NMO8T16, the gate of the second NMO8T14, and one input terminal of the second NAND gate 18, and the drain of the second PMO8T12 is connected to the drain of the second NMO8T14 and the second NAND gate 18.
The gate of NMO8T13 and the first NAND gate 17
is connected to one input end of the The drain of the third NMOS T15 is connected to the source of the first NMOS T13, the gate is connected to the output terminal of the first NAND gate 17 and the remaining input terminal of the second NAND gate, and the source is connected to the output terminal of the first NAND gate 17 and the remaining input terminal of the second NAND gate. Connected to Vss. 4th NMO8T
The drain of 1.16 is connected to the source of the second NMO8T14, and the gate is connected to the output terminal of the second NAND gate and the remaining input terminal of the first NAND gate 17. The source is connected to Vz. Said first,
The source of the second PMOS T 1.2 is connected to Vdd.

FIG. 3 is an operational waveform diagram of the embodiment shown in FIG.
The signals φ and φ applied to the gates of the first and second PMO8T11.12 are signals having the levels of Vdd and QQ, and when the signal φ falls (therefore, when φ rises) The potential of the drain Q of the first PMO8T11 rises to vdd after a certain delay. Then, the second PMO
The drain Q of 8T12 falls to V81. Therefore, the output X of the first NAND gate 17 rises to Vdd, and then the output Y of the second NAND gate 18 rises to Vllg.
Falling down. In this series of operations, the first PMO8
At the time when T11 is turned on, the first NMO8T
13 is on, but the third ONMO8T15 is off, so no conflict occurs. Also, the third ONMOS T
15 is turned on after the first NMO8T13 is turned off, so there is no conflict here either. On the other hand, since the second and fourth NMO8T14.16 are both on at the time when the 2CPMO8T12 is turned off, the potential at the point Q rapidly falls to Vllg. Furthermore, the fourth ONMOS T16 is turned off only after the potential of Q falls and therefore the output X of the first NAND gate 17 rises, so the potential of Q can sufficiently fall during this period. Here, when the NMO8T16 is turned off, the point Q becomes a floating state, but Q
A low potential is maintained by the floating capacitance. If there is a risk that the potential at point Q may fluctuate due to leakage, etc., a DC path sufficient to overcome leakage may be provided between point Q and vBIl, but as shown by the broken line in FIG. Efficiency is better if a resistance component 19.20 is provided between the drains M and N of the third and fourth NMO8T15.16 and V58.

FIG. 4 shows another embodiment of the present invention, in which NOR gates 26.18 are replaced with NAND gates 17.18 in FIG.
24, one input terminal of each of the NOR gates 23 and 24 is connected to an inverter 21 and 22, respectively.
Connected to Q and Q via. FIG. 5 is an operational waveform diagram of the embodiment shown in FIG. 4, and although there are some differences, it is clear that the same effect as explained with respect to FIG. 3 can be obtained. Further, the floating state is as described above and will not be described here. (The same applies to the following embodiments.) Next, FIGS. 6 and 7 are embodiments in which the embodiment shown in FIG. 4 is logically converted and replaced with a NAND gate and an inverter. There are some differences in waveforms, but basically the same effect is obtained. Moreover, FIGS. 8 and 9 show an example in which the embodiment shown in FIG. 2 is logically converted and replaced with an inverter and a NOR gate, and is basically the same as FIG. 2. Yes.

In the above embodiment, to simplify the explanation, only the delay time is shown, ignoring the rise and fall times of the operating waveform, but in reality, the threshold level of the logic gate and the threshold level of the transistor are shown. Since these are different, it is necessary to carefully examine the rise and fall times. It is good if there are many delayed parts as in the embodiment shown in FIG. 8, but if there are few delayed parts as in the embodiment shown in FIG. The NAND gate 1
) There is a risk that the NMO8T13 remains on at the time when the output X of

Regarding this point, it is possible to solve one problem by changing the size of the transistors constituting the NAND gates 17 and 18. Furthermore, if we consider actively adopting such a method, the embodiment shown in FIG. 10 can be adopted. That is, in FIG. 10, inverters 61, 62.
If the configuration is configured so that the delay of 66.64 is sufficiently large, the first
As is clear from the waveform shown in FIG. 1, the same effects as in the previous embodiment can be obtained. It can also be seen that the delay may be constructed from resistance components 41, 42 and stray capacitance as in the embodiment shown in FIG.

To summarize the features of the present invention from the above embodiments, the present invention applies a signal that is in phase with the signal appearing at the point Q and delayed in phase to the gate of the third NMO3T15,
It can be seen that the feature is that a signal which is in phase with the signal appearing at the point Q and whose phase is delayed is applied to the gate of the fourth NMO8T16.

〔Effect of the invention〕

As described above, the level conversion circuit of the present invention does not require a large change in transistor size because there is no competition condition.
Good compatibility with other circuit parts, low current consumption,
It also has excellent voltage characteristics and high speed, and its implementation effects are extremely impressive.

In addition, as shown in FIG. 14, the first and second PM, 03
3rd and 4th PMOS T51 in parallel with T11.12
．． It is also possible to make changes such as connecting 52 and connecting each gate to the points Q and Q.

Furthermore, the resistance component lowered at the points M and N may be connected in common (between M and N as shown in FIG. 14).

Further, in the above description, connection of the substrate of each transistor was not described, but it is up to the user to connect it to the power supply, to the source, or to leave it open. Furthermore, although each of the above-mentioned embodiments has been shown in the case of a level converter using DD as a reference, it is obvious that if Vss is used as a reference, the configuration can be changed based on the same concept.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are circuit diagrams and waveform diagrams showing the prior art. 2 to 9 show an embodiment of the present invention, FIGS. 2, 4, 6, and 8 are circuit diagrams, and FIGS. 3, 5, and 7
Figure 9 is a waveform diagram. FIGS. 10 and 11 are circuit diagrams and waveform diagrams showing other embodiments of the present invention. FIG. 12 and FIG. 13 are a schematic diagram and a waveform diagram showing still another embodiment. FIG. 14 is also a circuit diagram showing another embodiment of the present invention. 11...First PMO8T. 12...Second PMO8T. 16...1st ONMO8T. 14...Second NMO8T. 15...3rd ONMO8T. 1゛;Rare...4th ONMOS T0 Fig. 2 Fig. 3 Fig. 6 Fig. 7 Fig. 8 Fig. 9 Fig. 10 Fig. 11

Claims (1)

[Claims] The first type MOS) transistor (hereinafter abbreviated as PMO8T) and the second type MOS) transistor (hereinafter abbreviated as NMO8T)
(abbreviated as T), and the drain of the first PMO8T is connected to the drain of the first NMO8T and the second ONMO8T.
means for connecting the source of the first NMO8T to the drain of the third ONMO8T;
means for connecting the drain of a second PMO8T to the drain of the second ONMO8T and the gate of the first ONMO8T; and means for connecting the source of the second NMO8T to a fourth NMO8T;
means for connecting to the drain of 8T, and the first and second P
means for connecting the source of the MO8T to a first power supply line; means for connecting the sources of the third and fourth ONMO8T to a second power supply line; means for applying a delayed signal; and means for applying a delayed signal to the gate of the fourth ONMO8T;
has means for delaying and applying a signal appearing at the drain of the PMO 8T, and a signal φ that operates at the level of the first power supply line and the third power supply line is applied to each of the gates of the first and second PMO 8T. A level conversion circuit characterized by applying φ and φ.