JPS60212013A - Multi-stage amplifier - Google Patents
Multi-stage amplifierInfo
- Publication number
- JPS60212013A JPS60212013A JP6800184A JP6800184A JPS60212013A JP S60212013 A JPS60212013 A JP S60212013A JP 6800184 A JP6800184 A JP 6800184A JP 6800184 A JP6800184 A JP 6800184A JP S60212013 A JPS60212013 A JP S60212013A
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- JP
- Japan
- Prior art keywords
- amplifier
- amplifiers
- gain
- output
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は多段増幅器に関し、特に集積回路に適した可変
利得の多段増幅器に関する。TECHNICAL FIELD The present invention relates to a multistage amplifier, and more particularly to a variable gain multistage amplifier suitable for integrated circuits.
（従来技術）
従来から可変利得増幅器は広範囲の入力レンジに１り一
定の出力にする場合等に広く用いられている。従来の可
変利得増幅器には何らかの可変インヒータメス素子ある
いは可変相互コンダクタンス素子を用いて利得を可変し
ていたが、この可変素子のダイナミックレンジは小さく
、従って広範囲の入力レンジに亘り歪なく増幅するのは
困難であった。これに対して、多段に亘り可変利得増幅
器を縦続接続し、各段の利得を各々制御するディレード
ＡＧＣを用いる手法があり、歪や雑音の点で前記よりは
改良されるものの十分とはいえないのが現状であった。(Prior Art) Variable gain amplifiers have been widely used to provide a constant output over a wide range of input ranges. Conventional variable gain amplifiers use some kind of variable in-heater female element or variable transconductance element to vary the gain, but the dynamic range of this variable element is small, so it is difficult to amplify over a wide input range without distortion. Met. On the other hand, there is a method using delayed AGC in which variable gain amplifiers are connected in cascade over multiple stages and the gain of each stage is individually controlled. Although this method is improved from the above in terms of distortion and noise, it is still not sufficient. This was the current situation.
第１図は従来のディレードＡＧＣ型の可変利得増幅回路
の一例のブロック図である。FIG. 1 is a block diagram of an example of a conventional delayed AGC type variable gain amplifier circuit.
入力端子１より入力された信号は可変利得増幅器２，３
．４で増幅され、そのまま出力端子６に出力されるか％
あるいは検波器５を介し出力端子７に出力される。通常
は出力端子６，７のいずれかが利用される。８はＡＧＣ
回路でアリ、検波器５の出力に応じて各可変利得増幅器
に与える制御電圧又は電流を決定する回路である。各段
の利得の配分は検波器５の出力に応じて予め定められて
いる。通常、弱入力時は信号対雑音比の点で初段の利得
を下げるのは得策でないので、後段から利得をしぼって
ゆくようにしておる。一方１強入力時にもし初段が利得
をもっていると、この段で過大入力のため歪んだり％あ
るいはさらに増幅されて次段で歪んだりしてしまうため
、所定の中入力持より初段をしばりこむようにしている
。これは前記ＡＧＣ回路８の中に実質的にコノパレータ
の役を果す回路（トランジスタやダイオード）を入れ、
検波出力が所定値になったところで初段をしぼりこむこ
とにより実現している。このようなディレードＡＧＯは
広く用いられており、可変利得増幅器２〜３の間に周波
数変換段を挿入することも多い。ｔｆｃ段数も２〜６段
程度がある。The signal input from input terminal 1 is sent to variable gain amplifiers 2 and 3.
．． 4 and output as is to output terminal 6?
Alternatively, it is outputted to the output terminal 7 via the wave detector 5. Normally, either output terminal 6 or 7 is used. 8 is AGC
This circuit determines the control voltage or current to be applied to each variable gain amplifier according to the output of the detector 5. The distribution of gains in each stage is determined in advance according to the output of the detector 5. Normally, when the input is weak, it is not a good idea to reduce the gain of the first stage from the viewpoint of signal-to-noise ratio, so the gain is reduced from the subsequent stages. On the other hand, if the first stage has a gain when the input is over 1, the excessive input will cause distortion in this stage, or it will be further amplified and distorted in the next stage, so the first stage is made to be tighter than the specified medium input. . This involves inserting a circuit (transistor or diode) that essentially serves as a conoparator into the AGC circuit 8,
This is achieved by tightening the first stage when the detection output reaches a predetermined value. Such delayed AGOs are widely used, and a frequency conversion stage is often inserted between the variable gain amplifiers 2 and 3. The number of TFC stages also ranges from 2 to 6 stages.
さて、上記ディレードＡＧＣ回路には下記のような欠点
かめる。第一に、多段に亘って歪なく、かつ信号対雑音
比を悪化させないように利得をしばる際の各段のＡＧＣ
制御信号を最適に作り出すのが難しいこととばらつきや
すい点である。第二に、粂段に用いられる可変利得増幅
器の特性を高利得時と低利得時（強入力時）のいずれに
おいても最適化するのが難しい点である。これを具体的
な回路で説明しよう。Now, the delayed AGC circuit described above has the following drawbacks. First, the AGC at each stage is used to limit the gain so as to avoid distortion across multiple stages and to prevent deterioration of the signal-to-noise ratio.
The two points are that it is difficult to optimally generate control signals and that they tend to vary. Second, it is difficult to optimize the characteristics of the variable gain amplifier used in the comb stage both at high gain and at low gain (strong input). Let's explain this using a concrete circuit.
第２図は第１図に示す可変利得増幅器の一つの詳細回路
図である。即ち、第１図に示す可変利得増幅器２，３．
４のうちの一つの回路の詳細回路図である。FIG. 2 is a detailed circuit diagram of one of the variable gain amplifiers shown in FIG. That is, variable gain amplifiers 2, 3 .
4 is a detailed circuit diagram of one of the circuits.
この回路は、ＡＧＯ制御信号出力源としての電流源１６
がカットオフのときはトランジスタ１２と２０からなる
差動増幅器として動作し出力端子２３に出力を生ずる。This circuit includes a current source 16 as an AGO control signal output source.
When is cut off, it operates as a differential amplifier consisting of transistors 12 and 20 and produces an output at output terminal 23.
トランジスタ１２と２０のエミッタ間に拡抵抗１７があ
るため増幅匿伏はぼ抵抗２１と抵抗１７の比で与えられ
る。定電流源１４．１９はバイアス用であり、２２は電
源、１１は入力端子である。尚、トランジスタ１２，２
０ノヘースには図示して−ないが所定のバイアスがかけ
られているものとする。Since the expanded resistor 17 is present between the emitters of the transistors 12 and 20, the amplification concealment is given by the ratio of the resistor 21 and the resistor 17. Constant current sources 14 and 19 are for bias, 22 is a power supply, and 11 is an input terminal. Note that the transistors 12 and 2
Although not shown, it is assumed that a predetermined bias is applied to the zero phase.
電流源１６がオンとなり、ＡＧＣ制御信号が流れると、
ダイオード１５．１８が導通し、抵抗１７に並列にダイ
オード１５．１８の動抵抗が入ることになり、差動増幅
器の増幅器が上昇する。ダイここでｋはボルツマノ定数
％Ｔは絶対＠度、ｑは電子の電荷、Ｉｄは各ダイオード
に流れる電流でＡＧＣｆ１１１Ｊｉｌｌ信号の１／２で
ある。Ｉｄ＝１ｍＡとすると約２６Ωの抵抗値を呈し、
Ｉｄ＝Ｑ、１ｍＡで２６０Ωとなり、Ｉｄに応じて動抵
抗が可変でき。When the current source 16 is turned on and the AGC control signal flows,
The diode 15.18 becomes conductive, and the dynamic resistance of the diode 15.18 is introduced in parallel with the resistor 17, causing the differential amplifier to rise. Here, k is the Boltzmann constant %T is the absolute degree, q is the electron charge, and Id is the current flowing through each diode, which is 1/2 of the AGCf111Jill signal. When Id=1mA, it exhibits a resistance value of about 26Ω,
Id=Q, 260Ω at 1mA, dynamic resistance can be varied according to Id.
従って利得が可変できる。代表例としては一６ｄＢから
＋２０ ｄＢの制ｉ範囲のものがある。この回路におい
て１強入力時はＡＧＣ制御信号１６がカットオフとなる
ため、抵抗１７によりきわめて直線性のよい（歪の少な
り）増幅が可能でおり、その利得感抵抗２１と１７の比
で与えられるので、集積回路化したときにもばらつきが
少ない。Therefore, the gain can be varied. A typical example is one with a control range of -6 dB to +20 dB. In this circuit, the AGC control signal 16 is cut off when the input is a little over 1, so the resistor 17 allows amplification with extremely good linearity (less distortion), and the ratio of the gain sensing resistors 21 and 17 provides the Therefore, there is little variation even when it is integrated into an integrated circuit.
一方１弱入力のときはＡＧＣ制御信号によってダイオー
ドが導通するが、その動抵抗はＡＧＣ制御信号の値によ
るため、はらりき要素が増えてしまう。中入力のときは
、ＡＧＣ％１ＪＩｉ信号が小さな値となり、ダイオード
が比較的高い動抵抗を示すように制御されるが、トラン
ジスタ１２，２０゜Ｔ
ダイオード１５．１８の直線性は各々−＝２６ｍＶｐｐ
程匿しかない丸めせいぜい：ｔｏｏｍｖｐｐ以上の信号
が入力されると歪んでしまうことになるので、それより
も弱い入力で、すてにＡＧＣ制御信号をカットオフにな
今ようにしなければならない。このことは、信号対雑音
比を中入力に悪化させることになる。したがって第２図
の回路を複数個用いた第１図のようなディレードＡＧＣ
回路においては、各段ともその入力が１００ｍＶｐｐ
になる直前で各ＡＧＣ制御信号をカットオフにするよう
に制御する必要があるが、各段の利得のばらつき、ＡＧ
Ｃ制御信号を各段へ与えるＡＧＣ回路８のばらつき等の
ために、極めて難しいという欠点がある。On the other hand, when the input is a little less than 1, the diode becomes conductive due to the AGC control signal, but since its dynamic resistance depends on the value of the AGC control signal, the number of factors increases. At medium input, the AGC%1JIi signal has a small value and the diode is controlled so that it exhibits a relatively high dynamic resistance, but the linearity of the transistors 12 and 20°T and the diode 15 and 18 is -=26 mVpp, respectively.
At best, this is only a moderate rounding: If a signal of toomvpp or higher is input, it will be distorted, so it is necessary to cut off the AGC control signal with a weaker input. This will degrade the signal-to-noise ratio for medium inputs. Therefore, a delayed AGC like the one shown in Fig. 1 using multiple circuits shown in Fig. 2 can be used.
In the circuit, the input of each stage is 100mVpp.
It is necessary to control each AGC control signal to cutoff just before the
This has the drawback of being extremely difficult due to variations in the AGC circuit 8 that supplies the C control signal to each stage.
（発明の目的）
本発明の目的は、上記欠点を除去し１弱入力、中入力１
強入力のいずれにおいても出力信号の歪、雑音が小さく
、所望の利得と広いダイナミックレンジを有する多段増
幅器を提供することにある。(Object of the invention) The object of the present invention is to eliminate the above-mentioned drawbacks and to
It is an object of the present invention to provide a multistage amplifier having a desired gain and a wide dynamic range, with low distortion and low noise in the output signal for any strong input.
（発明の構成）
本発明の多段増幅器は、利得の異なる複数個の増幅器か
らなる増幅器群を複数群縦続接続しかり前記各増幅器群
毎に前記増幅器の少くとも１個づつを選択する制御手段
を接続したことを特徴として構成される。(Structure of the Invention) The multi-stage amplifier of the present invention includes a plurality of amplifier groups each having a plurality of amplifiers having different gains connected in cascade, and a control means for selecting at least one of the amplifiers for each amplifier group. It is composed of characteristics that have been achieved.
（実施例） 次に１本発明の実施例について図面を用いて説明する。(Example) Next, an embodiment of the present invention will be described with reference to the drawings.
第３因は本発明の一実施例のブロック図である。The third factor is a block diagram of an embodiment of the present invention.
この実施例はディレードＡＧＣ型可変利得多段増幅器で
おる。This embodiment is a delayed AGC type variable gain multistage amplifier.
利得の異なる増幅器３２〜３６を一つの増幅器群にする
。図面のブロック内の数字は利得（倍）を表わす。同様
に、増幅器３８〜４９及び４４〜４８でそれぞれ一つの
増幅器群を構成する。初段の増幅器３２〜３６０入力側
を入力端子３１に並列接続し、出力側を選択器３７に接
続し、増幅器３２〜３６のうちのどれか一つの出力が退
場れ次段の増幅器群へ入力されるようにする。次段の増
幅器３８〜４２の群２次次段の増幅器４４〜４８も同様
に入力側を前段の選択器３７あるいは４３の可動接点に
並列に接続する。このようにして複数の増幅器群を縦続
接続する。最終段の増幅器４４〜４８の群の各々の出力
側に選択器４９〜５３を接続する。従りて、増幅器４４
〜４８の出力のうち、選択器４９〜５３によって選択さ
れた出力が加算合成されて出力端子５５に出力され、ま
た検波器５４を介して出力端子５６と制御手段としての
選択決定回路５７へ出力される。選択決定回路ｉｔ、例
、ｔハ、コ／バレータト、このコンパレータの出力でア
ップダウンするカラ／りと、このカクンタによりアドレ
ッシノグされるＲＯＭとで構成される。Amplifiers 32 to 36 having different gains are made into one amplifier group. The numbers in the blocks of the drawing represent the gains (times). Similarly, amplifiers 38 to 49 and 44 to 48 each constitute one amplifier group. The input sides of the first stage amplifiers 32 to 360 are connected in parallel to the input terminal 31, and the output sides are connected to the selector 37, so that the output of any one of the amplifiers 32 to 36 is inputted to the next stage amplifier group. so that Similarly, the input sides of the secondary stage amplifiers 44 to 48 of the next stage amplifiers 38 to 42 are connected in parallel to the movable contact of the previous stage selector 37 or 43. In this way, a plurality of amplifier groups are connected in cascade. Selectors 49-53 are connected to the output side of each group of amplifiers 44-48 in the final stage. Therefore, amplifier 44
Outputs selected by the selectors 49 to 53 among the outputs of the outputs 48 to 48 are summed and combined and output to an output terminal 55, and also output to an output terminal 56 and a selection determining circuit 57 as a control means via a detector 54. be done. The selection decision circuit is made up of a comparator, a comparator whose output goes up and down, and a ROM which is addressed by this comparator.
選択決定回路５７は、検波器５４からの検波出力の大小
に応じて利得６上げ下げの方向を決定し。The selection determining circuit 57 determines the direction of increasing or decreasing the gain 6 depending on the magnitude of the detected output from the detector 54.
予め定められた手順に従って選択器３７．４３ 。Selector 37.43 according to a predetermined procedure.
４９〜５３の選択肢を決定する。これにより所望の利得
と利得配分を決定できる。前述のようにＲＯＭを使用す
る場合には、ＲＯＭのデータにより検波器５４の出力に
応じどの増幅器を使うかを決定することが容易にできる
。Decide on options 49-53. This allows the desired gain and gain distribution to be determined. When a ROM is used as described above, it is possible to easily determine which amplifier to use according to the output of the detector 54 based on the data in the ROM.
第４図は＃ｌ３１ｇに示す増幅器群の一つと切換器の一
つの具体的回路例の回路図である。FIG. 4 is a circuit diagram of a specific circuit example of one of the amplifier groups and one of the switches shown in #l31g.
第４図において、トランジスタ（６３，６４）。In FIG. 4, transistors (63, 64).
（６５，６６）、（６７，６８））（６９，７０）。(65,66), (67,68)) (69,70).
（７１，７２）の各組がそれぞれ一つの増幅器を構成す
る。各増幅器に接続するトランジスタ７３〜７７は切換
器を構成する。即ち、端子９２〜９６のうちの１個のみ
を選び１選ばれた端子に接続するベースのみに所定の電
圧を与え他のベース會低レベルとすることにより、前述
の５個の増幅器のうちの任意の１個のみに定電流源９９
の電流ｔｍすように選択される。各増幅器のコレクタは
カスコード増幅器を構成するトランジスタ７Ｂ、’１９
を介して負荷８８．８９に出力を生じ、端子９７゜９８
から出力される。ここで９０．９１は電源である。各増
幅器の利得は各トラ／ジメタ対のエミッタ動抵抗と各エ
ミッタに接続された各抵抗８０〜８７の和と負荷８８．
８９の比によって各々決定される。特に、集積回路にお
いて抵抗比は鞘層が良いため、各増幅器の利得も精度良
く作れる。Each set of (71, 72) constitutes one amplifier. Transistors 73 to 77 connected to each amplifier constitute a switch. That is, by selecting only one of the terminals 92 to 96 and applying a predetermined voltage to only the base connected to the selected terminal and setting the other bases at a low level, one of the five amplifiers mentioned above is Constant current source 99 for only one arbitrary
The current tm is selected so that the current is tm. The collector of each amplifier is a transistor 7B, '19, which constitutes a cascode amplifier.
output to the load 88.89 through the terminal 97°98
is output from. Here, 90.91 is a power supply. The gain of each amplifier is the sum of the emitter dynamic resistance of each transistor/dimetal pair, each resistor 80 to 87 connected to each emitter, and the load 88.
Each is determined by a ratio of 89. In particular, since the resistance ratio of the integrated circuit is good in the sheath layer, the gain of each amplifier can be created with high precision.
さらに、利得の高い増幅器においてはエミッタに接続さ
れる抵抗は小δ〈（又は０Ω）、従って、利得が大きく
なり、利得の低い単位増幅器では抵抗は大きくなるため
に強入力まで歪まないという利点をもつ。従ってＡＧＣ
回路に用いた場合、常に最適な利得／ダイナミックレン
ジを有する。Furthermore, in a high-gain amplifier, the resistance connected to the emitter is small δ (or 0Ω), so the gain is large, and in a low-gain unit amplifier, the resistance is large, so it does not distort even strong inputs. Motsu. Therefore, AGC
When used in circuits, it always has optimal gain/dynamic range.
第４図に示す増幅器の切換において、定電流源９９相轟
を各段に設けて、これをオ／／オ７テるように変更すれ
ば（図示せず）、任意の複数個の増幅器の並列が可能と
なり、各利得の和の利得を得ることができる。この場合
は少ない増幅器で多くの利得の組合せが出来、効率的で
ある。In the amplifier switching shown in Fig. 4, if a constant current source 99-phase source is provided at each stage and this is changed to an output (not shown), any plurality of amplifiers can be switched. Paralleling is possible, and a gain that is the sum of each gain can be obtained. In this case, many gain combinations can be made with a small number of amplifiers, which is efficient.
入力レベルに応じてどの増幅器を選択するかの手順は予
めメモリに書いておくこともできるし。The procedure for selecting which amplifier according to the input level can be written in memory in advance.
おるいは出力に応じて複数４ｍのコンパレータを用いて
対応する増幅器のオフ／オフを行ってもよい。Alternatively, a plurality of 4m comparators may be used to turn off/off the corresponding amplifier according to the output.
（発明の効果） 以上説明したように、本発明によれば１弱入力。(Effect of the invention) As explained above, according to the present invention, the input is slightly less than 1.
甲入力、強入力のいずれにおいても出力信号の歪、雑音
が小さく、所望の利得と広いダイナミックレンジを有す
る多段増幅器が得られる。It is possible to obtain a multistage amplifier with low distortion and noise in the output signal in both the upper input and the strong input, and which has the desired gain and wide dynamic range.
第１図は従来のディレーＦＡＧＣ型可変利得増幅器の一
例のブロック図、第２図線第１１ｇに示す可変利得増幅
器の一つの詳細回路図、第３図は本発明の一実施例のブ
ロック図、第４図は第３図に示す増幅器群の一つと切換
器の一つの具体的回路例の回路図である。
ｌ・・・・・・入力端子、２，３，４・・・・・・増幅
器％５・・・・・・検波器、６，７・・・・・・出力端
子％８・・・・・・ＡＧＣ回路％ １１・・・・・・入
力端子、１２・・・・・・トランジスタ、１４・・・・
・・定電流源、１５・・・・・・ダイオード、１６・・
・・・・ＡＧＣｔ流源、１７・・・・・・抵抗、１８・
・・・・・ダイオード％ １９・・・・・・定電流源、
２０・・・・・・トランジスタ、２１・・・・・・抵抗
、２２・・・・・・電源、２３・・・・・・出力端子。
３１・・・・・・入力端子、３２〜３６・・・・・・増
幅器％３７・・・・・・選択器％３８〜４２・・・・・
・増幅器、４３・・・・・・選択器、４４〜４８・・・
・・・増幅器、４９〜５３・・・・・・選択器、５４・
・・・・・検波器、５５，５６・・・・・・出力端子。
５７・・・・・・選択決定回路、６１．６２・・・・・
・入力端子、６３〜７９・・・・・・トランジスタ、８
０〜８９・・・・・・抵抗、９０，９１・・・・・・電
源、９２〜９６・・・・・・端子、９７．９８・・・・
・・出力端子、９９・・・・・・定電流源。
竿２１
’？−５＠
第４街FIG. 1 is a block diagram of an example of a conventional delay FAGC type variable gain amplifier, FIG. 2 is a detailed circuit diagram of one of the variable gain amplifiers shown in line 11g, and FIG. 3 is a block diagram of an embodiment of the present invention. FIG. 4 is a circuit diagram of a specific circuit example of one of the amplifier groups and one of the switches shown in FIG. 3. l... Input terminal, 2, 3, 4... Amplifier %5... Detector, 6, 7... Output terminal %8... ...AGC circuit% 11...Input terminal, 12...Transistor, 14...
...Constant current source, 15...Diode, 16...
...AGCt flow source, 17...Resistance, 18.
...Diode% 19... Constant current source,
20...Transistor, 21...Resistor, 22...Power supply, 23...Output terminal. 31... Input terminal, 32-36... Amplifier %37... Selector %38-42...
・Amplifier, 43...Selector, 44-48...
...Amplifier, 49-53...Selector, 54.
...Detector, 55, 56...Output terminal. 57...Selection decision circuit, 61.62...
・Input terminal, 63-79...Transistor, 8
0-89...Resistance, 90,91...Power supply, 92-96...Terminal, 97.98...
...Output terminal, 99... Constant current source. Rod 21'? -5 @ 4th Avenue
Claims (1)
複数群複数液縦続接続前記各増幅器群毎に前記増幅器の
少くとも１個づつを選択する制御手段を接続したことを
特徴とする多段増幅器。Amplifier group 'fr consisting of a plurality of amplifiers with different gains:
A multi-stage amplifier characterized in that a control means for selecting at least one of the amplifiers is connected to each of the amplifier groups.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6800184A JPS60212013A (en) | 1984-04-05 | 1984-04-05 | Multi-stage amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6800184A JPS60212013A (en) | 1984-04-05 | 1984-04-05 | Multi-stage amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60212013A true JPS60212013A (en) | 1985-10-24 |
Family
ID=13361208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6800184A Pending JPS60212013A (en) | 1984-04-05 | 1984-04-05 | Multi-stage amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60212013A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6382109A (en) * | 1986-09-26 | 1988-04-12 | Sony Corp | Semicondcutor integrated circuit |
| US5008631A (en) * | 1989-08-16 | 1991-04-16 | Hewlett-Packard Company | Pulse analyzer with gain compression |
| EP0735668A1 (en) * | 1995-03-30 | 1996-10-02 | AT&T IPM Corp. | High-efficient configurable power amplifier for use in a portable unit |
| EP0762638A2 (en) * | 1995-08-31 | 1997-03-12 | Sony Corporation | Transmitting apparatus and method of adjusting gain of signal to be transmitted, and receiving apparatus and method of adjusting gain of received signal |
| US5796306A (en) * | 1995-08-28 | 1998-08-18 | Nec Corporation | Wide range variable output amplifier apparatus with high efficiency |
| WO1999029037A1 (en) * | 1997-11-28 | 1999-06-10 | Hitachi, Ltd. | High frequency power amplifying circuit, and mobile communication apparatus using it |
| WO1999043083A1 (en) | 1998-02-19 | 1999-08-26 | Ntt Mobile Communications Network Inc. | Amplifier for radio transmission |
| US6320913B1 (en) | 1997-06-23 | 2001-11-20 | Nec Corporation | Circuit and method for controlling transmission amplifiers |
| WO2004064251A1 (en) * | 2003-01-14 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd. | Variable gain amplifier circuit and radio machine |
| JP2007116750A (en) * | 2002-05-31 | 2007-05-10 | Toshiba Corp | Amplifier including variable inductor and radio terminal comprising amplifier |
-
1984
- 1984-04-05 JP JP6800184A patent/JPS60212013A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6382109A (en) * | 1986-09-26 | 1988-04-12 | Sony Corp | Semicondcutor integrated circuit |
| US5008631A (en) * | 1989-08-16 | 1991-04-16 | Hewlett-Packard Company | Pulse analyzer with gain compression |
| EP0735668A1 (en) * | 1995-03-30 | 1996-10-02 | AT&T IPM Corp. | High-efficient configurable power amplifier for use in a portable unit |
| US5796306A (en) * | 1995-08-28 | 1998-08-18 | Nec Corporation | Wide range variable output amplifier apparatus with high efficiency |
| EP0762638A2 (en) * | 1995-08-31 | 1997-03-12 | Sony Corporation | Transmitting apparatus and method of adjusting gain of signal to be transmitted, and receiving apparatus and method of adjusting gain of received signal |
| EP0762638A3 (en) * | 1995-08-31 | 1998-11-18 | Sony Corporation | Transmitting apparatus and method of adjusting gain of signal to be transmitted, and receiving apparatus and method of adjusting gain of received signal |
| US6320913B1 (en) | 1997-06-23 | 2001-11-20 | Nec Corporation | Circuit and method for controlling transmission amplifiers |
| AU751286B2 (en) * | 1997-06-23 | 2002-08-08 | Nec Corporation | Circuit and method for controlling transmission amplifiers |
| WO1999029037A1 (en) * | 1997-11-28 | 1999-06-10 | Hitachi, Ltd. | High frequency power amplifying circuit, and mobile communication apparatus using it |
| EP0977354A4 (en) * | 1998-02-19 | 2001-03-07 | Nippon Telegraph & Telephone | Amplifier for radio transmission |
| US6265935B1 (en) | 1998-02-19 | 2001-07-24 | Ntt Mobile Communications Network Inc. | Amplifier for radio transmission |
| EP0977354A1 (en) * | 1998-02-19 | 2000-02-02 | Ntt Mobile Communications Network Inc. | Amplifier for radio transmission |
| WO1999043083A1 (en) | 1998-02-19 | 1999-08-26 | Ntt Mobile Communications Network Inc. | Amplifier for radio transmission |
| JP2007116750A (en) * | 2002-05-31 | 2007-05-10 | Toshiba Corp | Amplifier including variable inductor and radio terminal comprising amplifier |
| WO2004064251A1 (en) * | 2003-01-14 | 2004-07-29 | Matsushita Electric Industrial Co., Ltd. | Variable gain amplifier circuit and radio machine |
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