JPS60211591A - Time counter for vehicle - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vehicle timing device that measures and displays the parking time of a vehicle.

[Prior art]

Conventionally, this type of timekeeping device includes one that is reset by pressing a reset switch at the start of parking and displays the parking time from the time of reset.

However, the conventional device described above has a problem in that the reset switch is often forgotten to be pressed, making it impossible to accurately measure time.

-1- In view of these problems, the inventors first developed a system that automatically resets when the vehicle starts parking, displays an accurate parking time, and also displays the parking fee. Proposed a timing device for vehicles (patent application filed May 1979-13979).

When using such a timing device, if parking ends immediately when the parking condition is resolved (for example, when the key switch changes from 1-OFF to ``ON''), it will not be possible to warm up or park in the parking lot. The inventors came up with the idea that the parking time is reset due to movement of the vehicle, so it is not always possible to know the exact rest time or parking fee.

[Purpose of the invention]

In view of the above-mentioned problems, the present invention provides a vehicle timing device that can more accurately measure parking time by particularly improving the parking state detection method in the timing device previously proposed by the inventors. With the goal.

(Structure of the Invention) The timing device of the present invention detects the start of parking of a vehicle.
- a parking start detection means for detecting the vehicle speed, a vehicle speed detection means for detecting the vehicle speed, a vehicle arrival end detection means for detecting the end of parking when the vehicle speed exceeds a predetermined speed, and a timing means for measuring the time from the start of parking to the end of parking. Equipped with

〔Example〕

Hereinafter, the configuration and operation of the embodiment will be explained together with reference to each figure.

Fig. 1 shows the overall configuration of the timing device, in which 1 is an ignition switch, 2 is a clock pulse generation circuit, 3 is a driving/parking detection circuit that serves both as a parking start detection means and a parking end detection means, 4 is a timing circuit, and 5 is a clock pulse generation circuit. 1 is a time display circuit, 6 is a mode display lamp, 7 is a battery, 8 is a charge level display circuit, and 9 is a vehicle speed sensor.

The driving/parking detection circuit 3 detects parking based on the "important" signal 1a from the ignition switch, and detects the end of parking, that is, driving based on the vehicle speed signal 9a from the vehicle speed sensor 9.

The clock circuit 4 is reset by the reset pulse 3a of the driving/parking detection circuit 3 at the start of driving and the start of parking, and counts the elapsed time by inputting the clock pulse 2a output from the clock pulse generating circuit 2. This is then output as "time measurement data M11". Also,
A charging level signal 4C that outputs a battery charging required signal 41) when a predetermined parking time has elapsed and also indicates the charging level of the battery.
Output.

FIG. 2 shows an example of the clock pulse generation circuit 2, in which reference numeral 21 denotes an oscillation circuit (in this example, a Suwa Seiko Metal 8
64. OB), 22, 23, and 24 are decimal frequency dividing circuits (T04518 manufactured by Toshiba in this embodiment).

The oscillation circuit 21 receives a 1000/3Hz clock signal 21a.
This clock signal 21a is sent to frequency dividing circuits 22 and 23.
．． 10/3H2 clock pulse 2 divided by 24
3a and 1/3 Hz clock pulse 2a.

FIG. 3 shows a circuit example of the driving/parking detection circuit 3.

31 in the figure is a waveform shaping circuit, resistors 311, 312, 31
3.314, a capacitor 315, a diode 316, an inverter 317, 318 and a transistor 319.

32 is a parking trigger pulse generation circuit, which is composed of a resistor 321, a capacitor 322, and a NOR gate 323.

33 is a delay circuit, which is composed of a binary counting circuit 331 (TC4520 manufactured by Toshiba in this embodiment) and an AND gate 332.

34 is an operation trigger pulse generation circuit, and resistor 341.34
2.343.344, capacitor 345, diode 3
46, a counter 347 (CD40103B manufactured by RCA in this example) that can arbitrarily select the frequency division ratio, an 8-bit switch 348 that sets the frequency division ratio, and an inverter 3
It consists of 49 parts.

35 is a D-type flip 70 tube.

36 is a reset signal generation circuit, which includes a D-type flip 70 tube 361, 362, an EXOR gate t-363, and an AND
It consists of a gate 364.

Further, 37 is a lamp drive circuit, and a buffer gate 37
1, resistors 372 and 373, transistor 374 and Zener diode 375.

-5- The 1 important signal 1a of the ignition switch 1 is shaped by the waveform shaping circuit 31, and when the switch 1 is turned off, the signal 1a is
Signals 31a, 31 at J level and “1” level
It is converted to b. The parking trigger pulse generation circuit 32 emits a trigger pulse 32a that becomes "1" level when the ignition switch is turned off, and the delay circuit 33, which is reset by the pulse 32a, counts the clock pulse 2a and waits for a certain period of time (30 in this embodiment). 11" level signal 33a is emitted after the elapse of 2 seconds). The signal 33a is input to the Cfl& terminal of the flip-flop 35, and at this timing, the signal 31a input to the D terminal is output from the Q terminal as the operation determination signal 35a. When the switch 1 is turned off, the driving discrimination signal 35a becomes the rOJ level, thereby causing the mode display lamp 6 to turn off, indicating that time measurement will start in the parking state. Furthermore, at this time, the reset pulse 3a is output from the reset signal generation circuit 36.

Now, the driving trigger pulse generation circuit 34 includes a vehicle speed sensor 9.
A vehicle speed signal 9a having a pulse number more proportional to the vehicle speed (in this embodiment, 637 pulses per second at a vehicle speed of 60Kn+/hour) is input. The counter 347 performs a counting operation only for 1/15 second while the clock pulse 2a is input, while the switch 348 has a vehicle speed of 30K.
The number of pulses (approximately 21 pulses in this example) obtained in 1/15 seconds in m/hour is set.

Turn on key switch 1 to start driving, and the vehicle speed is 30K.
When the time exceeds IIl/hour, a carry signal of 1-O'' level is generated from the C2 terminal of the counter 347. The carry signal is inverted by an inverter 349 and becomes a trigger pulse 34a. The pulse 34a is the flip 70
This inputs the input to knobs 35 and 361, which causes the output of flip-flop 35 to be at the "1" level, flip 70 and knob 36.
The outputs of 1 are each inverted to the 1'o' level, the indicator lamp 6 lights up, and the reset pulse 3a is output. After this, time measurement is started in the operating state.

FIG. 4 shows a circuit example of the clock circuit 4. 41-7 in the figure
- is a 20-decimal frequency divider circuit consisting of a decimal frequency divider circuit 411, an inverter 412, and a binary frequency divider circuit 413 using a D-type flip-flop.

42 is a hexadecimal counting circuit, 8CD counting circuit (TC4518 made by Toshiba in this example) 421.422, inverter 4
23, OR gate 424 and NAND gate 425.
Consists of 426.427. NAND gate 425.42
6 constitutes a flip 70 tube.

43 is a decimal counting circuit, BCD counting circuit 431.43
Consists of 2.

45 is a parking time setting circuit, AND gate 451.45
2.453.454 and an inverter 455.

Reference numeral 46 denotes a reset pulse generation circuit, which is composed of a D-type flip-flop 461 and an AND gate 462.

47 is the operation time setting circuit, AND gate 471.47
Consists of 2.473.

48 is the first blinking command circuit, which is a D-type flip 70-8
- Tube 481, OR gate 482 and AND gate 48
Consists of 3.

49 is a second blinking command circuit, which is a D-type flip-flop 49.
1 and an OR gate 492. 44 is a charging signal output circuit, which is a D-type flip-flop 4401.4402
．． Decimal counter (in this example, Toshiba TC45208
P> 4405.4406.4 bit subtractor 4407,
AND gate 4403.4408, NAND gate 44
09, OR gate 4414.4419, NOR gate 4
415, inverter 4404.4412.4416 and resistor 4410.4417, capacitor 4413.441
8. Consists of a diode 4411.

At the start of driving and parking, the 2decimal frequency dividing circuit 41 and the counting circuits 42 and 43 are reset by the reset pulse 3a. 1/3 The clock pulse 2a of H2 is input to the frequency divider circuit 41 and becomes the "1" level every minute.
minute pulse signal 418. The sexagesimal counter circuit 42 counts the 1-minute pulse signals 41a-9- and outputs the minute-by-minute timing data M in 2-digit BCD, as well as the 1-hour pulse signal 42a that goes to the "1" level every 60 minutes. do. 1 hour pulse signal 42a is 1
It is counted by the 0-base counting circuit 43 and becomes time measurement data H in 2-digit BCD time units.

The counting circuit 43 also outputs a 100-hour elapsed signal 43a that becomes "1" level from 80 hours after the start of counting to 100 hours after the start of counting, and a 20-hour elapsed signal 43b that becomes "1" level every 20 hours.

When parking, the e1 setting circuit 45 indicates that the driving detection signal 35a is rOJ.
When 15 minutes have elapsed in the level, that is, in the parking state, a 15-minute elapsed signal 45a is output, and when 30 minutes have elapsed, a 30-minute elapsed signal 45b is outputted. It also outputs an inverted signal 45G of the driving detection signal 35a. The operating time setting circuit 47 outputs a 1-hour elapsed signal 47a when the detection signal 35a is at the "1" level, that is, when 1 hour has elapsed in the operating state, and outputs a 2-hour elapsed signal 47b when 2 hours have elapsed. Also,
When 4 minutes have elapsed, a 4 elapsed signal 47c is output.

-10- The reset pulse generation circuit 46 generates the reset pulse 4 at the rising edge of the detection signal 35a, that is, when the operating state is entered.
Outputs 68.

The first blinking command circuit 48 receives the one hour elapsed signal 4.7a.
, 155 minutes elapsed signal 45a1 signal 450 and reset pulse signal 46a are inputted, and first point signal 4.8a is outputted. This flashing signal 48a becomes the "1" level when the vehicle is parked after driving for more than one hour, and becomes the rOJ level after 15 minutes of parking or when the vehicle is restarted.

The second blinking command circuit 49 includes the 2-hour elapsed signal 47b,
300 minutes elapsed signal 45b and reset pulse signal 46a
is input, and the second point signal 49a is output. This blinking signal 49a becomes 11'' level when the vehicle is operated for more than 2 hours, and becomes the rOJ level after 30 minutes of parking or when the vehicle is restarted.

The first blinking signal 48a and the second blinking signal 49a are O.
The signal is input to the R gate 410 and becomes the blinking signal 4a.

The charge required signal output circuit 44 has an inverted signal 45C of the 100-hour elapsed vortex signal 43a1 and the operation detection signal 35a,
A 200-hour elapsed signal 43b and a 4-minute elapsed signal 470 are input. The flip 70 knob 4402 receives the above signal 45.
It is set when the 100-hour elapsed Shintan 4aa is input when G is at the 11'' level, and the charging required signal 4b is output from its Q terminal. On the other hand, the counter 4405 is 200 when parking.
The time elapsed signal 43b is counted, and the counter 4406 counts the 4-minute elapsed signal 4.70 during operation. The count output of the counters 4405 and 4406 is 1, K2 is input to the subtracter 4407, and the subtracter 4407 receives the subtracted value (K
1- and 2) are output as a 4-bit charge level signal 4C. The value of the charge level signal 4G increases when the vehicle is parked, and decreases when the vehicle is driving. When the signal 4C becomes O, that is, when the driving time commensurate with the parking time has elapsed, the OR gate 4
The output of 414 changes from the "1" level to the l' OJ level, and a reset pulse is output from the NOR gate 4415, and the counters 4405, 4406 and flip 7
0 knob 4402 is reset. Due to this -12-, the charging required signal 4b is canceled. That is, the charging required signal 4b is output when the vehicle has been parked for more than 100 hours, and is canceled at a rate of 4 minutes of driving for every 20 hours of parking. For example, if the parking time is 140 hours, the charging required signal 4b will disappear after driving for 28 minutes.

FIG. 5 shows an example of the time display circuit 5.
1, 52, 53, and 54 are liquid crystal decoders (TC4543 manufactured by Toshiba in this embodiment), and 57 are liquid crystal numeric display devices (F2049 manufactured by Toshiba in this embodiment).

Each decoder 51, 52, 53, 54 and the liquid crystal display 57 are driven by the 100/3 Hz clock pulse 21a, and the minute-by-minute clock data M and hour-by-hour clock data H input from the clock circuit 4 are displayed on the display 57. will be displayed.

Here, when the blinking signal 4a of "1" level is input, the AN
10/3 Hz clock pulse 2 through D gate 55
3a is applied to the BI terminal of each decoder 51 to 54, thereby causing the liquid crystal display to blink.

When the charging signal 4b at the "1" level is input, the level of the clock pulse 21a is inverted by the EXOR gate 56 and applied to the MINUS terminal of the display 57, thereby displaying "-".

The level of the clock pulse 21a is also inverted by the inverter 58 and inputted to the C0L f16 of the display 57, so that the colon separating the hours and minutes is displayed by lighting.

When the parking time exceeds 100 hours, "-" is displayed on the display 57 in response to the charging required signal 4b.

As described above, this "-" display disappears after the driving time corresponding to the parking time has elapsed.

When the blinking signal 4a is input, the clock pulse signal 23a
is applied to the BI terminals of decoders 51-54. As a result, if you have been driving for more than a predetermined time, the timer display will flash while driving to notify you of the need to park or take a break. 14- is also indicated by blinking the clock display.

FIG. 6 shows the charge level display circuit 8, where 81 is a 4-bit decoder (in this example, Toshiba TC4028BP), and 82 is a transistor driver array (in this example, Toshiba TD
705P), 83 is a current limiting resistor, 84 is a 10-line bar graph LED C In this example, Sharp GL-112
R13).

The charge level signal 4C is input to a decoder 81, and the decoder output is outputted from output terminals Q, -Q according to the input value.

One of them is level 11. This is driver array 8
2 and causes the bar graph LED 84 to emit light (diagonal lines in the figure). The display on the LFD 84 changes as shown in FIG. 7 to indicate the operating time required for charging. That is, if the car is parked for 20 hours from the state shown in (1) in the figure, the display changes to the state shown in (2) in the figure. Also, if you drive for 4 minutes from state (1) in the diagram,
The display changes as shown in 3).

In this way, since the degree of charge of the battery is displayed using a bar graph, it is possible to easily check the required driving time for charging the battery after long-term parking.

In addition, instead of displaying a bar graph, the degree of charge may be displayed directly with numbers, and in this case, it can also be used as a time display.
To switch to the charge level display for a short time only when the confirmation switch is pressed.

〔Effect of the invention〕

As described above, the timing device of the present invention detects the transition from the parking state to the driving state, that is, the end of the parking state, only when the vehicle exceeds a predetermined speed. There is no problem that the parking time is reset due to movement of the parking time, and accurate parking time can be measured.

By using the present invention, it is possible to reliably know the rest time, charging time, parking fee, etc.

Of course, the above clock circuit may be realized by a computer program.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of the timing device, Fig. 2 is a circuit diagram of the clock pulse generation circuit, Fig. 3 is a circuit diagram of the driving/parking detection circuit, Fig. 4 is a circuit diagram of the timing circuit, and Fig. 5 is a circuit diagram of the clock pulse generation circuit. 6 is a circuit diagram of a time display circuit, FIG. 6 is a circuit diagram of a charge level display circuit, and FIG. 7 is a diagram showing a display example of a charge level display. 1...Key switch 3...Driving/parking detection circuit (parking start detection means and parking end detection means) 4...Clock circuit (timekeeping means) 5......・Time display circuit 9...Vehicle speed sensor (vehicle speed detection means) -17-

Claims (1)

[Claims] Parking start detection means for detecting the start of parking of a vehicle, vehicle speed detection means for detecting vehicle speed, parking end detection means for detecting the end of parking when the vehicle speed exceeds a predetermined speed, and timing from the start of parking to the end of parking. A vehicle timekeeping device comprising a timekeeping means.