JPS5819894B2 - Hensoku Kino Shift Position Hiyoji Souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission shift position display device for detecting the gear engagement position of a transmission in an automobile or the like.

Conventionally, when conducting vehicle tests to measure various characteristics in consideration of the gear meshing position of a vehicle such as an automobile, it was common practice to check the gear meshing position inside the vehicle each time the gear meshing position was changed. .

Therefore, even though various measuring instruments are installed outside the vehicle to conduct tests, there are many cases in which a dedicated tester is required to confirm the gear meshing position.

In order to detect the meshing position of gear outside the vehicle, the present invention uses a signal from an electromagnetic rotation detector using a ring gear on the input side of the transmission and a speedometer drive shaft rotation speed on the output side of the transmission. To provide a shift position display device for a transmission which detects a gear engagement position of a transmission by comparing the gear ratio of the transmission using a signal from a detector and prevents an erroneous display when a clutch is depressed. The purpose is to

The present invention will be described below with reference to embodiments shown in the drawings.

First, in the block diagram of Figure 1 showing the overall overview, 1
01 is a power input terminal, 102 is an initial setting circuit that generates a ``0'' signal to return the entire circuit to its initial state the moment the power source 1 is turned on, and 103 is connected to the speedometer drive shaft on the output side of the transmission. An input terminal for a signal (hereinafter referred to as a vehicle speed signal) with a frequency proportional to continuous speed from the second rotation speed detector 2 that generates 8 pulses per rotation of the drive shaft, and 104 is a vehicle speed signal waveform for shaping this vehicle speed signal waveform. Shaping circuit, 10
5 is a gate circuit that generates a gate signal, a memory signal, a reset signal, and a clutch clock signal from this waveform-shaped vehicle speed signal, and 106 is a first circuit that generates 115 pulses per engine revolution using the ring gear on the input side of the transmission. Input terminal 10 for a signal with a frequency proportional to the engine rotation speed (hereinafter referred to as engine rotation signal) from the rotation speed detector 3;
7 is an engine rotation signal waveform shaping circuit that shapes this engine rotation signal waveform; 108 is a shift position detection circuit that counts the engine rotation speed within a constant vehicle speed signal and detects the gear engagement position of the transmission; 109 is this circuit; A memory circuit for storing signals from the shift position detection circuit, 11
0 is a lamp drive circuit that drives a lamp according to the shift position and a lamp that displays the clutch depression state; 1
11 is a vehicle speed detection circuit that detects a state where there is no vehicle speed; 112;
Reference numeral 113 designates a backup signal input terminal that provides a °0" signal when the gearbox is in the reverse position, and a clutch signal input terminal 113 that provides a °°1" signal when the clutch is depressed.

Then, the memory in the memory circuit 109 is reset by the clutch signal indicating this clutch depression state, the shift position display of the lamp drive circuit 110 is canceled, and the depression state is displayed on a part of the lamp drive circuit 110.

In the above configuration, the initial setting circuit 102, the vehicle speed signal waveform shaping circuit 104, and the engine rotation signal waveform shaping circuit 107 are conventionally known and will not be described in detail. The electrical connection diagram of the gate circuit 105 shown in FIG. 1 is shown, and FIG. 3 shows the waveform diagram of each part thereof.

In FIG. 2, the terminal 201 is the output terminal of the initial setting circuit 102 shown in FIG.
A J signal is generated, returning this gate circuit to its initial state,
From then on, the °1" signal appears until the power is turned off.

Further, a vehicle speed signal having a frequency proportional to the vehicle speed, which has been shaped by the waveform shaping circuit 104 shown in FIG. 1, arrives at the terminal 202.

The vehicle speed signal shown in FIG.
The vehicle speed signal is 1/2/1/4 by flip-flops.
The pulse signals shown in FIG. 3B and C are obtained at the outputs of the first stage and the second stage, respectively.

From the pulse signal and vehicle speed signal, NAND gate 26L2
62°263.271, invert gate 281°28
2.283.284 performs logical operation and each output 2
03.204.206.205 have the third diagram, respectively.
Pulse signals shown at E, F'', and G are obtained.

These pulse signals will be used as reset signals and
Memory signal, gate signal, clutch clock signal.

Next, FIG. 4 shows an electrical wiring diagram of the shift position detection circuit 108 shown in FIG. 1.

In FIG. 4, the terminal 203 is the terminal 203 shown in FIG.
The reset signal shown in the third diagram has arrived.

When the reset signal becomes a °1” signal, the counting circuit 420
The decimal counters 421, 422 and 423 of are returned to their initial states.

In addition, the reset signal in the third diagram is applied to the invert gate 461.
Inverted by NAND gates 432, 433, 434
゜To input 435, 436, 437, terminal 40
2.404.406.408.410.

412 are all "°1" signals, and as will be described later, the terminal 20 returns the memory circuit 109 shown in FIG. 1 to its initial state.
6 is connected to the terminal 206 shown in FIG. 2, and the gate signal shown in FIG. 3 arrives.

An engine rotation signal shaped by the shaping circuit 107 arrives at the terminal 413 .

Then, when the gate signal in Fig. 3F is a °°1゛ signal, N
The AND gate 431 opens, and an engine rotation signal having a frequency proportional to the engine rotation speed appears at the output of the NAND gate 431, and reaches the counting circuit 420.

The counting circuit 420 includes three decimal counters 421 .
It is composed of 422.423 cascade connections, and 10
In the advance counter 421, the engine rotation signal is "10th".
, in the decimal counter 422, the engine rotation signal is 11.
The decimal counter 423 is designed to indicate the "1000th place" of the engine rotation signal.

Therefore, it is possible to count how many pulses of the engine rotation signal have been received while the gate signal in FIG. 3F is a ``1'' signal, that is, while the vehicle speed signal in FIG. The ratio between the vehicle speed signal and the engine rotation signal can be detected.

This ratio is determined by the gear ratio of the transmission and the driven gear ratio (the ratio of the transmission output shaft to the speedometer drive shaft). For example, the gear ratio of the transmission is 3.287 in 1st gear and 2.0 in 2nd gear.
43.3 speed is 1.394.4 speed is 1.000.5 speed is 0
．． 853, 4.039 in reverse, and the driven gear ratio is 2
In the case of 2:6, while the vehicle speed signal is 2 pulses, the engine rotation signal is 346.50 pulses in 1st gear and 215 pulses in 2nd gear.
．． 37 pulses, 146.95 pulses in 3rd gear, 105.42 pulses in 4th gear, 89.92 pulses in 5th gear, and 425.78 pulses in reverse, but in this example, ± Since we are looking at a margin of 6%, when in 1st gear 32
5 to 368 pulses, 202 to 229 pulses in 2nd speed, 3
138-156 pulses in 4th gear, 84-96 pulses in 5th gear, 400-45 pulses in reverse.
It is set to 2 pulses.

Here, the ``4'' output terminal of the decimal counter 421, the ``8'' output terminal of the decimal counter 422, and the 1
The "0" output terminal of the 0-base counter 423 is input to the NAND gate 441, and the engine rotation signal is 8.
When 4 pulses are input, the output of the NAND gate 441 becomes ゛°0.
The signal is inverted by the invert gate 462, and the terminal 401 becomes the signal "1".

Furthermore, the "7" output terminal of the decimal counter 421, the "9" output terminal of the decimal counter 422, and the 10
The "0" output terminal of the advance counter 423 is input to the NAND gate 442, and the engine rotation signal is 97.
When a pulse is input, the output of the NAND gate 442 becomes a 0° signal, which is inverted by the NAND gate 432, and the terminal 402 becomes a 1° signal.

Similarly, the decimal counters 421, 422, 4
23 output terminals are NAND gates 443, 444, 4
45°446.447,448,449,450°45
Connected to L4520 input, engine rotation signal is 9
When 9 pulses enter, the terminal 403 receives the °1"signal; when 113 pulses enter, the terminal 404 receives the "'1"signal; when 138 pulses enter, the terminal 405 receives the °l ll"signal; when 157 pulses enter, the terminal 406 receives the 1"signal; When a pulse enters, the terminal 407 receives a ``1°'' signal, and when a 230 pulse enters, the terminal 408 receives a ``°'' signal.
When the l゛ signal, 325 pulses are input, the terminal 409 becomes the “■” signal. When the 369 pulses are input, the terminal 410 becomes the “°1°” signal, 45
When 3 pulses are input, terminal 412 becomes °1" signal.Terminal 1
12 is connected to the backup signal terminal of the terminal 112 shown in FIG.

At this time, if the engine rotation signal enters 400 pulses, the NAND
The output of the NOR gate 451 becomes the °゛0゛0゛ signal, and the output of the NOR gate 471 becomes the ゛1°゛ signal.
becomes the °°1゛ signal.

Next, FIG. 5 shows an electrical connection diagram of the vehicle speed detection circuit 111 shown in FIG. 1, and FIG. 6 shows a waveform diagram of each part thereof.

In FIG. 5, the terminal 201 is connected to the terminal 201 in FIG.
520 inputs, the outputs of which are II 1 ll signals, respectively, are connected to decimal counters 511, 512, 513, frequency divider circuit 661 and D type flip-flop 521.
522 to its initial state.

The D-type flip-flops 521 and 522 use a well-known MOS ICCD4013 manufactured by RCA, USA.

An engine rotation signal from the waveform shaping circuit 107 shown in FIG. 1 arrives at the terminal 413, and this is shown in FIG. 6H.

When this engine rotation signal enters 497 pulses, the output of the NAND gate 532 becomes a 0° signal, which is inverted by the invert gate 551 to become a 1 signal, obtaining the signal shown in FIG.

Further, when the engine rotation signal enters 499 pulses, the output of the NAND gate 531 becomes a °"0" signal and enters the NAND gate 541, and its output becomes a "°1" signal, and the decimal counters 511, 512, 513, frequency dividing circuit 561,
and return the D type flip-flop to its initial state.

This signal is shown in FIG. 6J.

Terminal 101 is connected to a power source, and terminal 202 is connected to a second
The vehicle speed signal shown in FIG. 6K (same as the vehicle speed signal in FIG. 3A) is connected to the terminal 202 in the figure and arrives.

Now, if there is a vehicle speed, this vehicle speed signal enters the frequency dividing circuit 561, and its second stage output enters the clock terminal CL of the D-type flip-flop 521, and its output terminal Q1
The signal shown in FIG. 6M is generated by the signal shown in L in FIG. 6 (a reduced version of the signal shown in FIG. 6J).

This signal enters one data terminal of the D-type flip-flop 522, and the signal shown in FIG. 6N (reduced signal shown in FIG. 6) enters the clock terminal CL. The output terminal Q becomes a 0'' signal as shown in FIG. 6O, indicating that there is a vehicle speed.

Next, when the vehicle speed disappears, the vehicle speed signal becomes a steady "0" signal as shown in the right half of FIG. 6, so the output terminal Q1 of the D type flip-flop 521 is As shown in the half, it becomes a "0" signal.

Therefore, the output terminal Q of the D-type flip-flop 522 becomes a "1" signal as shown in the right half of FIG. 600, indicating that there is no vehicle speed.

In this way, when the vehicle speed is present at the terminal 501, a 0" signal is generated.
When the vehicle is not fast, a °°1゛ signal is generated.

Next, FIG. 7 shows an electrical connection diagram of the memory circuit 109 and lamp drive circuit 110 shown in FIG.

In this FIG. 8, the terminal 101 is connected to the power supply,
A memory signal arrives at the terminal 204 in FIG.

Terminal 113 is the terminal 113 in FIG. 1, and when a clutch signal is input, it becomes a °1" signal.

A clutch clock signal arrives at the terminal 205 in FIG.

A reset signal arrives at the terminal 203 in FIG.

The terminal 201 is the output terminal of the initial setting circuit 102 shown in FIG. 1, and becomes the II olj signal the moment the power is turned on, and is inverted by the invert gate 761 to put the D-type flip-flop 724 in the initial state.

Also, the terminal 501 is the terminal 501 in Figure 5 when the vehicle is not fast.
1'' signal arrives and U, - goes.

The terminal 113 to which the clutch signal is input is 1. ” signal and enters the D-type flip-flop 717Ω data terminal.

When the clutch clock signal arrives at the clock terminal CL, the output terminal Q becomes the "°l" signal.

This "°1" signal enters the data terminal of the D-type flip-flop 724.

When the memory signal arrives at the clock terminal CL,
The output terminal Q becomes a 1" signal, which lights up the lamp 708 to indicate that a clutch signal has been input.

On the other hand, the "°1" signal arrives at the input of the NOR gate 742, and its output becomes the "0" signal.

Then, it is inverted by the invert gate 762 to form D type flip-flops 718, 719, 720, 72L72.
No matter what state 2゜723 is in, its output terminal Q outputs the °゛0゛°0゛° signal. Therefore, the lamp 701゜10
2.703.704.705.706 are all not lit.

Also, the output terminal Q of the D type flip-flop 724
Since it is a "0" signal, it enters the input of the NAND gate 751.

Then, the output becomes the ``°1'' signal, which is inverted by the invert gate 763 and becomes the ``°O'' signal, and the lamp 70
7 doesn't turn on either.

Therefore, when a clutch signal is input, only the lamp 708 lights up to indicate the clutch depression state.

-Next, when there is no clutch signal, when a ``1'' signal indicating that there is no vehicle speed is input to the terminal 501, the output of the NOR gate 742 becomes the ``0'' signal, and the lamps 701, 702, 703 are activated as described above. .704.705.
706 does not light up at all.

and the D type flip-flop 718°719.
Since the output terminal point of 720.722.723 is the 11111 signal, the output of the NAND gate 731.732 is the "0" signal.

Since this "0" signal enters the NOR gate 741, its output becomes the "°1" signal, and the NAND gate 75
Enter the human power of 1.

Since there is no clutch signal in the input,
A signal has arrived and its output will be the 0'' signal.

Then, the signal is reversed by the invert gate 163 to become a "1" signal, and only the lamp 707 lights up to indicate that the vehicle is not fast.

Next, when the shift position is in the 5th gear, only the terminal 401 becomes the "1" signal as described above, which is input to the clock terminal CL of the D type flip-flop 711.

Therefore, the output terminal Q becomes a °°1'' signal, which is input to the data terminal of the D-type flip-flop 718.

Then, when the memory signal arrives at the clock terminal CL,
The output terminal Q becomes a "1" signal, and the lamp 701 lights up, indicating that the shift position is 5th gear.

Further, when the shift position is in the 4th gear, the '1' signal arrives at the terminals 401, 402, 403 as described above, and the '1' signal from the terminal 401 causes the output terminal of the D type clip-flop 711 to Q becomes a "°1°" signal, but before the memory signal arrives at the clock terminal CL of the D type flip-flop 718, the terminal 4
The “1” signal of 02 is the D type flip-flop 71.
Since it enters the reset signal R of 1, it is reset and the output terminal Q becomes a "0" signal.

Therefore, the output terminal Q of the D type control flop 718 also becomes a ``0'' signal, and the lamp 701 does not light up.

On the other hand, since the °°1' signal of the terminal 403 enters the clock terminal CL of the D type flip-flop 712, its output terminal Q becomes the °'1' signal, and the D type flip-flop 712 receives the °°1' signal.
Enter the data terminal of knob 719.

Then, when the memory signal arrives at the clock terminal CL,
Its output terminal Q serves as a ``1'' signal, and the lamp 7
02 lights up, indicating that the shift position is 4th gear.

Similarly, when the shift position is 3rd gear, the lamp 703 lights up, when the shift position is 2nd gear, the lamp 704 lights up, and when the shift position is 1st gear, the lamp 705 lights up. When the shift position is in the reverse position, the lamp 706 lights up.

In this way, different lamps light up depending on the engagement position of the transmission, making it easy to confirm the engagement position of the transmission, and by installing the above device outside the vehicle cabin, the effort required for complicated confirmation can be saved. It will be destroyed.

In the embodiments described above, the shift position is determined by how many pulses of the engine rotation signal are counted between two pulses of the vehicle speed signal, but the method of the embodiment described below may also be used.

This will be explained using the block diagram shown in FIG. 8 and the waveform diagram of each part shown in FIG.

The vehicle speed signal shown in FIG. 9P is inputted to the terminal 820, and the pulse signals shown in FIG. 9R and S are obtained by the rising edge detection circuit 804 and the falling edge detection circuit 805.

An engine rotation signal shown in FIG. 9T arrives at the terminal 821, and a pulse signal shown in FIG. 9V is obtained by the fall detection circuit 806.

Then, if the high frequency pulse from the oscillation circuit 801 that generates the high frequency pulse is input to the gate circuits 802 and 803,
When the vehicle speed signal and engine rotation signal are ゛°1゛ signal,
To open the gates of each department, its output is Q and V in Figure 9.
The pulse signal shown in FIG.
and is counted.

The outputs of the counting circuits 807 and 808 are shown in FIG.
The memory circuits 809 and 810 are
entered and memorized.

Then, each output enters the shift position detection circuit 811 by the pulse signal shown in FIG. The shift position is detected and displayed using lamps or the like connected to each of the output terminals 822.

In any of the above embodiments, it goes without saying that the number of pulse signals obtained from each detector and each circuit can be set arbitrarily. Various types can be used.

Further, the device of the present invention is not limited to a digital calculation type, but the digital amount from each of the detectors is converted into an analog amount, or each detector is of an analog amount generation type, and the calculation of each circuit is performed in an analog manner. The shift position may also be displayed as an analog quantity by using a formula.

As described above, in the present invention, the shift position position is detected and displayed by comparing the engine rotation signal on the input side of the transmission and the vehicle speed signal on the output side. It has the excellent effect of being able to electrically detect the gear engagement position of the transmission without attaching anything, and preventing false indications when the clutch is depressed based on the clutch depression signal, making it easy to shift outside the vehicle. This also has the effect of allowing you to check your position.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the overall configuration of an embodiment of the device of the present invention, Fig. 2 is an electrical wiring diagram of the gate circuit shown in Fig. 1, and Fig. 3 is an operation of the gate circuit shown in Fig. 2. Figure 4 is an electrical wiring diagram of the shift position detection circuit shown in Figure 1. Figure 5 is an electrical wiring diagram of the vehicle speed detection circuit shown in Figure 1. Figure 6 is an electrical wiring diagram of the vehicle speed detection circuit shown in Figure 1. FIG. 5 is a signal waveform diagram of each part to explain the operation of the vehicle speed detection circuit shown in FIG. 7, an electrical connection diagram of the memory circuit and lamp drive circuit shown in FIG. 1, and FIG. 8 is another implementation of the device of the present invention. FIG. 9 is a block diagram showing a partial configuration of an example. FIG. 9 is a signal waveform diagram of each part for explaining the operation of the embodiment shown in FIG. 2... Second rotation speed detector, 3... First rotation speed detector, 108,811... Shift position detection circuit, 110...・Lamp drive circuit as display means.

Claims (1)

[Claims] 1. A first signal that generates a signal according to the rotation speed on the input side of the transmission.
a rotational speed detector, and a second circuit that generates a signal corresponding to the rotational speed on the output side of the transmission.
generates a signal according to the gear ratio according to the signal from the rotation speed detector and the rain detector, and compares the signal with a plurality of preset signals according to the shift position of the transmission. Shift position detection means for detecting one shift position; display means for displaying the shift position detected by the detection means; means for canceling the display of the display means in response to a signal indicating a clutch depression state; A shift position display device for a transmission, comprising: means for displaying a clutch depression state in conjunction with display release; and a shift position display device for a transmission.