JPS60208801A - Chip resistor - Google Patents
Chip resistorInfo
- Publication number
- JPS60208801A JPS60208801A JP59066570A JP6657084A JPS60208801A JP S60208801 A JPS60208801 A JP S60208801A JP 59066570 A JP59066570 A JP 59066570A JP 6657084 A JP6657084 A JP 6657084A JP S60208801 A JPS60208801 A JP S60208801A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- electrode
- chip resistor
- chip
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Non-Adjustable Resistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
所業上の利用分野
木光明はチップ抵抗器に関覆るしの(ある1゜従来例の
構成とぞの問題点
3Ii(+、]]ヒビ−1−ターV −1’ I<笠、
人i’i’tの抵抗器を使用する機器の゛出現に、よっ
て抵抗器の形態ら進展し、Jlt抗ネッ1−ワークやチ
ップ抵抗器?9、小形、軽量、高集(^化へと変貌して
さている。、又、チップ抵抗器は高周波特f1に優れ、
プリント基板に接着後、半l−I]fζjりがil (
jヒe、ノノッしンブル]ス]・の大幅な低減ができる
。DETAILED DESCRIPTION OF THE INVENTION In the field of application, Ki Mitsuaki discusses chip resistors. 1'I<kasa,
With the advent of devices that use resistors, people have evolved from resistor configurations to JLT networks and chip resistors. 9. Chip resistors are becoming more compact, lightweight, and highly integrated.In addition, chip resistors have excellent high frequency characteristics f1,
After adhering to the printed circuit board, half l-I]fζjrigail (
It is possible to significantly reduce the amount of damage caused by this process.
従来のチップ抵抗器についC1第1図〜第4図を用い゛
て説明する。1第1図は従来のチップ抵抗器の外観斜視
図、第2図は第1図に81プる■−■線に沿うmi面図
、第31z1は同デツプ抵抗器の回路図【iδりる。A conventional chip resistor will be explained using C1 FIGS. 1 to 4. 1 Figure 1 is a perspective view of the external appearance of a conventional chip resistor, Figure 2 is a mi plane view taken along the line 81 in Figure 1, and Figure 31z1 is a circuit diagram of the same deep resistor [iδ .
第2図に示づように、アルミプ基板などのセラミック基
鈑1の上に電極2a、21+を印刷、焼成などにより形
成し、次に抵抗体4を同様に印刷、焼成などにより形成
り〜る。その後、半11食われの防11や、半III(
ζj性を良く覆るため、外部型445 a 。As shown in FIG. 2, electrodes 2a, 21+ are formed on a ceramic substrate 1 such as an aluminum plate by printing, firing, etc., and then a resistor 4 is formed in the same manner by printing, firing, etc. . After that, half 11 defense 11, half III (
External type 445 a to cover the ζj property well.
5 bを半[1j (=J法などにJ:り取(=jけ、
保:a膜6でパッケージして、第1図に示づような完成
品どなる。5 Take b by half [1j (=J method etc.)
After packaging with the A film 6, a finished product as shown in FIG. 1 is obtained.
しかしながらこの上うむ従来のチップ抵抗器では、第4
図のようなブリーダバイアス回路を構成づる場合、7a
、71+間と7b、7a間どの抵抗比が重要となり、両
省のV[容差が相乗され、バイアス電f[のばらつきの
要因となるー。このように、個々の値よりも両者の抵抗
比のti’i疫が必要な場合というのは、回路中に多・
(存在Jる。これを2個対にして使用りることは非常に
rs L、 < 、個々の粘1良を」二げるJ:う方法
はなかつ!、:。However, in conventional chip resistors, the fourth
When configuring a bleeder bias circuit as shown in the figure, 7a
, 71+ and between 7b and 7a, which resistance ratio is important, and the difference in V[capacitance between the two components is multiplied and becomes a cause of variation in the bias current f[]. In this way, when it is necessary to adjust the resistance ratio between the two rather than the individual values, it is necessary to
(Existence J. It is very difficult to use two of these in pairs.
発明の目的
本発明は上記従来の欠点を解消づるもので、従来2個使
用し℃い)ζ部品を1個で代用ぐさ、小型・化と精度の
向上とを実現でさるチップ抵抗器を提供することを目的
とする。Purpose of the Invention The present invention solves the above-mentioned drawbacks of the conventional technology, and provides a chip resistor that can replace the conventional two components (ζ) with one component, thereby realizing miniaturization and improved precision. The purpose is to
発明の構成・ ゛
上記目的を達成りるため、本発明のブツノ′抵抗器は、
第1の電極と第2の電極との間に配置?T 1ノ/に抵
抗体の任意の位置に第3の電極を段()だしのである。Structure of the Invention ・In order to achieve the above object, the resistor of the present invention has the following features:
Placed between the first electrode and the second electrode? At T1/, a third electrode is placed at an arbitrary position on the resistor.
実施例の説明
以下、本発明の一実施例について、図面に基づいて説明
する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.
第5図は本発明の一実施例にa3Gノるチップ抵抗器の
外観斜視図、第6図は第5図にJハJるVl−Vl線に
沿う断面図、第7図は同チップ抵抗器の回路図である。Fig. 5 is an external perspective view of a chip resistor according to an embodiment of the present invention, Fig. 6 is a cross-sectional view taken along the line Vl-Vl in Fig. 5, and Fig. 7 is the same chip resistor. FIG.
第6図のように、セラミック基板8の士に、両端の第1
及び第2の電極9a、9bと、それらの間の適当な位置
に位置−4る第3の電極9Cとを、印刷、焼成などによ
り形成づる。次に抵抗体10を第1〜第3の電極98〜
9CにまたがるJ:うに印刷、焼成などにより形成する
。その後、第1〜第3の外部電極118〜11cを半田
付1ノ法などにより取付け、保護膜12て・バックージ
して、第5図に承りような完成品と4「る。As shown in FIG. 6, between the ceramic substrate 8, the first
Then, the second electrodes 9a, 9b and the third electrode 9C located at an appropriate position between them are formed by printing, firing, etc. Next, the resistor 10 is connected to the first to third electrodes 98 to
J spanning 9C: Formed by sea urchin printing, firing, etc. Thereafter, the first to third external electrodes 118 to 11c are attached using a soldering method or the like, and the protective film 12 is back-packed to form a finished product as shown in FIG.
以上のように構成された本実施例のチップ抵抗器につい
て、以下イの使用例を説明り゛る。′まず、例えば第7
図のような電気回路を1個のチップ抵抗器′c梠成でき
る。りなわら、一方の端子が共通な2個の抵抗を1個の
チップ抵抗器で実現出来、小型化出来る。なお1.10
aは抵抗体10の電極9a。An example of use of the chip resistor of this embodiment configured as described above will be described below. 'First, for example, the seventh
An electric circuit as shown in the figure can be constructed using one chip resistor. However, two resistors with one terminal in common can be realized with one chip resistor, and the size can be reduced. Note 1.10
a is the electrode 9a of the resistor 10;
90間部分、iobは抵抗体10の電極9b 、9c間
部分である。さらに、第4図のようなブリーダバイアス
回路のように両者の抵抗比が問題となる場合、まず一方
の抵抗10aあるいは10bをレーザートリミングし、
その誤差を補正りるにうに他方の抵抗101zSうるい
は10aをレーザートリミングづれば、高tl11度の
抵抗比を持つチップ抵抗器が得られる。The portion between electrodes 90 and iob is the portion between electrodes 9b and 9c of the resistor 10. Furthermore, if the resistance ratio between the two is a problem, such as in the bleeder bias circuit shown in FIG. 4, first laser trimming one of the resistors 10a or 10b,
By laser trimming the other resistor 101zS or 10a to correct this error, a chip resistor having a high resistance ratio of 11 degrees can be obtained.
第8図は別の実′施例にJ’3 Uるチップ抵抗器の回
路図ぐ、上記実施例では第3の電極9Cを抵抗体10の
中間部に設【ノだが、この実施例r 1.i、抵抗体1
317)−一端に第3の電極9Gを設(′J:第2の電
極9bど第3のfrf棒9Gとをブーツノ抵抗器内BI
I ”c”導電体により接続したしのでdうる。FIG. 8 is a circuit diagram of a chip resistor according to another embodiment. 1. i, resistor 1
317) - A third electrode 9G is installed at one end ('J: The second electrode 9b and the third frf rod 9G are connected to the BI in the boot resistor.
I ``c'' Since it is connected by a conductor, it can be d.
発明の詳細
な説明したJ、うに本発明に、J、れば、3 Chi
j’をイ1するチップ抵抗器としたので、従来2個の部
品を1個て゛ゼ4成りることが出λ(、桟器の小!1°
J化を実現出来る。まlζ、レーザートリミング等によ
り、高fi’+爪の抵抗比を持つチップ抵抗を拐ること
ができる。さらに、31′i向に外部端子を出すことに
より、半ITI付・st−性がよくなる。まIJ本発明
によるチップ抵抗器の両端をM源及びアースに接続し、
中間に得られる電圧をバイアス電圧としで、電子回路へ
供給する場合、製造工程において両抵抗の相対値が一定
となるにうじレーザーミーリミングしたしのを使用寸れ
ば、精!良のJ:いバイアス電圧がgJられる。例えば
、−1ノの抵抗値をレーザー!・リミングした後、その
]−リリミタされた値の誤差を相殺するように他方の目
標値を設定づれば、得られるバイアス電圧の誤メイ−【
よ従来の約半分となり、回路の精度向1−が図れる。さ
らに、例えば、バイアス電圧によって利1艷1を調撃で
き′41回路にJ3いて、−ノ
1−記バイアスを発生させる回路素子(づなわら本発明
のチップ抵抗器)をあらかじめ接続しない状態C1別電
源により上記バイアスを供給し、これをijJ変しC所
定の利1!7が得られた11hの雷L1賄と同等のバイ
アス電圧が得られるにうに、別丁稈にて上記チップ抵抗
器をレーザーミーリミングして、最後に回路と接続Jる
方法が可能であり、これによれば、従来のアルミ〕基板
上の厚膜印刷抵抗をトリミングする方式に比べて、安価
にチ′−ツブ部品を使用して機能トリミングが実説ひき
る。Detailed description of the invention J, Uni to the present invention, J, If, 3 Chi
Since j' is a chip resistor with an angle of 1, it is possible to use one component instead of the conventional two.
J conversion can be realized. A chip resistor with a high fi'+claw resistance ratio can be removed by laser trimming or the like. Furthermore, by extending the external terminal in the direction 31'i, semi-ITI attachment and st-ability are improved. Connect both ends of the chip resistor according to the present invention to the M source and ground,
When using the voltage obtained in the middle as a bias voltage and supplying it to an electronic circuit, it is best to use a laser-rimmed material that ensures that the relative values of both resistances are constant during the manufacturing process. Good J: Good bias voltage is gJ. For example, a laser with a resistance value of -1! - After rimming, if you set the other target value so as to cancel out the error of the limited value, the resulting bias voltage will be incorrect.
It is about half that of the conventional method, and the accuracy of the circuit can be improved by 1-1. Furthermore, for example, the bias voltage can be used to check the bias voltage. The above bias was supplied by the power supply, and the above chip resistor was installed in a separate culm in order to obtain a bias voltage equivalent to the 11h lightning L1 voltage that was obtained by changing ijJ and obtaining a predetermined gain of 1!7. It is possible to perform laser trimming and finally connect to the circuit.This method allows chip parts to be manufactured at a lower cost than the conventional method of trimming thick-film printed resistors on aluminum substrates. Using the trimming function is demonstrated.
?1】1図は従来の1−ツノ(1(杭孔の外観斜視図、
第2図は第1図にJハノる■−1[線にγ0うjai面
図、第3図(J、同チップ抵抗器の回路し1、第4図G
J、 /リーグパイノ7ス回路の回路図、第5図(、L
本発明の一実施例におりる1ツゾ抵抗器の外観斜視図、
第6図は第5図におりるV[−、Vl線に沿うIrJi
面図、第7図は同チップ抵抗器の回路図、b′18図は
別の実施例にJ5りるデツプ抵抗器の回路図である。
ゝ9a・・・第1の電極、9 b・・・第2の電極、O
C・・・i′(3の電極、10.43・・・抵抗体、l
la・・・第1の外部型4?i+、1111・・・第2
の外部電極、11c・・・第33の外部゛電極
代理人 a 木 貨 弘
第1図
第2図
第3図? 1] Figure 1 is a conventional 1-horn (1 (external perspective view of a pile hole,
Figure 2 shows the circuit diagram of the same chip resistor in Figure 1, Figure 3 (J), Figure 4 shows the circuit diagram of the same chip resistor (1), Figure 4 (G
J, Schematic diagram of /League Pinos 7 circuit, Figure 5 (,L
An external perspective view of a tsuzoresistor according to an embodiment of the present invention,
Figure 6 shows IrJi along the V[-, Vl line in Figure 5.
A top view, FIG. 7 is a circuit diagram of the same chip resistor, and FIG. b'18 is a circuit diagram of a deep resistor J5 in another embodiment. 9a...first electrode, 9b...second electrode, O
C...i'(3 electrode, 10.43...resistor, l
la...first external type 4? i+, 1111...second
External electrode, 11c...33rd external electrode agent a Hiroshi Kimi Figure 1 Figure 2 Figure 3
Claims (1)
の任意の位Kに第3の71:i 441を一、ニジ()
たチップ抵抗器。 2、第1の電極に当接゛する第1の外部電極と第2の電
極に当接する第2の外部電極との間に、第3の電極に当
接づる第3の外部型14+を配「りした特許請求の範囲
第1項記載のチップ抵抗器。[Claims] 1. Add the third 71:i 441 to any position K of the resistor placed between the first electrode and the second electrode.
chip resistor. 2. A third external mold 14+ that contacts the third electrode is disposed between the first external electrode that contacts the first electrode and the second external electrode that contacts the second electrode. ``The chip resistor according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59066570A JPS60208801A (en) | 1984-04-02 | 1984-04-02 | Chip resistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59066570A JPS60208801A (en) | 1984-04-02 | 1984-04-02 | Chip resistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60208801A true JPS60208801A (en) | 1985-10-21 |
Family
ID=13319742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59066570A Pending JPS60208801A (en) | 1984-04-02 | 1984-04-02 | Chip resistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60208801A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63121403U (en) * | 1987-01-30 | 1988-08-05 | ||
JPS6437002U (en) * | 1987-08-28 | 1989-03-06 | ||
JP2018006726A (en) * | 2016-06-27 | 2018-01-11 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Resistive element and mounting substrate of the same |
-
1984
- 1984-04-02 JP JP59066570A patent/JPS60208801A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63121403U (en) * | 1987-01-30 | 1988-08-05 | ||
JPS6437002U (en) * | 1987-08-28 | 1989-03-06 | ||
JP2018006726A (en) * | 2016-06-27 | 2018-01-11 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | Resistive element and mounting substrate of the same |
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