JPS6020768B2 - Microprogram control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system, and more particularly to a microprogram control system that can control the execution of multiple machine cycles with one microinstruction.

The microprogram control method breaks down the operation of the processing unit into basic operations, determines microinstructions corresponding to each operation, stores these microinstructions in a control memory, and stores these microinstructions one after another in the control memory during execution. This method reads and executes the data from the device.

This method is easy to design and has good maintainability. It has the advantage of being highly flexible. On the other hand, since a new microinstruction is read and executed every machine cycle, if there are few operations performed in one machine cycle, there is little effective information in the microinstruction, and the use of a relatively expensive control memory device becomes less efficient. There are drawbacks that reduce the

The first object of the present invention is to make it possible to control multiple machine cycles with one microinstruction in a microprogram control method that normally reads a microinstruction every machine cycle.
Another object of the present invention is to eliminate the above disadvantages by retaining microinstructions for multiple machine cycles.A further object is to include a control part in the microinstruction that directs the time sequence of multiple machine cycles, and a control part that instructs the time sequence of multiple machine cycles in the microinstruction. By decoding and executing the control part of the microinstruction that instructs gate control at an arbitrary time by combining the generated circuits, the control part that instructs the time series for various processes that require multiple machine cycles can be used. By simply rewriting the corresponding microprogram, there is no need for a dedicated control circuit for various processes as in the past.

In addition to the above-mentioned features, the present invention also provides a logic system that occurs when switching cycles in order to continuously perform gate control when the same gate is opened over a plurality of machine cycles. Some measures were required to suppress the fluctuations, but with the present invention, such measures are no longer necessary as the microinstructions are retained.Additionally, the control portion of the microinstructions that instruct gate control can be set at any time. Since it can be used, it has the advantage that it is possible to control multiple machine cycles in the same way as if a microinstruction were executed every machine cycle. A detailed explanation will be given below according to the drawings.

FIG. 1 shows the overall configuration of a data channel device according to an embodiment of the present invention.

However, only the details necessary to explain the features of the present invention are described. In Figure 1, CM is a control storage device storing microprograms for executing various processes, CMIR is its instruction register, and DECI to DEC4 are for decoding microinstructions read into CMIR. This is a decoder.

A microinstruction consists of several control parts called fields, including JA, FA, FB, and
FC, FD, FT, and AC correspond to respective fields. In addition, DECI to DEC4 are FA to FD, respectively.
It is a decoder for fields. CMAR is C
a control storage device address register storing the address of M;
SEL is a circuit that selects information to be set in CMAR,
1ADD is CMAR's 11 adder, ADC is SEL,
This is an address control circuit that controls CMAR. The OTL is a circuit that controls a plurality of control fields for performing gate control, which is a feature of the present invention, over a plurality of machine cycles, and its details are shown in FIG.

The above is the configuration of the control section of this embodiment. Next, the configuration of the data section operated by the control section will be described.

Connections between this device and other devices are performed as follows. Main memory M. For M, a memory address data line MAB, a memory store data line MDB, and a memory answer data line M
This is done via the WB, and for the input/output control device IOC via the input/output interface bus lOBUS. MAR is a memory address register that stores memory addresses; MBR is a memory buffer register that stores memory store data or receives memory answer data; DA is a data address register that holds memory address information where data to be transferred is stored; WC is a word count register that stores data transfer amount information, F
LAG is a group of FFs that stores information indicating transfer control methods (commands, chaining flags, chain data flags, program controlled interruptions, etc.)
DB is a data buffer that stores transfer data, ADDE
R is an adder that mainly performs 11 and 11 additions, TEST is an extraction circuit for signals to be tested and various test circuits, and DET is an ADDE.
This is a detection circuit that detects all "0" of the R output and detects whether the TEST output is on or off and holds it. PBUS,RB
US is a signal bus for transmitting various information.

Figure 2 shows details of the CTL in Figure 1.
Detection circuit IDBT that detects activation of TL, flip-flops FI to F5 that generate timing, field FT
A decoder DECT decodes the data, and gates GCI to G create signals indicating whether the gate control field is valid or invalid.
Gates GC5 to G that detect the termination conditions of C4 and CTL
Consists of C7.

FIG. 3 is a time chart showing an example of the operation of the circuits shown in FIGS. 1 and 2, and will be explained below using a memory access operation as an example according to FIG. Now, assume that the contents of address 10 of the CM are read to the CMIR in the first machine cycle (hereinafter referred to as cycle), and that this instructs memory read control over a plurality of cycles.

The microinstruction at address 10 has fields JA, FA, and F.
Consists of B, FC, FD, FT, AC, FA to FD
is the field that controls the gate of the data section, JA is the CM
AC is a field that controls whether to use the next instruction address and the contents of JA or CMAR+1 address, and the FT field is a field that specifies the jump address of
One of the features of the present invention is that the FA to FD fields are instructed to be controlled over a plurality of cycles by the logic of a time series instruction of a plurality of cycles and the output of a timing tree that generates various timings.

Prior to execution of the first cycle, the IDET circuit detects the contents of the FT field from the CM output and determines whether the microinstruction read in the first cycle is to control over multiple cycles. Time is C
CT at the same time as setting CM output to MR
FI of L is set.

Note that the contents of CMAR used here are updated with the 0-phase clock in one cycle, and the contents of one temporary flea designation are set in a cycle before the one shown in the figure. CT
Activation of L starts with FI setting, and thereafter flip-flops F2 to F5 operate to generate various timings.

After setting F1, the CTL circuit connects to the ADC via the signal line SI, stops updating CMAR using the 0-phase clock, and sets F2 using the m-phase clock.

F2 is an FF that lights up while the CTL circuit is in operation, resets the FI in one phase of the second cycle via the signal line S2, propagates the timing tree with a pulse corresponding to the cycle, and updates the CMIR via the signal line S2. and allows retention for a specified number of cycles. F3,F
4, F5 propagates the FI output, respectively in the second cycle,
Timings corresponding to the third and fourth cycles are generated.

Here, the contents of the FT feed specify a time series related to the memory read operation, are decoded by DECT, and are output to the signal line DI.

In the first cycle, the logic of DI and FI is detected by the gate GCI, and the signal line S3 is driven.The logic of the signal line S2 and DI is also detected by the gate GCO, and a read command is sent to the MM via the signal line S8. .

S3 is a pulse corresponding to the first cycle and makes DECI valid only in the first cycle.

The output D2 of DECI opens gates G2 and GI, puts the contents of register DA on PBUS, and inputs it to ADDER.

On the other hand, this content is set to MAR by the m-phase clock. Further, D2 performs the function of ADDER by adding 11, and the content of DA is 11 and outputted to RBUS, gate G3 is opened, and DA is updated by setting it in DA with the 1-phase clock of the second cycle.

In the second cycle, the output of timing tree F3 and DI
The gate GC2 takes this logic and drives the signal line S4.

S4 is a pulse corresponding to the second cycle, and DEC2
is valid only in the second cycle. The output D3 of DEC2 is to open the gate G4 and transfer the contents of the register WC to PBUS and add -1 to the ADOER function, and open the gate G5 to add -1 the contents of WC to WC in the third cycle.
The WC is updated by setting it in phase.

At the same time, the ADDER output is detected by DET, and if it is all "0", the signal is sent to FL by opening gate G9.
Set a specific bit of AG.

In the third cycle, the output of the timing tree F4 and the logic of DI are taken by the gate GC3 and the signal line S5 is driven.

S5 is a pulse corresponding to the third cycle, and DEC3
is valid only in the third cycle. The output D4 of DEC3 is an FL that opens gate G6 and puts the contents of FLAG onto PBUS, and displays the -1 addition result of WC in the second cycle.
A detection instruction for detecting a specific bit of AG and a specific bit (for example, a data chain instruction) instructing transfer control in FLAG is given to TEST, and the detection result is displayed on DET. As will be explained later, if the WC value is zero and there is a data chain instruction, the microinstruction at the address specified in the JA field will be read from the CM and executed when the predetermined control held in the CMIR is completed. be done. In the fourth cycle, the output of the timing tree F5 and the logic of DI are taken by the gate GC4 to drive the signal line S6.

Further, the gates GC6 and GC7 detect that the fourth cycle is the final cycle of the multi-cycle control, and drive the signal line S7. S7 resets F2 in the m-phase of the fourth cycle, and restarts the update of CMIR with the 1-phase clock in the fifth cycle. In addition, during this operation, S7 restarts the ADC, selects the next microinstruction with SEL according to the instructions of the AC field and the logic of the output of DET, and instructs the setting of CMAR with the 0 phase clock. CM access of the microinstruction to be executed is performed.
The signal line S6 is a pulse corresponding to the fourth cycle DE
C4 is valid only in the fourth cycle. DEC4 output D
5 opens the gate G7 and puts the contents of the MBR which receives the memory retrieval information arriving via the MWB from around the 1st phase clock of the 4th cycle onto the RBUS, and the received information is transferred to the 5th cycle by opening the gate G8. Register D in one phase of the cycle
Set it to B to finish reading the transferred data from memory.
The 6th cycle uses the 1-phase clock to convert the CM access output at address 11, which started from the 0-phase clock of the 4th cycle, to CM.
Set to IR and continue executing the next control. The above is
This is an explanation of the operation of one embodiment of the present invention, and another embodiment to which the present invention is effectively applied is shown in FIG. 4, and its time chart is shown in FIG.

Figure 4 shows the configuration of Figure 1 with CMIRB and DECB added, and CMIR in Figure 1 is CMIRA, DECI
~DEC4 corresponds to DECA and ADC corresponds to MPC.

The feature of FIG. 4 is that it has two CMIR and DEC groups, which are used depending on whether microinstruction control is one-cycle control or multiple-cycle control. That is, C
As mentioned above, MIRA and DECA control microinstructions that perform control over multiple cycles, and are
MIRB and DECB control microinstructions read every cycle.

The purpose of this configuration example is to create two Cs with different usages as described above.
By preparing MIR and DEC groups, processing speed is increased.

To explain the operation using the time chart in Figure 5 as an example, the first
In a cycle, the contents of address 100 are read out to CMIRB and one cycle control is executed.

In the second cycle, the contents of address 101 are read out to CM Melon A, and thereafter three cycles of control including the third and fourth cycles are started. Here, switching between setting the CM output to CMRA or CMIRB is done using CMI.
The MPC decodes whether the microinstruction to be executed next is one-cycle control or multiple-cycle control based on instructions in specific fields of RA and CMIRB, and controls the setting of the instruction register. The MPC also controls SEL and CMAR to monitor address updates of microinstructions. CMIR
The content of address 101 set in A is to instruct multi-cycle control such as memory access, but in that specific field, the address of the microinstruction to be executed next after address 101 is specified and the next If the microinstruction to be executed is specified as one-cycle control or multiple-cycle control, and if it is one-cycle control, check whether the control range targeted by the microinstruction at address 101 and the control range of the next microinstruction to be executed are independent. If the next microinstruction is 1 microcontrol and the control range is independent after decoding with MPC, set the next microinstruction (in this case, address 102) to CMIRB in the third cycle and make it independent in parallel with CMIRA. Control takes place. Thereafter, parallel control becomes possible in the fourth cycle as well.

As described above, as in the above two embodiments, the present invention includes a field that indicates a time series and a circuit that generates timing.
By retaining the microinstruction register for multiple cycles, the microinstruction register is easily used to efficiently use microinstructions and to easily provide control over multiple cycles that is not limited to one-cycle control, and as shown in the latter embodiment. Microphones with some degree of parallel processing.

It enables program control and speeds up processing.
This is an effective method for improving the usage efficiency of the data section.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a part of FIG. 1 in detail, and FIG. 3 is a time chart explaining the operation of FIGS. 1 and 2. , FIG. 4 is a diagram showing another embodiment of the present invention, and FIG. 5 is a time chart explaining the operation of FIG. 4. In the figure, CMIR is Instruction Registry, DEC
I~DEC4, DECT is a decoder, CM is a control memory, CMAR is a control memory address register, S
EL is a selection circuit, ADC and MPC are address control circuits,
CTL is a control circuit, MM is a main memory unit, MBR is a memory buffer register, MAR is a memory address register,
DA is a data address register, WC is a word count register, FLAG is an FF group, DB is a data buffer, T
EST is a test circuit, and DFT and MET are detection circuits. Traditional drawings, 5 drawings, 2 drawings, 3 drawings, 4 boxes

Claims (1)

[Claims] 1. A microprogram control system that enables control over multiple machine cycles using microinstructions, which includes a timing generation circuit that generates timing over multiple machine cycles, and is composed of multiple control fields, each of which a first control part that instructs control of multiple gates in one microinstruction;
A second control portion is provided that instructs control over a plurality of machine cycles and specifies a time series of the plurality of control fields over the plurality of machine cycles, and the second control portion instructs control over a plurality of machine cycles. When the same microinstruction is retained for multiple machine cycles,
A microprogram control system characterized in that the timing output of the timing generation circuit is controlled according to a specified time series, and the plurality of control fields are sequentially decoded and executed.