JPS60207352A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize a superior resistive contact by alloying a metal layer combined with the wiring material of the first and the second electrodes by heat treatment. CONSTITUTION:A polycrystalline silicon film 14 is diffused with phosphorus and heat-treated. A titanium pattern 9 and a molybdenum silicide pattern 8 are reacted by the heat treatment and an alloy pattern 15 is formed and simultaneously, an alloy layer 16 is formed near a contact hole 13 and a gate electrode 17 is formed. Then, a phosphorus-doped polycrystalline silicon film 14 is patterned, the second layer polycrystalline silicon wiring is formed and a P-channel MOS transistor is manufactured. In this way, the polycrystalline silicon film 14 on a silicon substrate 1 is not exposed at the time of heat treatment and there is no trouble of making an oxidized film whereby a superior ohmic contact is made possible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention mainly relates to a method of manufacturing a semiconductor device in which gates, wiring, and wiring connections in MO8 type transistors of LSI are improved.

[Technical background of the invention and its problems] Metal silicide, which is an alloy of metal and silicon, is used in LSI (
It has been widely used as a material for gate electrodes, wiring, etc. to meet the requirements for miniaturization and speeding up of elements in large-scale integrated circuits. However, in the case of metal silicide, the metal silicide is vapor-deposited onto the semiconductor substrate, and then heat treatment is performed to relieve stress between the semiconductor substrate and the metal silicide, so this heat treatment makes the metal silicide thermally stable. The composition will change. This in turn makes it easier for oxidation to occur on the surface, so if the surface of the metal silicide is exposed during heat treatment in the manufacturing process of semiconductor devices, the surface of the metal silicide will be oxidized and a high-resistance silicon oxide film will be formed. If an attempt is made to make resistive contact (ohmic contact) between the metal silicide and the wiring made of polycrystalline silicon through a contact hole formed in the interlayer insulating film, it will not be possible.

[Purpose of the Invention] The present invention has been made in view of the above circumstances, and it is possible to reduce the contact 1 to the contact hole between the first wiring made of metal silicide and the second wiring made of polycrystalline silicon. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can realize good resistive contact at contact portions, reduce wiring resistance, and enable high integration density.

[Summary of the Invention] In order to achieve the above object, the present invention includes forming at least a first electrode wiring made of metal silicide on an insulating film of a semiconductor substrate, and forming a metal layer at least in a portion of the first electrode wiring where a contact hole is to be formed. After depositing the metal layer, an interlayer insulating film is formed on the entire surface and a contact hole is formed, and a second electrode wiring material is deposited on the interlayer insulating film, or after the contact hole is formed in the metal layer, the contact hole is formed. After the metal layer is deposited on the metal layer, a second wiring material is deposited, and by heat treatment, the metal layer is combined with the first and second electrode wiring materials to form an alloy, thereby reducing the resistance at the contact portion of the wiring. In addition, by forming a metal layer on the entire surface of the first electrode wiring material, alloying with this metal layer is achieved by heat treatment, and the resistance of the first electrode wiring material is lowered by metal silicide. also possible.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Example 1 First, for example, a specific resistance of 1 to 10 Ω・cm, a plane orientation (100
) is selectively oxidized to a thickness of 2000~
After forming the field oxide film 2 of 5,000 layers, thermal oxidation treatment is performed to form a layer of 50 to 50 nm thick on the surface of the island-shaped silicon substrate 1 portion (device region) separated by the field oxide film 2.
A gate oxide film 3 of 0 was formed. Next, the entire surface is coated with polycrystalline silicon 4 with a thickness of 2,000 to 4,000 people, for example.
Molybdenum silicide layer 5 with a thickness of 2000-4000 people
1(a)).

Next, a resist pattern (not shown) is formed on the titanium layer 6 by photolithography, and using this resist pattern as a mask, the titanium layer 6, the molybdenum silicide layer 5, and the polycrystalline silicon 114 are sequentially and selectively etched. A polycrystalline silicon pattern 7, a molybdenum silicide pattern 8, and a titanium pattern 9 were formed in this order from the substrate 1 side. Next, using the resist pattern as a mask, a P-type impurity, such as boron, is added at an acceleration voltage of 3
Ion implantation was performed under the conditions of 0 keV and a dose of 115×10° lSclm4. After this, remove the resist pattern and
Activation treatment was performed to form P+ type source and drain regions 10.11 in the island-shaped substrate 1fR region (as shown in FIG. 1(b) and FIG. 2). Note that FIG. 2 is a plan view of FIG. 1(b).

Next, the entire surface was coated with a thickness of 3,000 people as an insulating film between the eyebrows.
After depositing the VD-8i02 film 12, selective etching is performed to form a contact hole 1 in the CVD-8i02 film 12.
3 was drilled (see Figure 1). Next, L was drilled on the entire surface.
PCVD (Low Pressure Chemlca
The thickness is 30 mm using the Vaper Deposition method.
6- (as shown in FIG. 1(d)) in which polycrystalline silicon 114 was deposited.

Next, phosphorus was diffused or ion-implanted into the polycrystalline silicon film 14 and heat treated to dope the polycrystalline silicon film with phosphorus. Through this heat treatment, the titanium pattern 9 and the molybdenum silicide pattern 8 reacted to form an alloy pattern 15 thereof. At the same time, in the vicinity of the contact I/hole 13, the titanium pattern 9 reacted with the polycrystalline silicon film 14 in contact with the underlying molybdenum silicide pattern 8 and the contact hole 13 to form an alloy layer 16 thereof. Note that through these steps, the polycrystalline silicon pattern 7,
A gate electrode 17 consisting of the remaining molybdenum silicide pattern 8' and the alloy pattern 15 is formed (as shown in FIG. 1(e)).

Next, the phosphorus-doped polycrystalline silicon film 14 was patterned to form a second layer of polycrystalline silicon wiring connected to the gate electrode 17 via the alloy layer 16 in the contact hole 13, thereby manufacturing a P-channel MOS transistor. .

In the semiconductor device manufactured in this way as shown in FIG. 1(e), a polycrystalline silicon pattern 7 is provided on a semiconductor substrate 1, a residual molybdenum silicide pattern 8' is formed on the polycrystalline silicon pattern 7, and an alloy pattern 15 is formed on the remaining molybdenum silicide pattern 8'. The upper layer of this alloy pattern 15 is covered with an interlayer insulating film 12, and a wiring 14 made of polycrystalline silicon formed on this interlayer insulating film 12 is connected to the alloy pattern 15 of the gate electrode through a contact hole 13. It is connected.

Since this alloy pattern 15 is formed by alloying the molybdenum film 5 and titanium 116 deposited on the polycrystalline silicon film 14 through heat treatment, the surface of the polycrystalline silicon film 14 on the silicon substrate 1 is exposed during the heat treatment. Since this does not occur, there is no concern that an oxide film will form, and good ohmic contact is therefore possible. Moreover, since an ohmic connection is made between the wiring 14 and the remaining molybdenum silicide pattern 8' by a low resistance alloy pattern, a low resistance of the polycide can be realized. At this time, the sheet resistance of the wiring portion was several 100 mΩ·am, and the contact resistance was several Ω·cm. In addition, in the conventional method, the contact resistance becomes as large as 1Ω to 1MΩ.

Example 2 First, for example, a specific resistance of 1 to 1 oΩ・cm in one plane orientation (100
) is selectively oxidized to a thickness of 2000~
After forming 5,000 field oxide films 1 to 2, a thermal oxidation process is performed to form a layer of 50 to 50 nm thick on the surface of the island-shaped silicon substrate 1 portion (device region) separated by the field oxide film 2.
A gate oxide film 3 of 0.00 people was formed. Next, a polycrystalline silicon film 4 with a thickness of, for example, 2,000 to 4,000 people is applied to the entire surface.
, a molybdenum silicide layer 5 having a thickness of 2,000 to 4,000 layers was sequentially deposited (as shown in FIG. 3(a)).

Next, a resist pattern (not shown) is formed on the titanium layer 6 by photolithography, and using this resist pattern as a mask, the molybdenum silicide layer 5 and the polycrystalline silicon film 4 are sequentially and selectively etched to form the substrate 1 side. A polycrystalline silicon pattern 7 and a molybdenum silicide pattern 8 were formed in this order. Next, P using the resist pattern as a mask.
A type impurity, for example, boron, was ion-implanted under the conditions of an acceleration voltage of 30 keV and a dose of 5 x 101"α. After this,
The resist pattern was removed and activation treatment was performed to form P+ type source and drain regions 10.11 in the island-shaped substrate 1 region (as shown in FIG. 3(b)).

Next, the entire surface was coated with a thickness of 3000 mm as an interlayer insulating film.
After depositing the VD-8102 film 12, selective etching is performed to form a contact hole 1 in the CVD-8102 film 12.
3 was drilled (as shown in FIG. 3(C)).

After this step, tungsten was deposited in the contact hole 13 made in the interlayer insulating film 12, and a tungsten layer 21 was formed only in this portion (as shown in FIG. 3(d)).

Next, a polycrystalline silicon layer was deposited on the entire surface by the LPCVD method, and after heat treatment was performed, the polycrystalline silicon layer was etched to form a wiring 22 made of polycrystalline silicon. As a result, an alloy layer 23 of the polycrystalline silicon pattern 7 forming the electrode, the molybdenum silicide pattern 8, and the wiring pattern 22 was formed in the contact hole 13 (FIG. 3(e) box). .

In such a semiconductor device, a gate electrode made of a polycrystalline silicon pattern 7 and a molybdenum silicide pattern 8 and a wiring 22 formed on an interlayer insulating film 12 are in contact with each other via an alloy layer 23 in a contact hole 13. Therefore, as in Embodiment 1, the gate electrode is not connected to the resistive layer by the alloy layer, so it is not possible to reduce the wiring resistance. It is possible to reduce the resistance at

Nao, in Example 2, the means for forming a metal layer only in the contact hole of the CVD-8102 film was as follows:
This can be achieved by depositing a metal layer on the VD-8I O2 film, alloying the metal layer and the molybdenum silicide layer at the contact hole portion by heat treatment, and then removing the unreacted metal portion. Furthermore, before alloying, patterning may be performed so that the metal remains only in the contact portion.

Further, in the above embodiment, a two-layer structure of a polycrystalline silicon pattern 7 and a molybdenum silicide pattern 8 was used on the electrode side, but the above-mentioned effects can be sufficiently obtained with other metal silicides or a single-layer structure. Also. Further, metal or metal silicide may be used for the second layer wiring.

[Effects of the Invention] As described in detail above, according to the present invention, metal is deposited and alloyed on the metal silicide forming the electrode wiring at least in the contact hole portion, so that the second metal silicide in the contact hole portion is Therefore, even if metal silicide is used for electrodes and wiring materials, it is possible to lower contact resistance and shorten signal delay time, making it possible to improve the fineness of integrated circuits. Accordingly, it is possible to provide a method for manufacturing a semiconductor device, which has features such as speedup and speedup.

[Brief explanation of drawings]

Figures 1(a) to (e) are process diagrams showing one embodiment of the present invention, Figure 2 is a plan view of Figure 1(b), and Figures 3(a) to (e).
) is a process chart showing another embodiment of the present invention. 1...Silicon substrate, 2.3.12...Oxide layer, 4
゜14... Polycrystalline silicon film, 5... Metal silicide layer, 6... Titanium layer, 7... Polycrystalline silicon pattern, 8... Molybdenum silicide pattern, 9...
・Titanium pattern, 10...source region, 11...
Drain region, 12.=CVD-8I O2, 13-contour') Tor*-tour, 15... Alloy pattern, 16
．． 23... Alloy layer, 21... Tungsten layer, 22
···wiring. Applicant's representative Patent attorney Takehiko Suzue 13- ＾ He-D. Figure 3 Figure 3 Figure 2 Koma

Claims (1)

[Scope of Claims] <1) A step of forming at least a first electrode wiring made of metal silicide on an insulating film of a semiconductor substrate, and depositing a metal layer at least in a portion of the first electrode wiring where a contact hole is to be formed. , a step of forming an interlayer insulating film on the entire surface and forming a contact hole, and after depositing a second electrode wiring material on the interlayer insulating film, heat treatment or buttering the second electrode wiring material. A method of manufacturing a semiconductor device, comprising the steps of: heat-treating the metal layer, or alloying the metal layer and first and second electrode wiring materials to form an ohmic connection. (2) The method of manufacturing a semiconductor device according to claim 1, wherein the metal layer is formed on the entire upper surface of the first electrode wiring. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the first electrode wiring has a two-layer structure of a polycrystalline silicon layer and a metal silicide layer formed on the upper surface of the polycrystalline silicon layer. (4) After forming at least a first electrode wiring made of metal silicide on the insulating film of the semiconductor substrate, forming an interlayer insulating film over the entire area including the first electrode wiring, and forming a contact hole in the interlayer insulating film. a step of depositing a metal layer in the contact hole; and a step of depositing a second electrode wiring material on the interlayer insulating film and then heat-treating it, or patterning the second electrode material and heat-treating it. A method for reporting a semiconductor device, comprising the step of alloying the metal layer and first and second electrode wiring materials to form an ohmic connection.