JPS6020638U - Matrix input circuit - Google Patents
Matrix input circuitInfo
- Publication number
- JPS6020638U JPS6020638U JP10894683U JP10894683U JPS6020638U JP S6020638 U JPS6020638 U JP S6020638U JP 10894683 U JP10894683 U JP 10894683U JP 10894683 U JP10894683 U JP 10894683U JP S6020638 U JPS6020638 U JP S6020638U
- Authority
- JP
- Japan
- Prior art keywords
- input circuit
- matrix input
- circuit
- switch circuit
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electronic Switches (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はマトリックス入力回路の一般例を示す回路図、
第２図はその出力波形図、第３図ａは制御信号によって
開閉する電子スイッチの従来例を示す回路図、第３図す
はその等価回路、第４図ａは本考案の一実施例を示す回
路図、第４図すはその等価回路、第５図は本考案の他の
実施例を示す回路図である。
１：マイクロプロセッサ、０１〜Ｇ６：相出力端子、Ｋ
１−に、二人尖端子、８１〜Ｓ２４：スイッチ、Ｑ□：
ＰＮＰ トランジスタ、Ｑ□′：ＮＰＮトランジスタ
、Ｑ工″：ＰＮＰトランジ及夕、Ｒ１：抵抗。Figure 1 is a circuit diagram showing a general example of a matrix input circuit.
Fig. 2 is an output waveform diagram, Fig. 3a is a circuit diagram showing a conventional example of an electronic switch that opens and closes according to a control signal, Fig. 3 is its equivalent circuit, and Fig. 4a is an example of an embodiment of the present invention. FIG. 4 is an equivalent circuit thereof, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. 1: Microprocessor, 01-G6: Phase output terminal, K
1-, two-point terminal, 81-S24: switch, Q□:
PNP transistor, Q□': NPN transistor, Q': PNP transistor, R1: resistor.
Claims (1)
子にスイッチ回路を設け、該スイッチ回路は、通常はグ
ランド又は電源に接続されており、この接続を解除する
制御手段を設けたことを特徴とするマトリックス入力回
路。 ２、上記マトリックス入力回路において、上記スイッチ
回路はトランジスタ等の半導体スイッチ素子によって電
気的に接続の解除ができることを特徴とする実用新案登
録請求の範囲第１項記載のマトリックス入力回路。1. The phase output terminal and the input terminal are connected by a resistor, a switch circuit is provided at the input terminal, and the switch circuit is normally connected to ground or a power supply, and a control means is provided to disconnect this connection. Characteristic matrix input circuit. 2. The matrix input circuit according to claim 1, wherein the switch circuit can be electrically disconnected by a semiconductor switch element such as a transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10894683U JPS6020638U (en) | 1983-07-15 | 1983-07-15 | Matrix input circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10894683U JPS6020638U (en) | 1983-07-15 | 1983-07-15 | Matrix input circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020638U true JPS6020638U (en) | 1985-02-13 |
Family
ID=30253979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10894683U Pending JPS6020638U (en) | 1983-07-15 | 1983-07-15 | Matrix input circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020638U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61195138U (en) * | 1985-05-15 | 1986-12-05 |
-
1983
- 1983-07-15 JP JP10894683U patent/JPS6020638U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61195138U (en) * | 1985-05-15 | 1986-12-05 |
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