JPS60205674A - Image data expansion processing device - Google Patents

Abstract

PURPOSE:To realize easily and at high speed minute angle rotation when outputting picture information by using a vector generator to rotate image data. CONSTITUTION:Compression coded image data from a host computer 1 are restored to a dot image through an image expander 16 and stored in specified position of an image memory 12. The content of the memory 12 is read out laterally, parallel/series converted 14 and supplied to a video controller 9, and a picture is displayed by a CRT device 10. A vector generator 15 generates an address of oblique direction following DELTAX and DELTAY in the memory 12. Accordingly, by generating an address of oblique direction by the generator 15 and generating image data by the expander 16 synchronizing with above-mentioned process and writing in the memory 12, the image data can be rotated.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to an image data development processing device, particularly for example, when image data input from a scanner is input diagonally due to misalignment of paper, etc. The present invention relates to an image data development processing device that corrects data by rotating it by a small angle in the opposite direction.

(B) Technical Background and Problems Recently, digital processing of images has become popular, and it is desired to output image data input from a scanner, facsimile, etc., to a CRT display, printer, etc., for example.

FIG. 1 shows a diagram for explaining the background of the technology.

For example, when image data of an original pattern as shown in FIG. 1(a) is inputted by a scanner, the sheet of paper with the original pattern is diagonally shifted as shown by the dotted line in FIG. 1(b) with respect to the scanning direction of the scanner. If so, the pattern of the input image data will be as shown in FIG. 1(c). It is not desirable to output such image data as is to a display, printer, etc. because it looks bad.

Therefore, it is essential to rotate the input image data by a small angle in the opposite direction and correct it so that a pattern similar to the original pattern is output.

Conventionally, in order to correct misalignment of paper during input,
When image data is rotated by a small angle, correction calculations are performed on the image data represented by dots under the control of, for example, a microprocessor, and each dot is read out and written at the calculated correction position. Therefore, there is a problem in that the minute angle rotation processing required for this correction takes a very long time.

(C) Object and Structure of the Invention The present invention aims to solve the above-mentioned problems, and is capable of outputting image information such as character data, graph data, image data, etc. to a display or a printer without spending a lot of time. The purpose is to enable rotation. Therefore, the image data development processing device of the present invention includes an image memory in which dot-patterned image data is stored, and rotates a pattern obtained from given data and develops it in the image memory. a vector generator that generates an image memory address in the diagonal direction on the image memory according to the displacement, and a vector generator that synchronizes each bit of the dot patterned image data with the image memory address generated by the vector generator. and an image memory control unit that controls writing to the image memory,
It is characterized by rotating image data. Hereinafter, embodiments will be described with reference to the drawings.

(D) Embodiment of the Invention Fig. 2 is an example of the configuration of a display system using the present invention, Fig. 3 is a diagram illustrating the composition of character data and the contents of an image memory, and Fig. 4 is a diagram illustrating the combination of character data and the contents of an image memory. A diagram for explaining address generation, FIG. 5 is an example of the configuration of a vector generator, FIG. 6 is an explanatory diagram of the control state of the vector generation controller, FIG. 7 is an example of the configuration of an image decompressor, and FIG. 8 is the invention of the present invention. FIG. 2 is a diagram illustrating a processing mode of an embodiment.

In the figure, l is the host computer, 2 is the host interface,
3 is a microprocessor, 4 is a memory, 5 is a CRT controller, 6 is a code buffer, 7 is a character generation memory, 8 is a parallel to serial converter, 9 is a video controller, 10
is a CRT display, 11 is an image memory controller, 12 is an image memory, 13 is a read buffer,
14 represents a parallel-to-serial converter, 15 represents a vector generator, and 16 represents an image decompressor.

Although the present invention is not limited to controlling data displayed on a display, the display shown in FIG.
This will be explained using a system as an example. The host computer 1 is a device that processes image information input from, for example, a scanner or facsimile, and is a device that supplies data to be displayed on the CRT display 10 via the host interface 2. These data include, for example, character data consisting of code information, graph data consisting of vector information, data obtained by compressing dot pattern image data, and the like. The microprocessor 3 is a device that performs display control based on instructions stored in the memory 4 in advance in order to display image data at the correct angle on the CRT display 1o in accordance with a request from the host computer 1.

If the data transferred from the host computer 1 is character data, the character code is stored in the code buffer 6 according to the character display position. Code buffer 6 is
As shown in FIG. 3, the buffer memory is made up of, for example, 48 horizontal characters x 64 vertical lines, and stores one character code in one character position. The character codes on the code buffer 6 are read out horizontally one character at a time under the control of the CRT controller 5, and the character generation memory 7 is accessed using this address as an address, where it is converted into a character pattern of dots. . The character generation memory 7 is a ROM for a character generator.

The character pattern obtained from the character generation memory 7 is converted into serial data by a parallel-to-serial converter 8 and input to a video controller 9.

When the data transferred from the host computer 1 is graph data, by setting its displacement in the vector generator 15, a graph pattern is developed into dots on the image memory 12, as will be described in detail later.

In the case of image data, since image data usually has a large amount of data, compression encoding such as the MH method, which is known as a facsimile image encoding method, is used. When compression-encoded image data is sent from the host computer 1, the image data is restored to a dot image through an image decompressor 16, which is a decoder, and is stored in a designated location on the image memory 12.

The image memory 12 is connected to the image memory controller 1
The X address (XAR) and Y address (YA
This is a bit map memory addressed by R), and has a size of, for example, 768 dots horizontally by 1024 dots vertically. Graph data and image data are stored in a dot pattern on the image memory 12 one dot at a time while updating the X address and Y address. To display the contents of the image memory 12 on the CRT display 1°, under the control of the CRT controller 5, 32 bits of the contents of the image memory 12 are read in the horizontal direction and set in the read buffer 13, and then the parallel to serial converter 14 The data is parallel-to-serial converted and supplied to the video controller 9 one bit at a time. As a result, an image will be displayed on the CRT display 10.

The character data and the contents of the image memory 12 are synthesized as shown in FIG. 3, and when input to the video controller 9, they are synthesized by performing a logical sum between the dots.

Note that the output of the character generation memory 7 may be controlled to be written directly into the corresponding position of the image memory 12 using OR logic.

A digital differential analyzer (DDA) method is well known as a method for drawing straight lines on a bitmap memory. Hereinafter, according to Figure 4, point A (
0,0) to point B (ΔX.

A case in which a straight line is drawn to ΔY) will be briefly explained.

■ Write “1” on the memory corresponding to point A.

■ Set the initial value ΔY to ΣΔY and perform the following evaluation and processing ■.

■(i) When ΣΔY is ΔX/2 or more, x=x+1 Y=Y+1 ΣΔY=ΣΔY+ΔY−ΔX shall be.

(ii) When ΣΔY is smaller than ΔX/2, X=X+
1 Y=Y ΣΔYmi ΣΔY+ΔY.

(2) Draw a dot at the X and Y positions updated by the result of (2) and continue the evaluation and processing (2).

■ When X becomes ΔX, end the process.

The vector generator 15 is constructed as shown in FIG. 5, and generates a straight line graph pattern according to the D()A method, for example. In FIG. 5, 2o to 22 are respectively Δ
12-bit registers each holding X, ΔY, and ΣΔY;
Reference numeral 23 represents a 12-bit wide arithmetic unit having addition, subtraction and comparison functions, 24 represents a vector generation controller, and 25 represents an address register.

The arithmetic unit 23 compares ΔX/2 and ΣΔY, and outputs a 1-bit signal indicating the comparison result. Based on the signal of this comparison result, the vector generation controller 24 sets the X address XAR of the address register 25.
, Y address YAR, and the vector generation controller 24 controls the updating of ΣΔY, and the arithmetic unit 23 performs addition of ΣΔY and ΔY, leads the result to the register 22, and further performs the above-mentioned process. Depending on the comparison result, control is performed to subtract ΔX from ΣΔY. The dot expansion of the vector into the image memory 12 is the updated
This is done by writing 1-bit data of "1" to the positions of address XAR and Y address YAR.

FIG. 6 shows the control state of the vector generation controller 24, and in stage 1-3l, the arithmetic unit 23 compares ΔX/2 and ΣΔY, and moves to the location of the non-terge memory 12 specified by XAR and YAR. is written. At stay 1-32, ΣΔY and ΔY are added,
A new ΣΔY is set, and 1 is added to each of XAR and YAR according to the comparison result in stay) Sl. In state S3, when ΣΔY is greater than or equal to ΔX/2, a process of subtracting ΔX from ΣΔY is executed.

Next, a configuration example of the image decompressor 16 will be explained with reference to FIG. Note that the compression code is an MH code. In FIG. 7, 30 represents a shift register, 31 a shift control section, 32 an MH child table OM, 33 an MH register, and 34 an image output control section.

Compressed data supplied from the host computer is input from the memory to the SR1 section of the shift register 30. When the SR0 section is empty, the data in the SR1 section is left-shifted and packed to the left end of the SR0 section.

MH child table OM using the upper 13 bits of SR0 part
32 is accessed, and the read data is set in the MH register 33. MH child table OM32 is M
This is a read-only memory that stores the code length and run length of the MH code at the address corresponding to the H code.

A code length is set in the upper part of the MH register 33, indicating the code length of the MH code at the left end of the SR0 part. M
A count value indicating the run length of white dots or black dots is set in the lower part of the H register 33. This count value is sent to the image output control section 34, and white bits "θ" or black bits "1" corresponding to the length of the count value are output as image data. This output will be written to the image memory 12 shown in FIG.

The code length set in the MH register 33 is sent to the shift control section 31, and the shift control section 31 shifts both the SR0 section and the SR1 section of the shift register 30 to the left by the number of codes. By this left shift, SR
When one copy becomes empty, the next compressed data is set and decoding is repeated in the same way. Similarly, when the compression code is not an MH code, a well-known image decompressor can be used.

As explained in FIGS. 4 and 5, the vector generator 15 has a function of generating diagonal addresses on the image memory 12 according to ΔX and ΔY. Therefore, when performing correction by rotating the image data by a small angle, each scan line of the image data may be written on a diagonal line designated by ΔX and ΔY, as shown in FIG. That is, when the vector generator 15 generates an address in the diagonal direction, the image data is generated by the image decompressor 16 in synchronization with this, and is written into the image memory 12, thereby making it possible to rotate the image data.

The rotation of image data as shown in FIG. 8 is performed by the image memory controller 11 shown in FIG. 2 under the following control.

For the first line (Ll) of image data, XAR, MA
The initial values xo and y of the start coordinates are set in R, the number of horizontal dots XD is set in ΔX, and the displacement YD is set in ΔY.

Then, in synchronization with the output bits of the image decompressor 16,
The vector generator 15 is operated to write image data to the image memory 12.

In the case of the second line (L2) of the image data, the addresses of the coordinates X+, Y+ of the second line are as follows: 0For example, if two vector generator circuits shown in Figure 5 are prepared independently, , one vector generator circuit calculates the horizontal address of the image data, and the other vector generator circuit calculates the vertical diagonal address of the image data once per horizontal row, Set this to MAR, YAR.

If there is only one vector generator circuit, the microprocessor 3 shown in FIG. Determine the Y r address using the method explained in Fig. 4, and convert it to XAR,
Set it to YAR.

Comparing the case of using two vector generator circuits and the case of using only one, using only one circuit slows down the processing, but when calculating all dot positions with a microprocessor as in the past, In comparison, the number of calculations is l/XD
(However, XD is the number of horizontal dots in the image data.) For example, if XD is 300 dots, the number of calculations is 1/300, so the calculation time is significantly shortened.

The present invention has been described above using an example in which the present invention is applied to a display system, but the present invention can be similarly applied to a device that rotates image data by a small angle and outputs the image data to a printer, for example.

(E) Detailed Description of the Invention As described above, according to the present invention, image data can be rotated by a small angle easily and at high speed by using a vector generator.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the background of the technology, FIG. 2 is a configuration example of a display system using the present invention, FIG. 3 is a diagram for explaining the composition of character data and the contents of an image memory, and FIG. Figure 4 is a diagram for explaining address generation by a vector generator, Figure 5 is a configuration example of a vector generator, and Figure 6 is a diagram for explaining address generation by a vector generator.
The figure is an explanatory diagram of the control state of the vector generation controller.
FIG. 7 shows an example of the configuration of an image decompressor, and FIG. 8 shows a diagram illustrating a processing mode of an embodiment of the present invention. In the figure, 1 is the host computer, 2 is the host interface,
3 is a microprocessor, 4 is a memory, 5 is a CRT controller, 6 is a code buffer, 7 is a character generation memory, 10 is a CRT display, 11 is an image memory controller, 12 is an image memory, 15 is a vector generator, 16 is a Represents an image stretcher. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney Hiroshi Mori 1) (1 other person) 1 Figure 3 Figure 4 Figure O 6 O 6 times

Claims (1)

[Claims] In an apparatus that includes an image memory in which dot-patterned image data is stored, and rotates a pattern obtained from given data and develops it in the image memory, a diagonal direction on the image memory is changed according to a specified displacement. a vector generator that generates an image memory address; and an image memory control unit that controls writing each bit of dot patterned image data into the image memory in synchronization with the image memory address generated by the vector generator. An image data expansion processing device comprising: and rotating image data.