JPS60202911A - Chip type surge absorber - Google Patents

Chip type surge absorber

Info

Publication number
JPS60202911A
JPS60202911A JP6144284A JP6144284A JPS60202911A JP S60202911 A JPS60202911 A JP S60202911A JP 6144284 A JP6144284 A JP 6144284A JP 6144284 A JP6144284 A JP 6144284A JP S60202911 A JPS60202911 A JP S60202911A
Authority
JP
Japan
Prior art keywords
type surge
electrode
chip
surge absorber
chip type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6144284A
Other languages
Japanese (ja)
Inventor
海老根 一英
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP6144284A priority Critical patent/JPS60202911A/en
Publication of JPS60202911A publication Critical patent/JPS60202911A/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、電子機器を誘導雷等の異常電圧から保護する
非直線抵抗器でプリント基板等に直接接続するり一ドレ
ス角板状のチップ形サージ吸収器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a non-linear resistor that protects electronic equipment from abnormal voltages such as induced lightning, and is a non-linear resistor that is directly connected to a printed circuit board or the like. It concerns absorbers.

従来例の構成とその問題点 近年電子回路の小形化が急速に進み、その構成要素であ
る電子機器の小形化、特にプリント基板に直接組み込み
可能なチップ化された電子部品が市場から強くめられて
いる。IC,トランジスタなどの半導体を誘導雷等の異
常電圧から保護するために用いるサージ吸収器において
も同様に小形化ならびにチップ化が強く望まれている。
Conventional configurations and their problems In recent years, the miniaturization of electronic circuits has progressed rapidly, and the market has strongly demanded miniaturization of the electronic devices that are their components, especially chip-based electronic components that can be directly integrated into printed circuit boards. ing. Similarly, there is a strong desire for surge absorbers used to protect semiconductors such as ICs and transistors from abnormal voltages caused by induced lightning to be miniaturized and chipped.

以下、図面を参照しながら上述したような従来のチップ
形サージ吸収器について説明を行う。
Hereinafter, a conventional chip type surge absorber as described above will be explained with reference to the drawings.

第1図は、従来のチップ形サージ吸収器で、1は、酸化
亜鉛よりなるバリスタ素体で、2及び3はバリスタ素体
1に設けられた電極で端面を含んで各々の面の一部を連
接して設けられている。図示していないが通常、耐候性
能を良くするため、端面部近辺を除いてエポキシ樹脂等
の保護被覆が形成されている。この端面部がプリント基
板に直接ハンダ付けされる。ところで、サージ吸収器は
、サージ耐量を大きくとるため、数個並列接続して使用
されることが多いが、従来のチップ形サージ吸収器では
、プリント基板上だけでの接続になるため個々の間の距
離を離して個々の端面電極がプリント基板にしっかシ接
続する必要があり、またプリン1基板自体を折シ曲げる
テスト等に弱い欠点があった。
Figure 1 shows a conventional chip-type surge absorber, in which 1 is a varistor body made of zinc oxide, 2 and 3 are electrodes provided on the varistor body 1, and part of each surface including the end face. are arranged in a connected manner. Although not shown, in order to improve weather resistance, a protective coating such as epoxy resin is usually formed except for the vicinity of the end face. This end face portion is directly soldered to the printed circuit board. By the way, surge absorbers are often used by connecting several pieces in parallel in order to increase surge resistance, but with conventional chip-type surge absorbers, connections are made only on the printed circuit board, so there is no need to connect the individual surge absorbers. It is necessary to securely connect each end face electrode to the printed circuit board at a distance of 100 mm, and there is also a drawback that it is difficult to perform tests such as bending the printed circuit board itself.

発明の目的 本発明は上記欠点に鑑みてなされたものであり、バリス
タ素体の片刃の面の両端部に溝を設け、チップ形サージ
吸収器を並列に接続するのにこの溝部にリード線を埋め
込んだ形で・・ンダ等により接続することで強固な並列
接続を可能にするチップ形ザージ吸収器を提供するもの
である。
Purpose of the Invention The present invention has been made in view of the above-mentioned drawbacks, and it is necessary to provide grooves at both ends of the single-edged surface of the varistor body, and to insert lead wires into the grooves to connect chip-type surge absorbers in parallel. The present invention provides a chip-type surge absorber that enables a strong parallel connection by being connected in an embedded form with a connector or the like.

発明の構成 この目的を達成するため本発明のチップ形サージ吸収器
は、板状のバリスタ素体の片方の面の両端部近辺に溝を
設け、この溝を含んで表裏者々の面に一方の端面部と連
接し、上記溝に対応する部分に溝を有する電極を設ける
構成とし、この構成とすることにより、チップ形サージ
吸収器の並列接続が強固に行えることになる。
Structure of the Invention In order to achieve this object, the chip-type surge absorber of the present invention has grooves near both ends of one side of a plate-shaped varistor element body, and includes grooves on the front and back surfaces of the plate-shaped varistor body. An electrode is provided with a groove in a portion corresponding to the groove, which is connected to the end face of the electrode, and with this configuration, the chip type surge absorbers can be connected firmly in parallel.

実施例の説明 以下本発明の一実施例について図面を参照しながら説明
する。第2図は本発明の一実施例におけるチップ形サー
ジ吸収器の斜視図である。4は、板状のバリスタ素体で
、例えば酸化亜鉛を主成分とする焼結体である。6及び
6は、バリスタ素体4の一方の面に設けた溝で、7は、
この一方の溝6を含む面に設けられた電極で、端面部電
極8及びバリスタ素体4の他方の面の一部に設けられた
電極9と連接している。まだ、この電極7にも溝6′が
形成される。10は、もう一つの溝5を含む面に設けら
れた電極で、端面部電極11及びバリスタ素体4の他方
の面に設けられた電極12と連接している。そして、こ
の電極10にも溝5′が形成されている。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a perspective view of a chip type surge absorber in one embodiment of the present invention. Reference numeral 4 denotes a plate-shaped varistor body, which is, for example, a sintered body containing zinc oxide as a main component. 6 and 6 are grooves provided on one surface of the varistor body 4, and 7 is
This electrode is provided on the surface including the groove 6 and is connected to the end surface electrode 8 and the electrode 9 provided on a part of the other surface of the varistor body 4 . A groove 6' is still formed in this electrode 7 as well. Reference numeral 10 denotes an electrode provided on a surface including another groove 5, and is connected to an end surface electrode 11 and an electrode 12 provided on the other surface of the varistor body 4. A groove 5' is also formed in this electrode 10.

以上のように構成されたチップ形サージ吸収器について
以下その効果を説明する。
The effects of the chip type surge absorber configured as above will be explained below.

第3図は、本発明によるチップ形サージ吸収器を2個並
列接続した例を示す斜視図である。13及び14は溝5
’、 6’がそろうように並べられた2個のチップ形サ
ージ吸収器の溝s/ 、 e/に埋め込むようにハンダ
等で接続されたリード線を示す。
FIG. 3 is a perspective view showing an example in which two chip type surge absorbers according to the present invention are connected in parallel. 13 and 14 are grooves 5
The lead wires are shown embedded in the grooves s/ and e/ of two chip-type surge absorbers arranged so that the `` and 6 '' lines are aligned and connected with solder or the like.

発明の効果 このように本発明のチップ形サージ吸収器は構成される
ことによって2個のチップ形サージ吸収器を間隔をあけ
ずにぴったりとくっつけて並列接続することができ、ま
た、接続のためのハンダ等が溝部を有するため盛シ上り
高さが高くなることもない。又、リード線によって強固
に接続されることによシブリント基板自体を折シ曲げる
テスト等によっても、並列接続がはずれることはなくな
るなどの利点をもち、実用的価値の犬なるものである。
Effects of the Invention By configuring the chip type surge absorber of the present invention in this way, two chip type surge absorbers can be tightly connected in parallel without any gap, and it is possible to connect two chip type surge absorbers in parallel. Since the solder and the like have grooves, the height of the solder does not become high. In addition, since it is firmly connected by a lead wire, it has the advantage that the parallel connection will not be disconnected even in a test in which the shiblint board itself is bent, so it is of great practical value.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のチップ形サージ吸収器の斜視図、第2図
は本発明によるチップ形サージ吸収器の一実施例の斜視
図、第3図は本発明によるチップ形サージ吸収器を2個
並列接続した状態を示す斜視図である。 4・・・バリスタ素体、5,6・・・溝、7.10・ 
電極、8,11 ・端面部電極、9,12・・・・電極
、5/ 、 e L・・・・・・電極に設けた溝。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 第2図 第3図
FIG. 1 is a perspective view of a conventional chip-type surge absorber, FIG. 2 is a perspective view of an embodiment of the chip-type surge absorber according to the present invention, and FIG. 3 is a perspective view of two chip-type surge absorbers according to the present invention. FIG. 3 is a perspective view showing a state in which the devices are connected in parallel. 4... Varistor body, 5, 6... Groove, 7.10.
Electrode, 8, 11 - End surface electrode, 9, 12... Electrode, 5/, e L... Groove provided in the electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 板状のバリスタ素体の片方の面の両端部近くに溝を設け
、この溝を含んで表裏者々の面に一方の端面部と他方の
面の一部に連接し、上記溝に対応する部分に溝を有する
電極を設け、この電極の溝にリード線を埋め込み可能な
構成としたチップ形サージ吸収器。
Grooves are provided near both ends of one surface of the plate-shaped varistor body, and the front and back surfaces including this groove are connected to one end surface and a part of the other surface, corresponding to the grooves. A chip-type surge absorber that has an electrode with a groove in its part and a structure in which a lead wire can be embedded in the groove of the electrode.
JP6144284A 1984-03-28 1984-03-28 Chip type surge absorber Pending JPS60202911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6144284A JPS60202911A (en) 1984-03-28 1984-03-28 Chip type surge absorber

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6144284A JPS60202911A (en) 1984-03-28 1984-03-28 Chip type surge absorber

Publications (1)

Publication Number Publication Date
JPS60202911A true JPS60202911A (en) 1985-10-14

Family

ID=13171182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6144284A Pending JPS60202911A (en) 1984-03-28 1984-03-28 Chip type surge absorber

Country Status (1)

Country Link
JP (1) JPS60202911A (en)

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