JPS60201600A - Mos type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the circuit from being destroyed by using a detecting and protecting function so as to turn on an MOS transistor (TR) in the ON-state if an output terminal is short-circuited to a power supply of inverse level due to mis-operation thereby preventing the MOSTR from flowing steadily a large current. CONSTITUTION:If the user short-circuits an output terminal 5 in error to a common point (L level) of an inverting level at read of ''1'' (output H level), since an MOSTRT7 is turned on, a point (d) goes from an H level to an L level, an MOSTRT9 is turned off and the level of a point (e) changes from the L level to the H level. Then the MOSTRT11 is turned on, the level of a point (a) changes from the H level to the L level and an MOSTRT3 is turned off so as to block a large current from flowing to the MOSTRT3. Thus, the output terminal 5 brought into the L level due to short-circuit is brought into the floating state. Thus, the destruction of the MOSTRT3 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an MO8 type semiconductor integrated circuit applied to an output buffer 7 of a MOS memory.

[Background technology] - The inventor of this invention is a non-volatile memo! We have developed various MOS memory ICs such as J (ROM, EFROM, etc.).

FIG. 1 shows the λ4 calculated by the inventor prior to filing this application.
A circuit block diagram of the main parts of the OS memory IC is shown. That is, in FIG. 1, 1 is a memory cell array,
2 is a sense amplifier, 3 is an output driver, and 4 is an output buffer, and this output buffer 7 receives logic "L" (H level) and logic "0" (L level) outputs from the output driver 3. configured to be supplied. Output buffer 4
In, T.

˜T is an enhancement type n-channel MOS transistor (MOS) transistor T.

For example, the threshold voltage Vth+ of -0, IV, MOS
Threshold voltages Vth2 to V of transistors T2 to T4
th4 is the same, for example +0.3V. Furthermore, VCC
is +5v.

Here, the configuration is such that the output of the output driver 3 is supplied to the gate electrodes of the MOS transistors T, , T,. The source and drain electrodes of MOS transistors T and T are connected in series between the power supply VCC and ground as shown. The connection point between the source electrode of the MO8l transistor T and the drain electrode of the Mos transistor T2 is connected to the 1'VO8) transistor T, NO'l-) electrode. Furthermore, the gate electrode of the MOS transistor T is connected to the gate electrode of the MOS transistor T3, and the source and drain electrodes of the MOS transistor T3 and MOS transistor T4 are connected in series to the power supply voltage Vcc and ground. connected between. And λ408) Source electrode of transistor T and MOS
An output terminal (output pin) 5 is taken out from the connection point with the drain electrode of the transistor T.

In the output buffer 4 of the MOS memory IC configured in this way, when "1" is read at 7 o'clock (at H level) and at 0
When reading "" (at L level), the FC user (customer) may mistakenly use the output terminal 5.For this reason, when reading "】", the output terminal 5 may be mistakenly connected to the ground side as shown by the dotted line in the figure. If short-circuited, the distance will be several tens of meters as shown in the diagram.
MOS) transistor T in which a large current I of A is in the on state
If the output terminal 5 is short-circuited to the power supply +VCC side when reading "0", the MO
S) The inventor of the present invention has revealed that a problem arises in that the transistor T4 is similarly destroyed.

[Purpose of the invention]

The purpose of the present invention is to immediately detect when the output terminal is at H level or L level and short circuit the output terminal to the L level or H level power supply side, respectively, due to misuse. Turns off the MOS transistor located in the
g) A MOS type semiconductor capable of preventing a large current from constantly flowing through the MO3) transistor in the state 1-1 MO8) The transistor can be prevented from being destroyed and its reliability can be improved. The purpose is to capture and provide integrated circuits.

The above and other objects and novel features of the present invention are:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the output electrode side has two MOS transistors connected in series, the series body of these MOS transistors is connected between two different power supplies, and one of the input electrodes of the two MOS transistors is turned on. A control signal is supplied to turn off the other one, and the output terminal is taken out from the connection point on the output electrode side of the two MOS transistors.
In the OS type semiconductor integrated circuit, detecting that the output terminal is short-circuited to the one power supply at the opposite level;
Based on this detection output, a detection protection circuit is provided to turn off the N08) transistor that is in the ON state among the two MOS transistors. If there is a short circuit to the L level or H level power supply side, which are opposite levels, this will be detected immediately and the MOS transistor that is in the on state will be turned on.
The output is set in a floating state to prevent a large current from constantly flowing through the MO8) transistor.
This prevents destruction of the transistor and improves reliability.

[Example 1] FIG. 2 shows an example of the present invention, and in particular, the present invention is applied to a MOS
A case where it is applied to a memory IC is shown.

In this figure, the same reference numerals (1) are used for the same parts or parts having the same functions as in FIG. 1.

In the same figure, 6 detects that the output terminal 5 is shorted to the ground side at the opposite level when reading "1",
This detection protection circuit 6 turns off the MOS transistor T3 which is in the on state based on this detection output and sets the output to a floating state.
It is composed of S transistors T, -T,2. The MOS transistors T, , T, are of n-channel enhancement type, and their threshold voltages vth5, Vt
ha is the same, for example 10, IV. Furthermore, MOS)
Transistor T5 is for backflow prevention. Also MOS transistor T? , TOTll-TO2 is an n-channel enhancement type, and its threshold value 1iE pressure Vth? .

■th0. ■th1□ and vth12 are 10, 3V if they are the same. Also MOS) transistor 'r6. '
rh.

is of n-channel depression type. Also MOS
) Transistors T9 and TIo constitute an inverter.

The gate electrode of the MOS) transistor T3 is connected to the common connection point of the gate electrode and the drain electrode of the MOS transistor T.

The source electrode of MOS) is the common connection point of the source electrode and gate electrode of transistor T6 and klO3) of transistor T
It is connected to the gate electrode of No.7. Also, the drain of MOS transistor T! Th is power supply +■cc(+5■)K
It is connected. The source electrode of the MOS transistor T7 is connected to the output terminal 5, and the drain electrode is connected to the M
OS) Source electrode of transistor T8 and MOS) transistor T.

is connected to the gate electrode of Note that the gate and drain electrodes of the λ40S transistor T are commonly connected to the power supply +
Connected to Vcc (+5V). Further, the source electrode of the MOS transistor T is grounded, and the drain electrode of the MOS transistor T is grounded.

common connection point of the gate and source electrodes of transistor Tll, gate of transistor Tll) [pole and MOS) transistor TI2
are connected to the drain electrodes of the two electrodes, respectively.

MOS transistor T. The drain electrode of is the power supply element VC
Connected to C. Also, the drain electrode of the MOS transistor TI is the MOS transistor T.

Its gate is connected to the pole, and its source electrode is grounded. Further, the gate electrode of the MOS transistor T I2 is connected to the gate electrode of the MOS transistor T4, and the source electrode is grounded.

The operation of the main parts of the MOS type semiconductor integrated circuit configured as above will be explained below with reference to the table below.

When normal "0" is read from the table (when the output is at L level), the potential at point a is at L level and the potential at point b is at H level due to the output of output driver 3 based on the output of sense amplifier 2. Therefore, MOS) transistor T3. T4 is in an off state and an on state, respectively. Therefore, the output terminal 5 is at L level. At this time, since point a is at L level, T is cutoff, but point C is at H level due to the MOS transistor T, and point C is always at level 1. Point d is at L level when MOS transistor T7 is turned on, and point e is at L level when MOS transistor T2 is turned on.

Therefore, the MOS transistor 'I'11 is in an off state, and the detection protection circuit 6 does not perform any operation on the output cover 74.

Also, when normally reading "1" (when the output is at H level), the output of the output driver 3 based on the output of the sense amplifier 2 causes point a to go to H level and point b to L level, so λ4
The 0S transistor T3 is turned on, and the λ10S transistor 'r41'rtt is turned off. Therefore, the output terminal 5 becomes H level.

At this time, since the point a is at H level, the MOS transistor T is turned on. Point 0 is at H level and the MOS transistor T is in an on state, but since the output terminal 5 is at H level, point d is at H level. and MOS transistor T
, is turned on, and point e remains at L level. Therefore M.O.
S) Since the transistor T11 is in the off state, the detection protection circuit 6 has no effect on the operation of the output cover and the filter 4, as in the case of reading "0".

However, when the user (customer) accidentally reads the output terminal -f5 as "]" due to carelessness or the like (when the output is at H level), the K
As explained in Fig. 1, if a short circuit occurs with the ground side (L level side) at the opposite level, the detection protection circuit
The operations shown in the table are performed. That is, M
Since the OS transistor T is on, the point d changes from the H level to the L level, the MOS transistor T turns off, and the point e changes from the L level to the H level. And M.O.S.
Transistor T7. turns on, point a changes from H level to L level, and MOS transistor T.

turns on. And as shown in Figure 1, the large current ■ is MO
S) prevents the flow to the transistor T.

Therefore, the output terminal 5, which has become L level due to the short circuit, is 70-
It will be in a ting state. Since such an operation of the detection protection circuit 6 is performed immediately, the output stage MOS transistor T is used as described in FIG.

It is possible to prevent the MOS transistor T3 from being destroyed due to the constant flow of a large current through the transistor T3, thereby improving the reliability of the circuit. The user can use it with peace of mind.

In addition, as shown in Fig. 1, in order to prevent the MOS transistor T3, which is in the on state when it is short-circuited to the ground side of the opposite level during 1'' reading, from being destroyed by a large current, as shown in the present application. Mo without providing the detection protection circuit 6
It is conceivable to increase the capacitance of the s-transistor T3, but if the capacitance of the MOS transistor T3 is increased, the capacitances of other elements must be similarly increased, resulting in a larger chip. On the other hand, in the present invention, the second embodiment
As shown in the figure, if the detection protection circuit 6 is added to the output buffer 4 without increasing the element capacitance of the output buffer 4 shown in FIG. 1, the chip does not have to be large, and the cost can be reduced.

[Embodiment 2] FIG. 3 shows another embodiment of the present invention, in particular when the present invention is applied to MO
This shows the case where it is applied to S Memo IJIC. In the same figure, the same reference numerals are used for the same elements or those having the same functions as in FIG. 1 (σ).

In the same figure, 7 is a power supply terminal VCC whose output terminal 5 is at the opposite level when reading 0"' (output L level).
A detection protection circuit that detects a short circuit with the circuit and turns off the λ40S transistor T4 that is in the on state based on this detection output and puts the output in the 70-ting state,
This detection protection circuit 7 is made up of MOS) transistors T13 to TI.
It consists of 8. and MOS transistor TI
3-T8. .

T+, +Tap H channel enhancement type MOS transistor T, 3. T, , T,,
, T, 8 threshold voltage V1h1a I Vtho
; I Vthx71 Vt)IH+• are the same, for example +0, 3■, and the threshold voltage Vtht4 of the MOS) transistor TI4 is, for example, 10'1■. Mo
The s transistor TI6 is of an n-channel depletion type, and the MOS transistors 5 and 16 constitute an inverter.

Here, the gate electrode of the λ(O5) transistor T3 is connected to the output terminal 5, and the source electrode of the MOS
) is connected to the gate electrode of transistor T. Further, the drain electrode of the MOS transistor TI3 is connected to the source electrode of the MOS transistor TI4 and the MOS transistor T1. is connected to the gate electrode of MOS) The gate electrode and drain electrode of transistor T,4 are connected,
A power supply +Voo (+5V) is connected to the common connection. Also MOS) transistor T8. The source of the transistor T, whose core is grounded and whose drain electrode is a MOS transistor, the connection point between the gate electrode and the source electrode of the transistor T, and the MO
They are connected to the gate electrodes of the S transistors T, , , T, , respectively. Note that the drain electrode of the MOS transistor TI6 is connected to the power supply Vcc (+5V) Km. Also, MOS) transistor T1. The drain of the MOS transistor T4 is connected to the gate electrode of the transistor T4, and the source electrode of the transistor T4 is grounded. Further, the drain electrodes of the MOS transistors T and 8 are connected to the gate electrode of the MOS transistor T, and the source electrodes are grounded.

The main moving parts of the MOS type semiconductor integrated circuit configured as described above will be briefly explained below.

When normally reading "1" (when the output is at H level), the output of the output driver 3 based on the output of the sense amplifier 2 causes point a to go to H level and point b to L level, so the MOS
Transistors T, , T4 are turned on and off, respectively. Therefore, since the output terminal 5 is at H level and the point f is also at H level, the MOS transistor TI3 is turned on, and the point g is at H level. and MOS transistor T
11 is turned on, and point h becomes L level. For this reason, MOS) transistor Tl? s T18 is in the off state. Therefore, the detection protection circuit 7 has no influence on the operation of the output buffer 4.

Also, during normal “0” reading (at output level),
The output of the output driver 3 based on the output of the sense amplifier 2 causes the point a to be at L level and the point b to be at H level.
MOS) transistor T8. T4 is turned off and turned on, respectively. Therefore, the output terminal 5 goes to L level, and the point f also goes to L level, so the MOS transistor TIB turns off, and the point g goes to H level by the MOS transistor T14. Then, the MOS transistor TI5 turns on, and the point h becomes L level. Therefore, MOS) transistor Tl? * TLM is in the off state, and the detection protection circuit 7 outputs the output buffer 4 as in the case of reading “】” mentioned above.
has no effect on the operation.

However, if the user (customer) accidentally shorts the output terminal 5 with the power supply terminal Voo (H level) at the opposite level as explained in Figure 1 due to carelessness when reading "O", , the detection protection circuit 7 operates immediately,
The MOS transistor T4, which is in the on state, is turned off. That is, when the output terminal 5 becomes H level due to a short circuit when reading "O", point f changes from L level to H level, MOS transistor T13 turns on, point g changes from H level to L level, and the MOS transistor T13 turns on. Tl11 is turned off. Therefore, point h changes from L level to H level and the MOS transistor Tl? *'ra
g changes from off to on state at point b.

Point i becomes L level. For this reason, MOS) transistor T
Since output terminal 4 is turned off, output terminal 5 is connected to the H level side power supply +V.
By shorting to CC, it is possible to immediately prevent a large current (several tens of mA) from flowing steadily through the MOS transistor T4.

Then, due to a short circuit, the output terminal which became I (level) was set to 70-
It will be in a tinging state. Since such an operation of the detection protection circuit 7 is performed immediately, it is possible to prevent the MOS transistor T4 in the output stage from being destroyed due to the constant flow of a large current, as in the conventional case, and the reliability of the circuit is improved. can improve sex. And the user can use it with peace of mind.

In this case as well, adding the detection protection circuit 7 as described in the first embodiment allows the chip to be smaller and costs to be lower than increasing the element capacitance of the conventional output buffer 4.

[Embodiment 3] FIG. 4 shows another embodiment of the present invention, in particular when the present invention is applied to MO
The case is shown when applied to an S memory IC. In this figure, the same reference numerals are used for the same parts or parts having the same functions as in FIGS. 1 to 3.

In the same figure, 8 is a detection protection circuit, and this detection protection circuit 8 has an output terminal 5 connected to the ground side (L
A combination of the detection protection circuit 6 shown in Fig. 2 in the case of a short circuit with the power supply +Vcc (H level side) and the detection protection circuit 7 shown in Fig. 3 in the case of a short circuit between the output terminal 5 and the power supply +Vcc (H level) side when reading "0". It is composed of Therefore, even if the output terminal 5 is short-circuited to the ground side or the power supply +Vcc side of the opposite level when reading "1" or "0", this detection protection circuit 8 immediately detects this.
Based on this detection output, the MOS transistor T3 or T4, which is in the on state, is turned off, and the output is made to be in a floating state. The configurations of the detection protection circuits 6 and 7 constituting the detection protection circuit 8 are as shown in FIGS. 2 and 3, respectively.

In the circuit shown in FIG. 4 configured in this manner, during normal reading of "0" or "1", the detection protection circuit 8, that is, the detection protection circuits 6 and 7, is controlled by the operation of the output cover sofa 4 as described above. It has no effect on

However, as described above, if the user accidentally shorts the output terminal (output bin) 5 to the ground side when reading "1", the detection protection circuit 8, that is, the detection protection circuit 6 is activated, and the first embodiment As already explained <MOS) transistor T3
The large current caused by the short circuit turns off the MOS) transistor T.

can be prevented from being destroyed.

Further, even if the user accidentally shorts the output terminal 5 to the power supply terminal VCC (H level) at the time of "0" reading 1, the detection protection circuit 8, that is, the detection protection circuit 7 operates, and the second embodiment As already explained in Section 1, the MOS transistor T4 is turned off and a large current is generated due to a short circuit.
4 can be prevented from being destroyed by 1.

In addition, the reliability of the circuit can be further improved, and the user can use the circuit with greater peace of mind.

Note that in order to solve the problem of the circuit shown in FIG. It can be done at a low cost.

〔effect〕

If the output terminal is at H level or L level and the output terminal is short-circuited to the L level side or H level side power supply respectively due to misuse, the detection protection circuit will immediately detect this and the output MOS in stage on state
) The transistor is turned off and the output is placed in the 70-state, thereby preventing a large current from constantly flowing through the MO8) transistor, preventing the MO8 transistor from being destroyed, and thus improving reliability. The invention achieved by the present inventor has been specifically explained based on the examples above, but the present invention It goes without saying that the present invention is not limited to the above embodiments, and that various changes can be made without departing from the spirit thereof.

For example, according to the present invention, two
In the embodiment, the two MOS transistors T1. Although it has an N-channel configuration like T4, it may have a P-channel configuration or a C-MOS configuration. In this case, it goes without saying that the constituent elements of the detection protection circuits 6 to 8 and the channel configurations of the circuit elements in the preceding and subsequent stages may be changed as necessary.

[Application field]

The above explanation will mainly focus on non-volatile memory ICs, which is the field of application for which the invention was made by the present inventor.
Although the case where it is applied to the output buffer of MOS memory IC such as
For example, it can be applied to general MOS semiconductor integrated circuits, such as output buffers for general MOS semiconductor integrated circuits.

[Brief explanation of drawings]

Figure 1 shows the J O
FIG. 2 is a circuit diagram showing an example of an output buffer of an S memory IC. 2 to 4 are circuit diagrams showing each embodiment of the present invention. 4...Output buffer, 5...Output terminal, 6-8...
・Detection protection circuit, T, ~Tts...MOS) transistor, +Vcc...Power supply ・

Claims (1)

[Claims] 1. The output electrode side has two MOS transistors connected in series, and the series body of the MOS transistors is connected between two different power supplies, and each input of the two MOS transistors is connected in series. A control signal is supplied to the electrodes so that one turns on and the other turns off, and in an MO8 type semiconductor integrated circuit in which the output terminal is taken out from the connection point on the output electrode side of the two MOS transistors, the output terminal is opposite The present invention is characterized by comprising a detection membrane circuit that detects a short circuit to one of the power supplies that is at a high level, and turns off the one of the two MOS transistors that is in an on state based on this detection output. MO8 type semiconductor integrated circuit. 2. The MO8 type semiconductor integrated circuit according to claim 1, which is applied when the output terminal is short-circuited to the ground side, which is one of the power supplies. 3. The MO8 type semiconductor integrated circuit according to claim 1, which is applied when the output terminal is short-circuited to the ground side of one of the power sources and the other power source side forming a pair. .