JPS6020159A - Fault detecting system of multiplexer - Google Patents

Abstract

PURPOSE:To detect an instantaneous fault of a multiplexer by providing an idle time when switching an input signal of the multiplexer, and detecting at every idle time whether an output signal voltage is within a prescribed range or not. CONSTITUTION:When a scanning signal is inputted to a multiplexer 21, a switch 211 is turned off, and after an idle time T has elapsed, a switch 212 is turned on, and an input signal AI-2 is inputted to an amplifier 22. In this case, if an internal switch 212 becomes faulty and an on-state is continued, when a switch 27 is turned on by a check signal at an idle time, the signal AI-2 flows to an earth through a resistance 26 and the switch 27. As a result, a voltage generated in the resistance 26 is amplified by the amplifier 22, becomes higher than a constant-voltage E, and an output of a comparator 24 becomes ''1''. Subsequently, its output and the check signal is brought to AND by an AND gate 28, and an error signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a failure detection method for a multiplexer that switches input signals.

[Background of the invention]

A plurality of signal lines are usually connected to an input device of a computer system, and input signals are input to a processing device by switching the signal lines using a multiplexer or the like. Figure 1 shows an example of a process computer system. Input device 2 that inputs a plurality of analog signals from the process 60 via the signal line 70
0 has a multiplexer that switches the analog signals and sequentially captures them one by one, converts the captured signals into digital signals, and outputs the digital signals to the processing device 10 via the signal line 80 and the system bus 50. The processing device 10 receives signals from the input device 20 via the system bus 50,
A digital signal is output to the output device 40. Output device 4
0 converts the digital signal from the signal line 90 into an analog signal and outputs it to the process 60 via the signal line 100.

Here, one of the conventional failure detection methods for a multiplexer that switches analog signals and sequentially takes in them will be explained with reference to FIG. In FIG. 2, reference numeral 21 is a multiplexer that sequentially turns on internal switches 211 to 21n one by one in response to a scanning signal and switches a plurality of input signals one by one; 35 is a multiplexer 210 with one input terminal (internal switch 2
11), 22 is a preamplifier that amplifies the output of the multiplexer, and 23 is an analog/digital (hereinafter referred to as A/D) that converts the amplified signal into a digital signal.
24.25 is a comparator that detects whether the voltage obtained by amplifying the reference voltage of the reference power supply 35 is within a specified range (Va±E); 28 is a comparator 24.25; This is an AND gate that performs the logical product of the output of the output and the selection signal.

The operation will be explained below. Internal switch 2 depending on the scanning signal
11 is turned on and the reference voltage of the reference power source 35 is taken in, the comparators 24 and 25 detect whether the output voltage of the preamplifier 22 is correctly amplifying only the reference voltage.

Amplifier 2 when only internal switch 211 operates normally
When the output voltage of 2 is Vs, the comparator 24 sends out an output signal if the amplified voltage is larger than V s + E, and the comparator 25 sends out an output signal if the amplified voltage is larger than V s - E. The bias voltages V++ +E and Vs-E are set so that if the voltage is smaller, an output signal is sent out. AND
The selection signal, which is one input of the gate 28, is used when turning on the internal switch 211 of the multiplexer 21 (reference voltage 3
5) is sent.

Next, in response to the scanning signal, the internal switch 212 of the multiplexer 21 is turned on to take in the input signal Al-1. Then, the input signals are sequentially taken in as Al-1, Al-2, Al-3, . . . n. - When the input of the current υ is completed, the internal switch 211 is turned on again, and the reference voltage is input from the reference power source 35 and detected by the comparators 24 and 25. At this time,
If even one switch other than the switch 211 is turned on, the voltage input to the comparator 24.25 will fluctuate and fall outside the specified range (VS±E), so an error signal will be output. Ru.

This method detects a failure in an internal switch by checking the reference power supply once every - period when switching input signals.

That is, in the event of a failure in which one of the internal switches of the multiplexer 21 is permanently turned on, when the internal switch 211 is turned on (when the reference power is drawn in),
Either of the comparators 24, 25 will be at logic level "1". The AND gate 28 performs a logical product with the selection signal.
A final error signal is output and a fault is detected.

However, although the above method can detect a permanent failure of the switch inside the multiplexer 21,
An instantaneous failure in which the internal switch 212 is turned on only at a certain moment (for example, the internal switch 212 temporarily fails (ON), but when the scanning signal is turned on, the internal switches are sequentially switched, and when the internal switch is turned on and the reference voltage is taken in) 212 has already been turned off), it has the disadvantage that it cannot be detected.

[Purpose of the invention]

An object of the present invention is to provide a fault detection method that can detect even instantaneous faults in multiplexers as described above.

[Summary of the invention]

The present invention provides an idle time when switching input signals of a multiplexer, and focuses on the fact that no signal voltage is generated during this idle time, so that the output signal voltage of the multiplexer is within a specified range in each idle time. If it is out of a specified range, an error signal is sent to the processing device to detect a multiplexer failure.

In other words, the switching of the internal switch of the multiplexer is
In order to prevent multiple selections, the current internal switch is first turned off by the scanning signal, an idle time (hereinafter referred to as idle time) is provided, and the next internal switch is turned on by the scanning signal. During this idle time, if the multiplexer is normal, no internal switches are turned on, and therefore no signal voltage should be generated at the output of the multiplexer. Therefore, if any signal voltage is generated during the idle time, it can be determined that the multiplexer has failed.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG.

In FIG. 3, multiplexer 21, amplifier 22, A
/D converter 23, comparators 24, 25, AND gate 28
is the same as in FIG. However, in the conventional method, the voltages applied to the inverting input of the comparator 24 and the non-inverting input of the comparator 25 are set within a specified range (VS±E) centered on the voltage (■8) amplified from the reference voltage. In contrast, the present invention
It is set within a specified range (±E) centered on the ground potential. Furthermore, the difference from FIG. 2 is that the output of the multiplexer 21 is grounded via a series circuit consisting of a resistor 26 and a switch 27. Further, in order to open and close the switch 27, a check signal is sent out in place of the selection signal, and this check signal is sent out every idle time. Then, this check signal and the signal obtained by wire-ORing the outputs of the comparators 24 and 25 are input to the AND gate 28, and the logical product is taken and an error signal is output. .

Here, the input impedance of the amplifier 22 is so high that it can be ignored in terms of the accuracy of the data taken in as a ratio to the signal source impedance.

Also, the series circuit consisting of resistor 26 and switch 27 was inserted because the internal switch of the multiplexer was OF'l;
J. Even during idle time, some residual voltage remains at the output of the multiplexer due to the capacitance of the lead-in line from the signal source, and the input of the amplifier 220 does not become an oven, so this is to reduce the voltage. . In other words, if some voltage is generated at the output of the multiplexer 21 during the idle time and that voltage is amplified by the amplifier 22, the comparators 24 and 25 will detect a range centered on the ground potential, so it will not be in a normal state. However, this is because there is a risk that it will be judged as a malfunction.

Here, the operation will be explained using the time chart shown in FIG. First, a scanning signal is input to the multiplexer 21, the internal switch 211 is turned on, and the input signal Al-
1 is input to amplifier 22. Next, turn switch 211 to
FF, then turn on the switch 212 after the idle time T has elapsed.
L, T, Al-2 is input. Suppose that the internal switch 212 fails and remains in the ON state. The check signal is sent every idle time (CHl, CH2, CH3).

) is output and the switch 27 is turned on.

In this case, since the internal switch 212 has failed and remains in the ON state, Al-2 is connected to the resistor 26 and switch 2.
7 to ground. Therefore, a voltage is generated in the resistor 26, and this voltage is amplified by the amplifier 22, and the constant voltage E
The output of the comparator 24 becomes '1'.The output and the check signal CH2 are ANDed by the AND gate 28, and an error signal Ep is generated.

Once the failure of the internal switch 212 is recovered, the error signal will not be generated during the next idle time, and it will be unclear which contact has caused the error. The contents of the scanning signals may be stored and retrieved as needed.

FIG. 5 is a block diagram in which the embodiment of the present invention shown in FIG. 3 is applied to a computer system including the input device 20.

Multiplexer 21, amplifier 22, A/]) converter 23
, comparators 24, 25, resistor 26, switch 27, AND
Game 128 is similar to that in FIG.

51 is a data bus, 52 is a control paste, which is included in the system bus 50 and connected to R10 (not shown, see FIG. 1) after processing. , 30.degree. 34 is an AND gate, 31 is a flip-flop, and 32.33 is a register. Note that single-line arrows represent the flow of control signals, and double-line arrows represent the flow of address and data signals.

First, the processing device 10 causes the register 33 to input an address signal to the D terminal via the data bus 51 and an address latch signal to the T terminal via the control bus 52. Then, the address is latched in the register 33, and the output of the register 33 operates the multiplexer 21 as a scanning signal and is input to the D terminal of the register 32. Then, the multiplexer 21 selects one of the input signals Al-1 to Al-n, its output is amplified by the amplifier 22, and the output signal is sent to the A/D converter 23.
convert it into a digital signal.

The digital signal is logically ANDed with the data acquisition signal from the control bus 52 by the AND gate 30, and is input to the processing device 10 via the address bus 51. This is the normal data flow.

Next, the flow of failure detection data using check signals is shown below.

The processing device 10 controls the control bus 5 during idle time.
2, outputs the check signal CH through switch 2
Turn ON 7 to perform failure detection.

If this happens, the internal contacts 211 to 2 of the multiplexer 21
If any one of 1n fails and is short-circuited, the 3rd
As explained in the figure, since the AND gate 28 generates the Scherrer signal, the flip-flop 31 is set. The output of the flip-flop 31 is then output as an error signal to the processing device 10 via the control bus 52, allowing the processing device 10 to know that a failure has occurred.

When the flip-flop 31 is set, a pulse is input to the T terminal of the register 32, and the address at that time is stored in the register 32. When flip-flop 31 is set, the contents of register 32 are not updated. Therefore, if the processing unit 10 outputs a sear address capture signal as necessary, the contents of this register 32 can be changed to
The data is taken into the processing device 10 via the D gate 34 and the data bus 51, and the failed address can be known at any time. When a faulty address is taken in, an error reset signal is output, and the error 7 lip-flop 31 is reset to prepare for the next error detection and address storage.

According to this embodiment, the failed address is stored in the register 32 even in the case of an instantaneous failure in which a certain switch temporarily fails and recovers during a cycle, rather than a permanent failure. Therefore, it has the effect of being able to detect failures.

Another embodiment of the present invention will be described using FIG. 6.

The difference between FIG. 5 and FIG. 3 is that the series circuit of resistor 26 and switch 27 is removed. However, in this example,
It is applicable only to amplifiers 22' whose input impedance 29 is low relative to the input signal source impedance.

In the case of this embodiment, when all the internal switches of the multiplexer 21 are OFF during the idle time, the multiplexer 2
Even if some residual voltage remains in the output of 1, the input impedance 29 is low, so the residual voltage is reduced and the influence of the residual voltage can be eliminated. When any one internal switch is still in the ON state, the voltage appearing by the voltage division ratio of the signal source impedance of the input signal and the input impedance 29 of the amplifier 22' is amplified.

The subsequent operation is similar to that shown in FIG. 3, in which the output from the amplifier 22' is detected by the comparators 24 and 25, and the AND is performed with the check signal to detect a failure based on the presence or absence of an error signal. The error signal can be processed in the same manner as in FIG.

Another embodiment of the present invention will be described using FIG. 7.

This embodiment uses a capacitor storage transmission type multiplexer 21'. This multiplexer 21'
The input side and the output side, that is, the signal source side and the amplifier side are isolated. That is, this multiplexer 2
1' is an internal switch 221 to 22n having two contacts.
It is designed so that it can be switched to both the signal source side and the amplifier side), and is normally switched to the signal source side. At that time,
The signal voltage is charged to the capacitor. (Taking AI-1 as an example, resistor 230, capacitor 231, resistor 23
A current flows through path No. 2, and the capacitor 231 is charged. ) Here, when a scanning signal is input, one of the internal switches 221 to 22n is sequentially switched to the amplifier side depending on the content of the scanning signal. At this time, the voltage charged in the capacitor is amplified by the amplifier 22.

In such a multiplexer 21', failure detection when a failure occurs in the internal switches 221 to 22n is performed as follows.

For example, if the internal switch 221 fails and the switch 27 continues to be switched to the amplifier side even during the idle time and the check signal turns on the switch 27, a voltage will be generated in the resistor 36, so the AND An error signal is output from the gate 28.

Claims (1)

[Claims] 1. In a failure detection method for a multiplexer that switches multiple input signals, a free time is provided when switching input signals, and for each free time it is detected whether the output signal voltage of the multiplexer is within a specified range. A fault detection method for a multiplexer characterized by detecting faults.