CA1052903A - Time-base error correction system - Google Patents

Abstract

ABSTRACT OF THE DISCLOSURE
A time-base error correction system for a video signal employing a plurality of serially connected delay lines. Circuit means are conditio ed to detect the closest timing match between a reference synchronizing signal and the video signal as it appears at various points along the delay path and to connect the appropriate delay line point or junction to an output at which the correctly delayed video signal appears. Featured circuitry provides for eliminating the erroneous leading edge of a video synch-ronizing pulse distorted by changes in the selected delay point and for compensating for variations in d.c. offset of the video signal introduced by differential delay line path effects.

Description

lOSZ9~3 The present invention generally relates to variable delay circuitry and more particularly to a system for correcting time-base errors in a periodic or repetitive signal such as a video signal.
In many electrical systems it is desirable or necessary to change the time base of a signal such that it coincides with that of a reference waveform. For example, in the art of magnetic tape recording of video signals, it is necessary to correct timing errors during playback such that reproduced video is synchronized with a standard reference signal. In order to provide this processing of the reproduced video waveform, a number of time-base error correction systems have been developed, all of which .-include some form of variable delay circuitry with the lS amount of instantaneous delay being responsive to a measured time-base error. One type of correction system makes use of a plurality of fixed delay lines functioning in combination with the switching circuitry such that the video sigr.al may be fed through different delay paths in accordance with the condition of the switching circuitry.
Another scheme requires the use of a voltage variable delay line employing lumped constant inductors and voltage variable capacitors connected as a delay line network.
Examples of these systems are found in U.S. Patent No.
3,384,707 and U.S. Patent No. 3,202,769.
The present invention employing both types of time-base error correction schemes, is primarily directed ~o an improvement of the switched delay line class of devices. In particular it is an object of the present invention to provide more efficient delay network for use in a video time-base error correction system where .

lOS;~903 efficiency is measured in terms of cost versus delay correction capacity or range. In other words, the system of the present invention has the objective of providing a variable delay range useful for most video recording systems àt a lower cost than for other time-base error correctors having an equivalent capacity, reliability and accuracy.
The present invention includes a variable delay system employing a plurality of serially connected fixed delay lines as known per se in combination with a signal detection and switching circuit arrangement operating to compare the video synchronizing waveform (video sync) as it appears at the input, output, and interconnecting junctions of the delay lines with a standard or reference synchronizing `~ -~
signal and to select the delay point at which video sync first occurs following reference sync for connection to a video signal output.
Further, in accordance with a specific embodiment of the present invention a stretched sync inhibit circuit is provided for cancelling the erroneous leading edge of video signal synchronizing waveform which has been unavoidably stretched by a switched increase in the amount of signal delay through which the video is passed. This feature of the invention eliminates among other things the requirement of a delay circuit up~tream of the switched serially connected delay lines which has been found necessary in other systems.
Delay lines or delay circuits in advance of the switched variable delay path are undesirable because of the increased cost and complexity.
Further in accordance with a specific embodiment of the present invention, circuitry is provided for arbitrarily selecting one of the delay points in the serial path for con-nection to the video output in the event the video signal is outside the delay range capacity of the system. This avoids jvb/bk ;7 - ,. . ~. .

105'~903 the consequence of none of thc dclay points being selected pursuant to comparison betwecn thc video synchronizing waveform and the reference signal.

A full disclosure of the prcsent invention and the presently preferred embodimcnt thereof is provided below in con~unction with the drawin~s in which:
FIGURE 1 is a block diagram illustrating generally a time-base error correction system;
~'IGURE 2 is a comprehensive block diagram of the time-base error correction system constructed in accordance with the present invention;
FIGURE 3 is a block diagram illustrating a clamping circuit constructed in accordance with the present invention and employed in the system of Figure 2;
and FIGURE 4 is a detailed schematic diagram of the clamping circuit of Figure 3.
~he environment in which the present invention functions is illustrated generally by Figure 1, in which a time-base error corrector is adapted to receive a video signal from a video tape recorder ~VTR) and to detect any timing errors in this signal relative to a reference timing waveform. The video is selectively delayed in response to measured time-base error and issued as a corrected signal at the output. Figure 2 illustrates a time-base error correction system constructed in accordance with the prescnt invention in which a plurality of fixed delay lines and equalizer 11 are connected in a serial signal path with an input linc 1~ thcrcto ada~ted to receive a vldeo signal from the VT~. ~8 the vldeo signal passes through this series o lines lt is di~f~rentially delaycd at th~
variou.~ tap~ or ~unctions n~goaiated with tlle lines and one ,~, .

~05Z903 5 of these taps is selected by detection circuitry for connection to an output. The detection circuitry, including a set of sync pulse detectors 13, sequence detection circuits 14, and a permit selection pulse generator 16, serves to sense the line tap at which a leading edge of the video synchronizing waveform, in this instance of a horizontal line, first occurs in time following the corresponding leading edge of a horizontal reference timing waveform. In response to this detection, switching circuitry in the form of video switches 17 and switch control circuits 18, connect the selected delay line tap to an output line 19 for passage to a connected video output 21.
As an example of this operation, assume that :
the video s~nchronizing waveform is just leaving the first delay lines 11 and at this time a leading edge of horizontal reference is applied to permit selection pulse generator 16. Generator 16 in turn issues a signal to one o~ the inputs of each of sequence detection circuits 14 :-- ?
as more fully described herein enabling these circuits to respond to their remaining input from their associated - sync pulse detector 13 via AND gates 23. Shortly there-after a tap 22 between the first and second delay lines receives the leading edge of the video sync and causes ~ -the associated sync pulse detector 13 to apply~switching signal to the associated circuit 14 which in turn operates switch control 18 and the associated video switch 17. The video signal connected from tap 22 to line 19 passes through a series of output correction and processing stages to video output 21.
An important aspect of the present invention is that the detection circuitry does not merely sense 105'~903.
coincidence of reference and video sync. It is unlikely that precise coincidence will occur each time between the leading edge of the reference waveform and leading edge of the video synchronizing signal at one of the delay line taps. Thus the present invention functions to detect the first leading edge of video sync to occur after the corresponding leading edge of the horizontal reference timing signal. Nor does the invention operate in response to mere concurrence or coincidence of both video sync and reference sync tips (these signals having finite widths are referred to as sync tips), as this would not satisfy the "after" requirement, namely, first video leading edge "after" reference leading edge. In order to provide this "first"and "after" function, each of sequence detection circuits 14 include a gate 20 which is a.c. coupled to an ~-S flip-flop 24.
During operation, permit selection pulse generator 16 issues a signal over line 26 in response to the leading edge of the horizontal reference waveform. The signal issued over line 26 enables gate 20, via a J input of circuit 14, to respond through AND gate 23 to the sync pulse detector 13 associated with tap 22. When the leading edge of video sync appears at tap 22, AND gate 23 responds by issuing an output signal to the J' input of circuit 14.
Previously to this~gate 20 has been conditioned by the permit selection pulse generator to enable the J' input to respond to the output of AND gate 23 and thereby dispose flip-flop 24 in its set condition. The output of gate 20 is a.c.
coupled to the set input (S) of flip-flop 24 while the K input of circuit 14 is a.c. coupled to the reset (R) input such that these inputs are responsive to certain polarities of signal transitions.

- lOSZ903 These conditions enable flip-flop 24 to be disposed in its set condition only if line 26 has been first activated by a permit selection pulse and thereafter an output i~
received from AND gate 23.
In its set condition, the Q output of flip-flop 24 is high and in this state it activates the associated switch control 18 via a data input, ~ to assume its set condition and the Q output of the control 18 thereby closes video switch 17 over a line 27. Flip-flops 24 are returned to their reset condition by the trailing edge of the permit selection pulse on line 26. The K
input to each of circuits 14 is a.c. coupled to flip-flop 24 and is responsive only to a particular polarity of logic transition, in this instance the polarity transition associated with the trailing edge of the selection pulse on line 26. The foregoing logic restricts the functioning of sequence detection circuits 14 to select ~:
only that delay line tap at which the first video sync:
following reference sync occur~.
Once this selection of a tap is performed, the Q output of one of flip-flops 24 will, in addition to operating the associated switch control 18, activate an inhibit select pulse generator 28 through an OR gate 29.
Each of the inputs to gate 29 is connected to the Q
output of a separate one of flip-flops 24 as shown. Pulse generator 28 issues, over line 31, a signal to one of the inputs of each of AND gates 23 disabling such ~ :
gates from responding to subsequent ~ync pulse detector ~ignals. Thus, a selection once made disable~ the further operation of the remaining switch controls 18.
Furthermore, inhibit pulse generator 28 has . . ;.
: . , lOSZ903 its output line 31 connected to the clock input8, ~ Of each of switch controls 18 so as to dispose such controls in a condition dictated by the instantaneous logic level at the data input,~. In this instance the data input iS activated by the Q output of an associated flip-flop 24. Accordingly, a switch control 18 which has been disposed in its set condition during the previous measurement of a video line interval is reset by the occurrence of an inhibit pulse on line 31, as the data input ~, at that time is in its low condition, ~assuming that the same delay tap has not been selected). Conversely, the selected switch control 18 receives a high logic signal at the ~ input which is immediately followed by a signal at the ~ input from generator 28 causing the control to assume its set switching condition. The associated video switch 17 operates in response thereto.
It will be observed that the operating conditions of the disclosed network introduce a time shift distortion or error into the leading edge of the video synchronizing waveform as it appears on output line 19. In particular, if the detection circuitry operates to select a tap including a greater delay than the previously selected tap~
the leading edge of the video sync waveform will coincide with that of the video signal as it appears at the Up-stream tap. In other words, the video sync waveform is improperly stretched. The present invention as an important feature of its construction and operation provides a stretch sync inhibit circuit 32 which serves to cancel thiS erroneous leading edge of the output sync waveform.
In particular, thiS iS achieved by passing the video on output line 19 through a video gate 33 Of inhibit 105'~903 circuit 32 and operating gate 33 in accordance with the sequence of signals appearing at input line 12 to the delay line path~ and output line 3i from inhibit circuit pulse generator 28. A gate control circuit 34 has a set input responsive to the leading edge of video sync on input line 12 disposing the control circuit in its set condition which in turn operates gate 33 to "gate-off"
the video signal. Gate control 34 remains in its set condition until it receives a signal over line 31 indicating that a delay line tap has been selected, this being generall~ coincide:,tal with the occurrence of the leading edge of video at the selected tap. In response thereto gate 34 receives a reset signal through an OR gate associated with the reset input causing the gate control to assume its reset condition and gating the video "on"
again. This function of control 34 and gate 33 effectively cancels that portion of the video synchronizing waveform erroneously introduced by switching from one tap of delay , lines 11 to another down stream. To avoid the undesirable and possible consequence of gate control 34 failing to receive a reset signal from inhibit pulse generator 28, the reset input of control circuit 34 is alternatively - , responsive, through the OR gate to the video synchronizing waveform of the output tap of the last serial fixed delay ~ ~
line over line 36. This back-up signal serves as an ~ -inhibit release pulse to restore the video gate to its 'on~ condition allowing video to pas8 to output 21.
A still further aspect of the present invention is the provision of circuitry for arbitrarily selecting one of the delay taps for connection to output line 19 9 _ in the event the vldeo signal waveform is out of the delay connection range of the detection and switching circuitry.
Complete loss of video at output 21 is thereby avoided; it being preferable that some signal appears at the output even though it i9 incorrectly timed. For this purpose, an AND logic circuit 37 is provided including an AND gate 38 having inputs responsive to each of the Q outputs of separate switch controls 18. In the event all of switch controls 18 are disposed in their "off" condition, AND
gate 38 issues an output signal. Assuming this happens, the output from gate 38 is inverted and applied through an OR gate 39 to the output line 27 from one of switch controls 18 thereby operating the associated video switch - irrespective of the state of the switch control itself.
In this instance, AND logic circuit 37 is connected to the video switch associated with a central tap 41, located halfway between the input and output of the delay line series.
A soft clamp 46, i.e., ~ clamp circult having 20 a 610w time response, ad~acent the input of the tapped delay line sections, together with a hard clamp 47, i.e., fast-acting clamp circuit, ad~acent the video output. The use of soft clamps and hard clamps, Lndividually, in connection with video signal systems, is, of course, known ~ -per se. However, it has been found that the successful operation of the present invention, involving as it does the pasaage of the video signal through diverse delay line paths and through various switching devices, is due in part to the provision of both soft clamping at a point in the video path prior to the tapped delay lines and mb/ ~ - 10 -105;~903 hard or fast-acting d.c. restoration at the vldeo output.
Soft clamp 46 is of a conventional design, well known to those skilled in the art, and provides for slowly eliminating over a plurality of horizontal line period~
any d.c. offset errors in the video signal. That ig, as intended for the present invention, a slow clamp refers to one having a time constant greater than the one hori-zontal line period and typically requiring from 5 to 20 video lines before stabilizing at an average d.c. correction. .
This provides for eliminating average d.c. offset errors so that any d.c. crrors which are introduced in the signal by reason of passage through the delay lines and ~ , video switches lies within the correction range of hard clamp 47. After d.c. restoration by soft clamp 46, the `
video is fed through a sync regeneration network including :- . .
a sync height limiter circuit 51 for limiting the negative excursion of synchronizing waveform, a circuit 52 for removing sync from the video, an amplifier rise time ~-: : -generator 53 in series with circuit 52 for developing new leading edge for the synchronizing waveform, and a circuit 54 for adding the regenerated sync waveform to the sync height limited video signal received from circuit 51. - ;
.
After sync regeneration, the video is fed through the first stage of time-base correction provided by fixed delay lines ll. Following this corrective ~ -operation and after passage through the stretch sync inhibit circuit 32, video is passed through a second stage of tapped delay lines 56 which, in this instance, is essentially equivalent to the delay lines ll and associated switching circuitry described above.
11 .

105'~903 In the present embodiment, the first stage of tapped delay lines 11 provides a very coarse time-base error correction in that the values of fixed delay lines 11 are larger than each of the delay lines included in the second stage 56. By using a first set of relatively larger value delay lines followed by a second stage of relatively small value fixed lines, an efficient cost per delay unit of correction range is achieved.
Following the second stage of correction, hard clamp 47, as indicated above, functions to clamp or d.c.
restore each horizontal line period to a desired d.c. level.
As used herein, "hard clamp" refers to the ability of the clamping circuit to correct or restore each video period, in this instance a horizontal line, to a desired d.c. level.
This fast response clamping is performed during the video sync tip of each horizontal line. It is this combination of a soft clamp at the input to the switched video foll~wed by a hard clamp at the output which is believed to contribute substantially to the successful operation of this invention.
In the present invention, a particularly constructed and operated hard clamp circuit 47 is employed. Conventional hard clamp circuits have been found disadvantageous in the past due to their use of reactive capacitive components directly in the video signal path which introduce tilt in the video and fast-acting switching in shunt with the video signal path which introduce undesirable spike effects in the video signal disrupting the information carried thereby. In contrast, the hard clamp used in the present invention, as illustrated in greater detail in Figures 3 and 4, has the characteristic advantage of isolating the clamping circuitry from the video signal path. With reference to Figures 3 and 4, the video path 61 extending from the output of the second stage of tapped delay lines 56 to the input of the last stage of correction as shown in Figure 2 is provided with a clamping point or junction 62 connected to the clamping circuitry 63. As will be demonstrated in greater detail, the video signal path 61 does not pass through any - 10 reactive components nor are there any switching elements immediately in communication with junction 62. A further characteristic feature of this particular clamping circuit is its extremely fast response, functioning ; quickly enough to clamp each video line during the synchronizing tip of the horizontal blanking interval. ~
The circuit of Figures 3 and 4 operate in ` ; ~-the following manner. A comparator 64 responds at one -. :, . .
input to the video line voltage at junction 62 and at the other input to a clamp reference voltage. The output .
of comparator 64 assumes one or the other of two discrete values, lying at either a high or low logic state, depending on whether the video at junction 62 during the measurement mode is above or below the clamp reference.
A control logic circuit 65, enabled by a sync input signal which is derived from video sync by means of a sync stripper 50, responds to the output of comparator 64 and activates either a positive constant current source 66 or a negative constant current source 67, depending on the logic state at the output of the comparator.
A holding capacitor type storase means 68, together 7.
~...

. . .

~05A~903 with a buffer or operatlonal amplif~er 69, functlons to develop an increasing or decreasing voltage at ~unction 62 proportional to the charge on storage capacitor 68 thereby adding or subtracting an appropriate d.c. offset to the video signal level. A resister 71 serves to isolate the low impedance output of buffer 69 from ~unction 62. The input to comparator 64 i8 of high impedance and thu~, junction 62 is isolated at both ends of circuit 64 from the internal switching operations thereof by suitable impedance buffer or isolation means.
A~ an example of the sequence of operations, if the video sync tip at clamping ~unction 62 is below clamp reference, comparator 64 and control logic 65 operate to activate positive current source 66 which in turn pumps a steady stream of current into capacitor 68 rapidly increasing the voltage at ~unction 62. As the voltage at clamping ~unction 62 crosses the clamp reference level the logic condition of the comparator output changes state cauæing the control logic circuit 65 to disable or turn off positive current source 66 leaving ~unction 62 at the correct d.c. voltage. In general, the operation of the circuit in response to a video sync tip at ~unction 62 lying above clamp reference ig similar, with the following exception.
Control logic 65 functions to turn off both current sources only in response to the voltage at ~unction 62 crossing the clamp reference level in a particular direction. The -~-purpose and operation of this unidirectional response of control logic 65 will be discussed in further detail in connection with the schematic diagram of Figure 4. The entire searching sequence for the correct d.c. voltage occurs within the time width of the horizontal sync tip.
Once the mb/p`~ - 14 -105;~903 ~5_ correct offset is reached, it is held or stored on capacitor 68 for the duration of the succeeding video line.
It is observed that the construction and operation of hard clamp 47 of Figure 3 is based on a digital or discrete level logic in which the correctlon of the offset error i5 performed at discrete current and voltage levels except for the variable charge on capacitor 68. This principle of operation is believed to provide for the exceedingly reliable and fast-acting ;
functioning of the circuit. Furthermore, the use of logic control as opposed to analog control significantly reduces the manufacturing cost of the network.
With reference to FLgure 4, comparator 64 is, in this instance, formed by a ~TL (transistor-transistor ~ `
logic) logic device having an output 76 which is coupled to control logic 65 through an input converter stage 77 .
in this instance comprising a MECL (mo~orola cmitter coupled logic) converter serving to transform the TTL logic on line 76 to MECL logic upon which the control logic 65 is based. The output of the MECL converter 77 issues C~ ~\~ ~Q n ~ ~
separate signals of ¢ompllmcntary s'tates over lines 78 and 79 which are coupled as shown to a pair of AND gates 81 and 82 operating the positive and negative current sources 66 and 67. Another AND gate 83 has an input connected directly to output line 78 and a second input connected through a RC (resistive-capacitive) delay network to output line 79 which serves to disable AND gates 81 and - -- - - 82 through an RS flip-flop 84 thus turning off the current-sources in response to a particular transition of logic states of the output of comparator 64. In particular, and as ind$cated briefly above, control logic 65 operates to turn off the current sources only as the d. c.
voltage of clamping ~unction 62 crosses the desired lOSZ903 or clamp reference voltage from below to above (low to high). This functioning has the important advantage of always disposing the final voltage correction at junction 62 slightly above the reference level, rather than above or below depending on the polarity of the added d.c. correction and thus insuring a greater line-to-line accuracy in the clamping level.
Thus, assuming that the sync tip at junction 62 lies above reference, as sync input is received by ~6~b~ . -sy~c ~tr~'p~c r S~
}~qier{~ and converted to MECL logic by a converter 86, an output from AND gate 87 sets flip-flop 84 which in turn ena~les the pair of AND gates 81 and 82 from the Q output of the flip-flop. Depending upon the logic ~
condition of comparator 64 the output lines 78 and 79 will -enable one of AND gates 81 and 82 to turn on the appropriate one of current sources 66 and 67. Assuming that the video signal is initially above the clamp reference, ,-comparator 64 and control logic 65 function to turn on current source 67 driving the voltage at clamping junction 62 downward. The video voltage at junction 62 during sync ;
tip thus crosses tlle reference voltage in a high to low -direction causing comparator 64 to change state which in turn switches the logic condition of the complimentary output lines 78 and 79. After this switching AND gate 82 turns off negative current source 67 and AND gate 81 turns on positive current source 66. The voltage on holding comparator 68 respond.s by raising the voltage level at junction 62 unt~l clamp reference is again crossed, although in this instance from a low to hlgh direction. Output lines 78 and 79 again switch logic states and RC delay network 89 at one of the inputs ~05'~903 to AND gate 83 sustains the former voltage condition at such input and gate 83 thereupon responds to the changed voltage state at the other input issuing an output signal resetting flip-flop 84. Flip-flop 84 is thus restored to its original condition in wh~ch AND gates 81 and 82 are disabled by the Q output of the flip-flop device. The foregoing sequence of operations takes place entirely within the sync tip of a horizontal blanking waveform. The illustrated ~C network connected ' -~ ;
between converter 86 and AND gate 87 provides a selective ~ ;

response so that only the leading edge of video sync sets flip-flop 84.
Following the d.c. restoration by hard clamp 47, a vernier corrector 91 as shown in Figure 2 provides a final time-base error compensation. Preferably corrector 91 is a voltage variable delay line or lines responsive to horizontal reference and in color systems to the color subcarrier reference. Such a time-base error corrector ~-is disclosed in U.S. Patent 3,213,192. The final stage, circuit 92, provides for processing the video signal, eg.

regenerating or adding new sync signals, and is of a construction well known to those skilled in the art.

Claims (7)

WE CLAIM:

1. A system for correcting a timing error in a video signal including a periodic synchronizing waveform com-prising a plurality of serially connected delay lines for receiving and sequentially delaying a video signal, a detector circuit for detecting a certain time sequence between a reference timing signal transition and one of a plurality of sequentially delayed transitions of the synchronizing component of the video signal as they appear at the taps between the delay lines, and switch-ing means for connecting a selected one of said taps to a video output, said detector circuit being responsive to a reference timing signal transition and to the first occurrence at a tap of the sequentially delayed synchron-izing waveform transitions following that reference timing signal transition to operate the switching means to connect the tap at which the said first delayed transition occurred to the video output.

2. A system according to Claim 1 wherein the detection means comprises a separate electrical flip-flop means associated with each of said taps and each having an out-put connected to said switching means to connect the associated tap to said video output, a separate sync pulse detector connected to each tap for sensing the occurrence of said video signal waveform, a permit selec-tion pulse generator for receiving said reference signal and for generating a permit selection pulse in response thereto, gating means connecting each said sync pulse detector to an input of an associated flip-flop means for switching the state thereof, said gating means having a control input connected to said permit selection pulse generator for enabling said gating means in response thereto, whereby the input of said flip-flop means is responsive to an associated detection only when said gating means is enabled by a permit selection.

3. A system according to Claim 2, wherein said detec-tion means further comprises an inhibit select pulse gen-erator, an OR logic gate having a separate inputs indi-vidually connected to the outputs of said flip-flops and having an output connected to said inhibit pulse genera-tor, said gating means connected and responsive to an output of said inhibit circuit pulse generator for dis-abling the response of each of said flip-flops to said sync pulse detectors, whereby said inhibit pulse genera-tor is actuated once one of said flip-flops is switched and the inhibit pulse generated in response thereto operates said gating means to disable further response of the flip-flops to said sync pulse detectors.

4. A system according to Claim 1, the combination with said delay lines, detection means and switching means comprising video signal gating means interposed between said switching means and said video output, control cir-cuit means connected to an input to said delay lines and to said detection means and being responsive to a lead-ing edge of said synchronizing waveform at an input to said delay lines to dispose said video gating means in a gate-off condition and said control circuit means being responsive to detection of said first occurring synchron-izing waveform following the reference signal to dispose said video gating means in a gate-on condition, whereby a stretched leading edge of the synchronizing waveform is cancelled.

5. A system according to Claim 4, further comprising OR logic circuit means connected to said control circuit means having an input responsive to said detected first occurring synchronizing waveform following the reference signal and another input responsive to the synchronizing waveform appearing at an output tap of the last serially connected delay line such that said control circuit means operates to dispose said video gating means in its gate-on condition in response to either of the inputs to said OR logic means, whereby said gating means is released from its gate-off condition in the absence of said detection.

6. A system according to Claim 1 the combination with said delay lines, detection means and switching means comprising AND logic means connected to said switching means and being responsive to a condition in which none of said taps are selected for connection to said video output, circuit means connected and responsive to said logic means operating said switching means to connect a predetermined one of said taps to said video output.

7. A system according to Claim 6 in which said switch-ing means includes a separate switch control and switch for each delay line tap, and said AND logic means com-prising an AND gate having inputs connected to each of said separate switch controls and said circuit means having an output connected to and for operating one of said switches associated with one of switch controls.