JPS60198811A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60198811A
JPS60198811A JP5674984A JP5674984A JPS60198811A JP S60198811 A JPS60198811 A JP S60198811A JP 5674984 A JP5674984 A JP 5674984A JP 5674984 A JP5674984 A JP 5674984A JP S60198811 A JPS60198811 A JP S60198811A
Authority
JP
Japan
Prior art keywords
epitaxial layer
polishing
insulating film
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5674984A
Other languages
Japanese (ja)
Inventor
Hiromi Sakurai
桜井 弘美
Tatsuhiko Ikeda
龍彦 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5674984A priority Critical patent/JPS60198811A/en
Publication of JPS60198811A publication Critical patent/JPS60198811A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To separate elements of high accuracy and high quality by annealing an epitaxial layer formed in an insulating film hole, then polishing the surfaces of the epitaxial layer and the insulating film, thereby stabilizing the characteristic of an element formed on the layer and preventing the wirings from disconnecting. CONSTITUTION:An epitaxial layer 3 is formed in the hole of an SiO2 film 2 on an Si substrate 1, the entirety is heated and annealed at 1,200-1,300 deg.C for approx. 10-20sec to recover the crystallinity. Then, the surface is lightly polished. Since the frictional resistance abruptly increases if a projection is erased, the finishing point of the polishing can be simply observed, and can be mirror- polished with good reproducibility. The surface after polishing is completely flat, no disconnection of wiring occurs to stabilize the characteristic of an element formed on the layer 3, an element separating structure of high accuracy and high quality can be obtained merely adding simple step to the conventional steps.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関し、特に半導体装
置を平坦化かつ微細分離形成するための方法に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for planarizing and finely separating a semiconductor device.

〔従来技術〕[Prior art]

一般に、LSI等の素子間分離構造は従来より各種研究
され実用化されてきており、特に酸化膜分離法は結晶性
を損わず、分離容量や配線基板間容量が低減できること
から長年にわたり使用されてきた。そして最近では、さ
らに集積度を上げるために、バードヘッドやバードビー
クを低減するための分離方法が各種検討されている。中
でも選択エピタキシャル法は、酸化膜をシャープに切り
落とす技術の発展と平行して発展してきており、最も簡
単なプロセスで分離構造が得られるものである。
In general, various types of isolation structures between elements such as LSIs have been studied and put into practical use. In particular, oxide film isolation methods have been used for many years because they do not impair crystallinity and can reduce isolation capacitance and wiring board capacitance. It's here. Recently, in order to further increase the degree of integration, various separation methods have been studied to reduce bird's heads and bird's beaks. Among them, the selective epitaxial method has been developed in parallel with the development of technology for sharply cutting off oxide films, and is the method by which an isolated structure can be obtained with the simplest process.

ここで従来構造の一例として、選択エピタキシャル成長
法で分離構造を得た場合の利点と欠点について述べる。
Here, as an example of a conventional structure, the advantages and disadvantages of obtaining an isolated structure by selective epitaxial growth will be described.

第1図は従来の選択エピタキシャル成長法について工程
別に示したものである。まず同図(a)で示すように、
Si基板1上に形成されたSi酸化膜2を一部異方性エ
ソチング等によって開口し、前処理をほどこすとともに
自然成長酸化膜を除去した後、エピタキシャル成長装置
でSi H2Cj!2をH2中で分解することによりエ
ピタキシャル層3を成長させる。このとき同II (b
)で示すように、せ、Si酸化膜2の上には何も成長さ
せないようにすることができる。これは分解したSiが
エネルギの安定した所までマイグレーションを起こし、
移動することによって達成されるもので、Si酸化膜2
上よりもSi基板1上に核があるため、ここに成長する
ものである。
FIG. 1 shows each step of a conventional selective epitaxial growth method. First, as shown in figure (a),
A portion of the Si oxide film 2 formed on the Si substrate 1 is opened by anisotropic ethoching, etc., and after pretreatment and removal of the naturally grown oxide film, Si H2Cj! is grown using an epitaxial growth apparatus. Epitaxial layer 3 is grown by decomposing 2 in H2. At this time, the same II (b
), it is possible to prevent anything from growing on the Si oxide film 2. This is because the decomposed Si migrates to a point where the energy is stable.
This is achieved by moving the Si oxide film 2
Since the nucleus is located on the Si substrate 1 rather than above, it grows there.

しかしながら現実には、同図(C)に示すように、Si
酸化膜2上にもSi島4(バードヘッド)が成長したり
、連続したパターンのエツジに突起5(バードビーク)
が生じたりする。上記Si島4はSi酸化膜2上に前処
理では除けなかった核の種となるゴミ等があったときこ
こに成長するものと考えられており、また突起5はマイ
グレーションしてくるStが広いSl酸化膜2上から最
も近いSiに到達し、移動しな(なって成長してくるた
めに特にパターンエツジで発生しやすいものと考えられ
る。
However, in reality, as shown in the same figure (C), Si
Si islands 4 (bird heads) also grow on the oxide film 2, and protrusions 5 (bird beaks) grow on the edges of continuous patterns.
may occur. It is thought that the Si island 4 grows here when there is dust, etc. that becomes the seed of a nucleus on the Si oxide film 2 that was not removed by pretreatment, and the protrusion 5 has a wide St that migrates. It is thought that this phenomenon is particularly likely to occur at pattern edges because it reaches the nearest Si from the top of the Sl oxide film 2 and grows without moving.

このような突起があると、突起形状が鋭いために配線の
際、断線を生じるという問題がある。またSi酸化膜開
口部とエピタキシャル成長したSiとの界面付近の結晶
性は悪く、接合を形成した場合、接合リークを生じると
いう問題がある。特にバイポーラ構造では、エミツタ・
コレクタショートをこの部分で発生しやすくなり、デバ
イス特性を安定化させる上でも上記界面付近の結晶性を
よくすることが必要である。
When such protrusions are present, there is a problem in that the protrusions are sharp and may cause wire breakage during wiring. Further, the crystallinity near the interface between the Si oxide film opening and the epitaxially grown Si is poor, and when a junction is formed, there is a problem of junction leakage. Especially in bipolar structures, the emitter
Collector shorts tend to occur in this area, and it is necessary to improve the crystallinity near the interface in order to stabilize device characteristics.

〔発明の概要〕[Summary of the invention]

この発明は、かかる点に鑑みてなされたもので、酸化膜
分離法によって素子分離構造を得るようにした半導体装
置の製造方法において、絶縁膜開口部に形成されたエピ
タキシャル層をアニールして、該エピタキシャル層の上
記絶縁膜開口部エツジとの境界部の結晶性を回復せしめ
、また上記エピタキシャル層及び絶縁膜の表面を平坦に
研磨することにより、簡単な工程を追加するだけで上記
エピタキシャル層に形成される素子の特性を安定化する
ことができるとともに、突起による配線の断線を無くす
ことができ、高精度、高品質の素子分離構造が得られる
半導体装置の製造方法を提供することを目的としている
The present invention has been made in view of the above, and includes a method for manufacturing a semiconductor device in which an element isolation structure is obtained by an oxide film isolation method, in which an epitaxial layer formed in an opening in an insulating film is annealed. By restoring the crystallinity of the boundary between the epitaxial layer and the opening edge of the insulating film, and polishing the surfaces of the epitaxial layer and the insulating film flat, the epitaxial layer can be formed by simply adding a simple process. The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which can stabilize the characteristics of the device that is connected to the semiconductor device, eliminate wiring breaks due to protrusions, and obtain a highly accurate and high quality device isolation structure. .

(発明の実施例〕 以下、本発明の実施例を図について説明する。(Embodiments of the invention) Embodiments of the present invention will be described below with reference to the drawings.

第2図は本発明の一実施例による半導体装置の製造方法
を説明するための図であり、同図(8)〜(telはそ
れぞれ各工程における半導体装置の断面構造を示してい
る。
FIG. 2 is a diagram for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and (8) to (tel) in the figure each indicate a cross-sectional structure of the semiconductor device at each step.

次にこの第2図を用いて本実施例による製造方法を説明
する。
Next, the manufacturing method according to this embodiment will be explained using FIG. 2.

まず、同図+al fblに示すように、従来の製造方
法と同様の方法で、Si基板1上にSi酸化膜(絶縁膜
)2を形成し、該Si酸化膜2の一部領域に開口部を設
け、選択エピタキシャル成長法によって31層3を該開
口部に成長させる。そして本実施例においては、上記S
i酸化膜2の開口部と31層3との界面付近の領域の結
晶性を回復させるために、該領域を同図(b)で示すよ
うに、レーザビームアニール、ランプアニール、電子ビ
ームアニール等で再結晶化している。例えばランプアニ
ールでは、1200〜1300℃、10〜20秒程度で
ウェハ全体を加熱することにより結晶性は回復し、実用
化レベルとなる。
First, as shown in FIG. 31 layer 3 is grown in the opening by selective epitaxial growth. In this embodiment, the above S
In order to recover the crystallinity of the region near the interface between the opening of the i-oxide film 2 and the 31 layer 3, the region is subjected to laser beam annealing, lamp annealing, electron beam annealing, etc. as shown in FIG. It is recrystallized in For example, in lamp annealing, by heating the entire wafer at 1200 to 1300° C. for about 10 to 20 seconds, the crystallinity is restored to a level of practical use.

次に同図fc)で示すように研磨機でウェハ表面を軽く
研磨する。実際に研磨する際、突起部が消えた時点で急
激に研磨機の摩擦抵抗が増えるため、研磨のエンドポイ
ントをWJ単につ込・むことができる。従って極めて簡
単に、再現性よく研磨することができる。研磨機はSt
ウェハの鏡面仕上げ用のものを用いるため次工程へのよ
ごれ等の心配はない。
Next, as shown in fc) in the figure, the wafer surface is lightly polished using a polishing machine. During actual polishing, the frictional resistance of the polishing machine increases rapidly when the protrusion disappears, so the end point of polishing can be simply inserted into the WJ. Therefore, polishing can be performed extremely easily and with good reproducibility. The polishing machine is St.
Since it is used for mirror-finishing wafers, there is no need to worry about contamination of the next process.

このような本実施例の製造方法によれば、第3図fa)
で示すように、アニール後はパターン依存性やSi島は
そのまま反映されて凹凸構造がやや少なくなる程度に過
ぎないが、研暦後は同図fblに示すように、完全に平
坦化がなされる。従って従来のように、バートヘッド、
バードビーク等によって配線が断線されることもない。
According to the manufacturing method of this embodiment, as shown in FIG.
As shown in Figure fbl, after annealing, the pattern dependence and Si islands are reflected as they are, and the uneven structure is only slightly reduced, but after the annealing process, as shown in Figure fbl, it is completely flattened. . Therefore, as in the past, Barthead,
Wiring will not be disconnected due to bird beak etc.

またエピタキシャルN3をアニールして再結晶化するよ
うにしたので、該エピタキシャル層3に形成される素子
の特性を安定化することができる。またこのような製造
方法は従来検討されているいかなる方法よりも簡単なも
のである。
Furthermore, since the epitaxial layer N3 is annealed and recrystallized, the characteristics of the element formed in the epitaxial layer 3 can be stabilized. Moreover, such a manufacturing method is simpler than any method that has been considered in the past.

さらに本実施例によれば、第5図に示すように酸化膜2
をエツチングして、残った酸化膜を分離用の膜として用
いており、このような方法によれば、極めて素子間隔の
狭い分離が可能となる。これは写真製版工程において抜
きパターンより残しパターンの方が狭い幅がflられる
からである。従ってこの方法では0.5〜1μmの幅の
分離が容易に得られる。しかもドライエンチングとは言
え一般にはイオンの散乱等もあって上部程広めに仕上が
るので、例えばバイポーラの分離を行なう際、第5図で
示すように、埋込み屓6同士の間隔に少しマージンが生
じ、製造上有利となる。
Furthermore, according to this embodiment, as shown in FIG.
The remaining oxide film is used as an isolation film. According to this method, it is possible to isolate elements with extremely narrow spacing. This is because in the photolithography process, the width of the remaining pattern is narrower than that of the punched pattern. Therefore, with this method, a separation with a width of 0.5 to 1 μm can be easily obtained. Moreover, even though it is dry enching, the upper part is generally wider due to ion scattering, etc., so when separating bipolar, for example, there is a slight margin between the embedded fins 6, as shown in Figure 5. , which is advantageous in manufacturing.

なお上記実施例ではエピタキシャル層を形成する際に、
選択エピタキシャル成長法によって形成するようにした
が、これは非選択エピタキシャル成長法、即ち全面エピ
タキシャル成長法で形成しても上記実施例と同様の効果
が得られる。この際、全面エピタキシャル成長法を行な
うことで、酸化膜上には多結晶が成長するが、酸化膜厚
以下まで削り落としてしまうことで上記実施例と同様の
結果が得られる。
In addition, in the above embodiment, when forming the epitaxial layer,
Although the selective epitaxial growth method is used to form the film, the same effect as in the above embodiment can be obtained even if the film is formed by a non-selective epitaxial growth method, that is, an entire surface epitaxial growth method. At this time, by performing the full surface epitaxial growth method, polycrystals grow on the oxide film, but by scraping the polycrystals down to the thickness of the oxide film or less, the same results as in the above embodiment can be obtained.

また、全面エピタキシャル成長法でエピタキシャル層を
形成した場合、第4図+alに示すように、研磨の際の
その一部3゛を残しておき、しかる後エツチングで不要
な部分を除去するようにすれば、同図中)で示すように
、非活性領域3°゛を電極として利用する構造も容易に
得られる。
In addition, when an epitaxial layer is formed using the full-surface epitaxial growth method, as shown in Figure 4+al, a portion of the epitaxial layer can be left at 3゛ during polishing, and then the unnecessary portion can be removed by etching. , in the same figure), a structure in which the non-active region 3° is used as an electrode can also be easily obtained.

さらに、上記実施例では基板及び絶縁膜として、Si基
板及びSi酸化膜を例にとって説明したが、半導体装置
を作る上で必要な、GaAs、 InSb等の半導体基
板にエピタキシャル成長する際も全く同様の方法が適用
できることはもちろんである。
Furthermore, in the above embodiment, a Si substrate and a Si oxide film were used as an example of the substrate and the insulating film, but the same method can be used for epitaxial growth on semiconductor substrates such as GaAs and InSb, which are necessary for manufacturing semiconductor devices. Of course, it can be applied.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る半導体装置の製造方法に
よれば、酸化膜分離法によって素子分離構造を得る際、
絶縁膜開口部に形成されたエピタキシャル層をアニール
して再結晶化し、また該アニール処理後に上記エピタキ
シャル層及び絶縁膜の表面を平坦に研磨するようにした
ので、従来の工程に簡単な工程を追加するだけで、高精
度、高品質の素子分離構造が得られる効果がある。
As described above, according to the method for manufacturing a semiconductor device according to the present invention, when obtaining an element isolation structure by the oxide film isolation method,
The epitaxial layer formed in the insulating film opening is annealed and recrystallized, and after the annealing process, the surfaces of the epitaxial layer and insulating film are polished flat, which adds a simple process to the conventional process. By simply doing this, it is possible to obtain a high-precision, high-quality element isolation structure.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図番才従来の選択エピタキシャル層による素子分離
方法を説明するための構造断面図、第2図は本発明の一
実施例による半導体装置の製造方法を説明するための構
造断面図、第3図は第2図の実施例における研冴工程前
後の構造断面図、第4図は本発明の他の実施例を示す図
、第5図は本発明における素子分離間隔を説明するため
の図であ1・・・基板、2・・・Si酸化膜(絶縁膜)
、3・・・エピタキシャル層。 なお図中、同一符号は同−又は相当部分を示す。 代理人 大岩増雄 第1図 (Q) 第2図 (Q) 第3図
Fig. 1 is a structural cross-sectional view for explaining a conventional device isolation method using a selective epitaxial layer; Fig. 2 is a structural cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention; The figures are cross-sectional views of the structure before and after the polishing process in the embodiment of Fig. 2, Fig. 4 is a diagram showing another embodiment of the present invention, and Fig. 5 is a diagram for explaining the element isolation interval in the present invention. A1...Substrate, 2...Si oxide film (insulating film)
, 3...Epitaxial layer. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 (Q) Figure 2 (Q) Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の一生面に絶縁膜を形成し、該絶縁膜
の一部領域に開口部を設け、該開口部にエピタキシャル
層を形成し、該エピタキシャル層の上記開口部エツジと
の境界部の結晶性を回復すべく少なくとも該エピタキシ
ャル層を含むその周辺領域をアニールし、上記エビクキ
シャノシ層及び絶縁膜の表面を平坦に研磨することを特
徴とする半導体装置の製造方法。
(1) An insulating film is formed on the whole surface of a semiconductor substrate, an opening is provided in a part of the insulating film, an epitaxial layer is formed in the opening, and a boundary between the epitaxial layer and the edge of the opening is formed. 1. A method of manufacturing a semiconductor device, comprising: annealing at least a peripheral region including the epitaxial layer to restore crystallinity; and polishing the surfaces of the epitaxial layer and the insulating film to a flat surface.
(2)上記エピタキシャル層の形成は、選択エピタキシ
ャル成長法によって行なうことを特徴とする特許請求の
範囲第1項記載の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the epitaxial layer is formed by selective epitaxial growth.
(3)上記エピタキシャル層の形成は、非選択エピタキ
シャル成長法によって行なうことを特徴とする特許請求
の範囲第1項記載の半導体装置の製造方法。
(3) The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial layer is formed by a non-selective epitaxial growth method.
JP5674984A 1984-03-23 1984-03-23 Manufacture of semiconductor device Pending JPS60198811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5674984A JPS60198811A (en) 1984-03-23 1984-03-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5674984A JPS60198811A (en) 1984-03-23 1984-03-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60198811A true JPS60198811A (en) 1985-10-08

Family

ID=13036170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5674984A Pending JPS60198811A (en) 1984-03-23 1984-03-23 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60198811A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03295235A (en) * 1990-04-12 1991-12-26 Toshiba Corp Manufacture of epitaxial wafer
US5963822A (en) * 1996-04-12 1999-10-05 Kabushiki Kaisha Toshiba Method of forming selective epitaxial film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03295235A (en) * 1990-04-12 1991-12-26 Toshiba Corp Manufacture of epitaxial wafer
US5963822A (en) * 1996-04-12 1999-10-05 Kabushiki Kaisha Toshiba Method of forming selective epitaxial film

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