JPS60194817A - Digital signal processor - Google Patents

Abstract

PURPOSE:To attain ease of fetch of input/output by dividing a random access memory (RAM) into an input data, an operation work area and an output data area, writing a data through interruption while the operation is executed and applying page changeover to the area after the end of operation. CONSTITUTION:In sectioning an input digital data into a prescribed length of frames and applying Fourier transformation (FFT) at each frame, the RAM3 is divided into the input data area, the operation work area and the output data area and the input data is fetched in the input data area during the execution of operation through the interruption processing. The arithmetic operation is executed by using the operation work area. After the end of the arithmetic operation, the result of operation is stored in the work area. Thus, the changeover of page allows the operation work area to be switched to the output data area, the input data area to be switched to the operation work area and the output data area to be switched to the input data area.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a digital signal processing device used, for example, in processing digitized audio signals. Background technology and its problems For example, when performing speech recognition, an audio signal is digitized, this digital signal is divided into frames of predetermined sample units, and each frame is subjected to Fourier transform (
FFT) and analysis is performed. Such FFT is generally performed as follows. 1st
In the figure, for example, 8 samples (words x (0) to x
(7)) as one frame, first word x(0
) (the value is aoo, the same applies hereafter) and x (41(b
oo ), x (21(a 10 ) and x(61(b
to), x(1)(a2o) and x(51(b 20
), x (31 (a 30 ) and X (71 (bao)
A so-called butterfly calculation is performed in which a tj+W; j5b rj a Lj-WB-b rh respectively. Furthermore, regarding these calculation results, aoo (!l: b The sum of oo is aol, the difference is ail, and the sum of 5aio and blo is bo
The Ls difference is bll, the sum of a20 and b20 is a21, the difference is a31, the sum of a30 and b30 is b21, and the difference is b3
1 and perform the same butterfly calculation. Furthermore, the sum of aot and boi is 802, the difference is 822, and ail and bll
The sum is 812, the difference is 832, the sum of 5a21 and b21 is bo2-, the difference is b22, and the sum of a31 and b31 is b1
2. Set the difference to b32 and perform the same butterfly calculation. Then, the sum of a02 and b02 is X (0), and the difference is X (4)
Let the sum of a12 and b12 be X(1), the difference be X(5), the sum of a22 and b22 be X(2), the difference be X(6), and the sum of a32 and ba2 be X(3). , let the difference be X(7),
Obtain the FFT values of X(0) to X(7). That is, FFT can be performed on one frame of data of 8 (-23) words by performing butterfly calculations 12 times (4 times in each stage x 3 stages = 12 times). Incidentally, when performing the above-mentioned arithmetic processing, a digital signal processing unit (DSP) having built-in multipliers, adders, registers for coefficients, etc. is actually used. That is, in FIG. 2, data from an input terminal (1) is supplied to D S'P (2), and is output from this DSPQω to an output terminal (2). This D S P Q(l
random access memory (RA) for storing data.
M) (31 is connected and a memory control unit) (MCU) (41) which also controls this RAM M (3) is provided. signals and control signals from the host CPU (5) are supplied, and according to these signals the RAM
(The address of 31 is controlled. Furthermore, the coefficients necessary for the calculation are retrieved by searching the read-only memory (ROM) (6) that serves as a coefficient table, and these coefficients are supplied to the DSP (lω through the CPU 51). In addition, a control signal from the CPU (51) is supplied to the DSP←ω and the MCU (41. As a result, for example, the above-mentioned FFT is performed. However, in this device, the FFT operation is performed using a predetermined clock pulse. On the other hand, the detection of input digital data is performed at a sampling period asynchronous to the clock pulse.Therefore, the acquisition of such input data (writing to RAM (31)) is performed in the same way as the above-mentioned 0FFT operation. It is difficult to process this using a program.Therefore, in the past, for example, an input cover memory for one frame was provided, and the data written in this memory was directly transferred to RAM +31 at the end of each frame. However, this method requires a separate RAM for Batza memory, and also requires a program and configuration for direct transfer, making the device complicated. OBJECT OF THE INVENTION In view of the above-mentioned points, the present invention is intended to enable good input data capture and arithmetic processing with a simple configuration. In a digital signal processing device that divides data into frames of a predetermined length and performs arithmetic processing for each frame, the random access memory is divided into an input data area, a calculation work area, and an output data area, and the While performing the above arithmetic processing using the area, the above input digital data is written to the above input data area by interrupt processing, and after the arithmetic processing of the above frame of - is completed, the above arithmetic work area is output. Switch the page of the random access memory so that the input data area becomes the data area, the input data area becomes the calculation work area, and the output data area becomes the input data area, and perform calculation processing for the next frame,
The present invention is a digital signal processing device that sequentially repeats this operation, and can perform good input data acquisition and arithmetic processing with a simple configuration. Embodiment By the way, in the above-mentioned apparatus, D S P (1(O) is specifically constructed as follows. In FIG.
A data bus (21) is provided, and this data bus (21
) is connected to a data RAM +31 and a RAM (22) for storing coefficients taken out from the coefficient table. A desired coefficient from the coefficient RAM (22) is then supplied to the register (23) via the data bus (21).
Memorized temporarily. The data from the data RAM (31) is then supplied to the multiplier (24) through the data bus (21) and the coefficients from the register (23) are supplied to the multiplier (24). The output of the adder (24) is supplied to one input of the adder (25).
The other input of the register (25) is supplied with a signal from the data bus (21) to the register (26).
) is supplied. Here register (23),
Multiplier (24), adder (25), register (26)
The part surrounded by the broken line is generally packaged into one LSI (30). Furthermore, an instruction decoder (27) for controlling the operation of this LSI (30) and a sequencer (28) for sequentially driving this decoder (27) are provided. And CPU
A control signal from (5) is supplied to the sequencer (28). Also, from LSI (40) to MCU (41 and R
A control signal to AM (22) is output. Roughly ten circuits (29) are connected to the data bus (21), and input terminals (1) and output terminals (2) are led out. In this circuit, by arbitrarily controlling each register, etc., it is possible to perform, for example, the above-mentioned 0FFT operation. Furthermore, the instruction decoder (27) is provided with a program as shown in the flowchart of FIG. 4, for example. A in this figure is a case where an N-point FFT calculation is performed. First, in the first step [1], each variable 1+J+n is set to “
0" is set. Next, in step [2], R of a, j, bLl, WNj
The addresses of A M (3) and (22) are calculated. Next, in step [3], butterfly calculation is performed using the data read from the calculated address. Next, in step [4], the value of i is incremented. Furthermore, in step [5], it is determined that i=N/2. Here, if 1f-N/2, the process returns to step [2]. As a result, the calculation is repeated by moving vertically in FIG. In this step, i is reset to 0'' and the value of j is incremented. Roughly in step [7], j = log N is determined. Here, when j f log N, step [2
] will be returned to. As a result, the computation is repeated by moving laterally in FIG. When j = log N, the F'FT calculation for one frame (N points) has been completed. Furthermore, if data is detected during the 0FFT calculation, the data is taken in by so-called interrupt processing. FIG. 4B shows a flowchart for this purpose. That is, in the first step [11], the values of registers such as variables i and j are saved. Next, the RAM of the data input/output in step [12]
+3) address is calculated. Here RAM (3)
As shown in FIG. 5, the area is divided into an input data area, an arithmetic work area, and an output data area, each of which has a predetermined address mapping for performing page switching, which will be described later. Next, the input data is stored at the address calculated in step [13], and the data at the calculated address is output. Next, in step [14], the value of n is incremented. Furthermore, in step [15], the saved register values are restored and the process returns to the original routine. In order to perform the above-mentioned interrupt processing in the S P QOI, the instruction decoder (27) and the sequencer (28) perform the following processing, for example. In FIG. 6, the output of the decoder (27) is supplied to the control bus (41). Also CPU (51
Signal and decoder (27) indicating the start of calculation from
is supplied to the control bus (41). This first address is the control bus (41)
to input A of the multiplexer (42). Further, a signal from the control bus (41) is supplied to the instruction logic (43), and input A is selected by the multiplexer (42) during one clock period immediately after the start of the calculation. The signal (address) from this input A is sent to the decoder (27)
is supplied to start the calculation operation. Further, the address from this multiplexer (42) is sent to an adder (44).
), and this added value is added to the clock pulse CP.
is supplied to a register (45) driven by The signal from this register (45) is fed to input B of the multiplexer (42). After the calculation starts, input B is selected by the multiplexer (42), so that sequentially incremented addresses are supplied to the decoder (27). When further interrupt processing is to be performed, first the decoder (27
) in the main routine, a signal indicating the type of interrupt processing,
The first address of the program is printed. This address is transferred from the control bus (41) to the register (46).
) and loaded with 'C on the output from logic (43). The signal from this register (46) is fed to input C of the multiplexer (42). A signal indicating the type of interrupt processing is also supplied to the logic (47). Furthermore, a signal from a register (45) is fed to a register (48), which signal is fed to an input C of a multiplexer (42). Then, when a request for interrupt processing is made from the CPU (5), a signal indicating type N of the interrupt processing from the CPU (5) is supplied to the logic (47), and the signal from the logic (43) described above is supplied to the logic (47). A match is determined and the output is retrieved when there is a match. The signal from this logic (47) is sent to the multiplexer (42) and register (48).
). This signal allows the multiplexer (
In step 42), the manual power C is selected for a one-crop period. As a result, the address of the instruction decoder (27) is jumped to the first address of the interrupt processing routine, and thereafter the address is incremented by selecting input B at the multiplexer (42). Furthermore, a return instruction is provided at the last address of this interrupt processing, and when this return instruction is output, the logic (43) causes the multiplexer (42) to select the manual operation for one clock period. This returns the address of the instruction decoder (27) to the address immediately before the start of the interrupt process. In this way, interrupt processing is performed in DSP (10). Furthermore, in the flowchart of FIG. 4A, step [
After the FFT calculation is completed in step [7], it is determined whether n=N in step [8]. Here, when n≠N, the data acquisition for one frame (N points) has not been completed, so the process waits until -, n-H, and during this time, data acquisition interrupt processing is performed in response to a request. And when it becomes n-N, step

Proceed to [9]. this step

In [9], page switching of RAM (31) is performed.
(At step 41, the upper digits of the address are read, and from then on, pages are switched so that the calculation work area up to that point becomes the output data area, the input data area becomes the calculation work area, and the output data area becomes the input data area.) After this page switching, the process returns to step [1]. This is how the arithmetic processing is performed. According to the above-mentioned device, interrupt processing is performed with a simple configuration, and data is processed using this interrupt processing. By importing data, it is possible to import data extremely easily, and by switching pages of the random access memory, data input/output and arithmetic processing can be performed extremely well.Effects of the Invention According to the present invention For example, it has become possible to import input data and perform arithmetic processing with a simple configuration.

[Brief explanation of drawings]

1 and 2 are diagrams for explaining the background art, FIG. 3 is a configuration diagram of an example of the present invention, and FIGS. 4 to 6 are diagrams for explaining the same. (1) is an input terminal, (2) is an output terminal, (3) is a random access memory, (5) is a CPU, Q[l] is a digital signal processing unit, (27) is an instruction decoder, (2)
8) is a sequencer. Figure 1 Figure 6 Hawk (

Claims (1)

[Claims] In a digital signal processing device that divides input digital data into frames of a predetermined length and performs arithmetic processing for each frame, the random access memory is divided into an input data area, a calculation work area, and an output data area. While the above arithmetic processing is being performed using the arithmetic work area, the above input digital data is written to the above input data area by interrupt processing, and after the arithmetic processing of the above frame of - is completed, the above arithmetic work area is written. The above random and access memory pages are switched so that the above input data area becomes the output data area, the above input data area becomes the calculation work area, and the above output data area becomes the input data area, and the calculation processing of the next above frame is performed. A digital signal processing device configured to sequentially and repeatedly perform the following steps.