JPS60193345A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60193345A JPS60193345A JP59049646A JP4964684A JPS60193345A JP S60193345 A JPS60193345 A JP S60193345A JP 59049646 A JP59049646 A JP 59049646A JP 4964684 A JP4964684 A JP 4964684A JP S60193345 A JPS60193345 A JP S60193345A
- Authority
- JP
- Japan
- Prior art keywords
- transparent body
- mold
- resin
- sealing
- resin layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229920005989 resin Polymers 0.000 claims abstract description 61
- 239000011347 resin Substances 0.000 claims abstract description 61
- 238000007789 sealing Methods 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 12
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 229920002050 silicone resin Polymers 0.000 claims description 5
- 238000009210 therapy by ultrasound Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 5
- 239000007787 solid Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000002525 ultrasonication Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置、とくに、光消去可能なメモリー素
子や、ＣＯＤ、ＣＰＤ等の固体撮像素子を封有し、光透
過性の窓を有する樹脂封止型半導体装置の製造方法に関
する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device, particularly a resin-sealed semiconductor device that encapsulates a photo-erasable memory element or a solid-state image sensor such as COD or CPD, and has a light-transmissive window. The present invention relates to a method for manufacturing a fixed type semiconductor device.
従来例の構成とその問題点
光で消去を行なう半導体メモリー装着や固体撮像装置で
は、コストダウンをねらって、従来のセラミック製のパ
ッケージに代わって、光透過性の窓材を封止樹脂ととも
に一体成型したパッケージを用いたものが現れている。Conventional configurations and their problems In semiconductor memory devices and solid-state imaging devices that are erased using light, a light-transmissive window material is integrated with a sealing resin in place of the conventional ceramic package in order to reduce costs. Products using molded packages are appearing.
従来、このような装置は第１図〜第３図に示すように、
まず、第１図のように、半導体メモリー素子や固体撮像
素子１を素子載置板２上に固定し、素子１上の電極と外
部リード３の内端とを金属細線４で接続し、ついで、第
２図のように、光透過性の樹脂６を介して透明体６を接
着し、この透明体６０表面を封止用金型７の内壁に押し
当てた状態で金型空間に封止樹脂８を注入して、第３図
のように樹脂封止成型を行なっていた。この製造方法で
は、透明体６０表面を金型７の内壁に押し崩てる際、強
すぎると石英やアルミナガラスからなる透明体６の表面
に傷がついたり、あるいは破損したりする。一方押し当
てる圧力が不十分だと封止樹脂注入のとき透切体６の表
面と金型７の内壁とのすきまにまで封止樹脂が入りこみ
透明体６の表面上に薄い樹脂膜を形成する。この樹脂膜
は後に機械的に除去しなければならず、煩雑な工程が必
要である。また機械的な除去を行なうと透明体６０表面
が傷つけら常に厳密にコノトロールしなければいけない
。このことはリードフレームや透明体の寸法および透明
体を半導体素子表面に接着する工程に対し、非常な高精
度を要求することになり、コストアンプやスループット
の低下をまねく。Conventionally, such a device, as shown in FIGS. 1 to 3,
First, as shown in FIG. 1, a semiconductor memory device or a solid-state image sensor 1 is fixed on a device mounting plate 2, and the electrodes on the device 1 and the inner ends of the external leads 3 are connected with thin metal wires 4. , as shown in FIG. 2, a transparent body 6 is adhered via a light-transmitting resin 6, and the surface of this transparent body 60 is pressed against the inner wall of a sealing mold 7 and sealed in the mold space. Resin 8 was injected and resin sealing molding was performed as shown in FIG. In this manufacturing method, when pressing the surface of the transparent body 60 against the inner wall of the mold 7, if the pressure is too strong, the surface of the transparent body 6 made of quartz or alumina glass may be scratched or damaged. On the other hand, if the pressing pressure is insufficient, the sealing resin will enter the gap between the surface of the transparent body 6 and the inner wall of the mold 7 when injecting the sealing resin, forming a thin resin film on the surface of the transparent body 6. . This resin film must be removed mechanically later, which requires a complicated process. Further, mechanical removal may damage the surface of the transparent body 60, so strict control must be performed at all times. This requires extremely high precision in the dimensions of the lead frame and the transparent body, and in the process of bonding the transparent body to the surface of the semiconductor element, leading to a reduction in cost and throughput.
発明の目的
本発明は上に述べたような従来の製造方法に見られた問
題をと９除いた製造方法を提供することを目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to provide a manufacturing method that eliminates the problems found in the conventional manufacturing methods as described above.
発明の構成
本発明は半導体素子表面上に透明体を設け、樹脂封止前
に透明体表面に弾性樹脂層を設け、弾性樹脂層を金型内
壁に押しあてた状態で、樹脂封止すべき構造体を金型に
固定し、封止用樹脂を注入。Structure of the Invention The present invention provides a transparent body on the surface of a semiconductor element, an elastic resin layer on the surface of the transparent body before resin sealing, and resin sealing with the elastic resin layer pressed against the inner wall of the mold. The structure is fixed in the mold and the sealing resin is injected.
硬化した後、前記弾性樹脂層を除去し、前記透明体表面
を露出させる工程を含む製造方法であり、この製造方法
によれば、金型に構造体を固定する際に透明体表面に傷
が入ったり、あるいは破損したすせず、また透明体表面
に封止樹脂の薄い膜が形成されることもなく、煩雑な工
程を付加することなく、高歩留りで半導体装置が製造で
きる。This manufacturing method includes a step of removing the elastic resin layer after curing to expose the surface of the transparent body, and according to this manufacturing method, there is no possibility that the surface of the transparent body is scratched when fixing the structure to the mold. Semiconductor devices can be manufactured at a high yield without adding any complicated steps, without causing scum to enter or break, and without forming a thin film of sealing resin on the surface of the transparent body.
実施例の説明
第４図〜第８図の工程順断面図を参照して本発明の第１
実施例を説明する。まず、第４図のように、光消去を行
なう半導体メモリー素子やＣＯＤ。DESCRIPTION OF THE EMBODIMENTS Referring to the step-by-step sectional views of FIGS. 4 to 8, the first embodiment of the present invention will be described.
An example will be explained. First, as shown in Figure 4, there is a semiconductor memory device or COD that performs optical erasure.
ＣＰＤ等の固体撮像素子（以下、光感応素子という）１
を素子載置板２上に固定し、同光感応素子１上の電極と
外部リード３とを金属細線４で接続し、シリコーン樹脂
などの光透過性の樹脂６を介して窓材となる石英、アル
ミナガラス等の透明体６を設ける。これまでは第１図の
場合と同じである。Solid-state imaging device such as CPD (hereinafter referred to as photosensitive device) 1
is fixed on the element mounting plate 2, and the electrode on the photosensitive element 1 and the external lead 3 are connected with a thin metal wire 4, and the quartz which becomes the window material is connected through a light-transmitting resin 6 such as silicone resin. , a transparent body 6 such as alumina glass is provided. The process up to this point is the same as in the case of FIG.
次に、第６図のように透明体６０表面に弾性樹脂層９を
形成する。本実施例では面積約３６−の透明体６の表面
に６〜１０ｍ９のシリコーン樹脂を塗布し１６０〜２０
０℃でキュアーを行ない最終的に厚さ３００〜５００１
上ｍの弾性樹脂層９を得た。Next, as shown in FIG. 6, an elastic resin layer 9 is formed on the surface of the transparent body 60. In this example, 6 to 10 m9 of silicone resin is coated on the surface of a transparent body 6 with an area of about 36 m.
Cure at 0℃ and finally have a thickness of 300~5001
An upper m elastic resin layer 9 was obtained.
金型空間内に封止樹脂８を注入する。封止樹脂８の硬化
が終了した製品は第７図のようになる。A sealing resin 8 is injected into the mold space. The product after the sealing resin 8 has been cured looks like the one shown in FIG.
つづいて、透明体６の表面の弾性樹脂層９の除去を行な
う。本実施例で弾性樹脂層９として用いたシリコーン樹
脂は、室温硫酸中で超音波を印加すれば数分間以内に選
択的に除去できる。弾性樹脂層９を完全に除去し透明体
６の表面を露出させると第８図に示すようになり、外部
リード３の折り曲げ成型。Subsequently, the elastic resin layer 9 on the surface of the transparent body 6 is removed. The silicone resin used as the elastic resin layer 9 in this example can be selectively removed within several minutes by applying ultrasonic waves in room temperature sulfuric acid. When the elastic resin layer 9 is completely removed and the surface of the transparent body 6 is exposed, it becomes as shown in FIG. 8, and the external lead 3 is bent and formed.
試験、マーキングを経て、製品は完成する。この製造方
法によれば樹脂封止の際に透明体６が金型７の内壁に直
接押しあてられることがないため透明体６表面に傷がつ
いたり破損したりすることがない。また透明体６の表面
と金型７の内壁との間は弾性樹脂層９が介在し、両者に
密着しているため、不要な封止樹脂の膜が発生すること
がない。After testing and marking, the product is completed. According to this manufacturing method, the transparent body 6 is not directly pressed against the inner wall of the mold 7 during resin sealing, so that the surface of the transparent body 6 is not scratched or damaged. Moreover, since the elastic resin layer 9 is interposed between the surface of the transparent body 6 and the inner wall of the mold 7 and is in close contact with both, no unnecessary sealing resin film is generated.
また透明体６と金型７の内壁の間に弾性樹脂層９次に第
９図〜第１３図の工程１屓断面図を用いて第２実施例を
説明する。第９図のように透明体６を光感応素子１上に
設けるまでは第１実施例と同様である。つづいて、第１
０図のように透明体６の表面にシリコーン樹脂などの弾
性樹脂層９を設ける。本実施例では第１０図に示すよう
に、透明体６０表面周縁に弾性樹脂層９を形成せず、封
止後露出させるべき領域のみに弾性樹脂層９を選択的に
形成する。後の工程は第１実施例に示したとおり、第１
１図のように、弾性樹脂層９を金型７の内壁に押しあて
て封止すべき構造体を固定して、金型７による空間内に
封止樹脂８を注入、硬化させ、第１２図のような封止構
造を作る。そして、第１３図のように、弾性樹脂層９を
、たとえば室温硫酸中で超音波処理をして除去すれば透
明体６の表面が露出する。この製造方法によれば、第１
実施例の効果に加えて、透明体６の表面周縁部が封止樹
脂８におおわれており、透明体６の固定がより完全にな
るとともに、透明体６と封止樹脂８との界面をつたわっ
ての水分の侵入を考えると、本製造方法で得られる半導
体装置はその侵入経路が長くなっており、耐湿性の向上
も期待できる。Further, the second embodiment will be described using the elastic resin layer 9 between the transparent body 6 and the inner wall of the mold 7, using step 1 cross-sectional views of FIGS. 9 to 13. This embodiment is the same as the first embodiment until the transparent body 6 is provided on the photosensitive element 1 as shown in FIG. Next, the first
As shown in Figure 0, an elastic resin layer 9 such as silicone resin is provided on the surface of the transparent body 6. In this embodiment, as shown in FIG. 10, the elastic resin layer 9 is not formed on the periphery of the surface of the transparent body 60, but the elastic resin layer 9 is selectively formed only in the area to be exposed after sealing. The subsequent steps are as shown in the first embodiment.
As shown in FIG. 1, the structure to be sealed is fixed by pressing the elastic resin layer 9 against the inner wall of the mold 7, and the sealing resin 8 is injected into the space formed by the mold 7 and hardened. Create a sealing structure as shown in the figure. Then, as shown in FIG. 13, if the elastic resin layer 9 is removed by ultrasonication in room temperature sulfuric acid, the surface of the transparent body 6 is exposed. According to this manufacturing method, the first
In addition to the effects of the embodiment, the peripheral edge of the surface of the transparent body 6 is covered with the sealing resin 8, which makes the fixation of the transparent body 6 more complete and allows the interface between the transparent body 6 and the sealing resin 8 to be Considering the possibility of moisture infiltration, the semiconductor device obtained by this manufacturing method has a longer ingress route, and is expected to have improved moisture resistance.
また別の実施例として、第１４図〜第１８図にその工程
順断面図を示す。これの各工程は、第９図〜第１３図の
場合と同じで、説明を省略するが、この結果をいえば、
透明体６の表面周縁部に環状に弾性樹脂層９を形成する
方法も可能である。この方法では透明体６の表面中央部
には弾性樹脂層９は形成されないが、金型７の内壁には
透明体６の表面周縁部の弾性樹脂層９が押しあてられる
ため透明体６の表面中央部は金型７の内壁と接触せず、
傷が生じたり、あるいは破損の心配はない。As another example, FIGS. 14 to 18 show cross-sectional views in the order of steps. Each step in this process is the same as in the case of FIGS. 9 to 13, and the explanation is omitted, but the results are as follows.
It is also possible to form an annular elastic resin layer 9 on the peripheral edge of the surface of the transparent body 6. In this method, the elastic resin layer 9 is not formed at the center of the surface of the transparent body 6, but since the elastic resin layer 9 at the peripheral edge of the surface of the transparent body 6 is pressed against the inner wall of the mold 7, the surface of the transparent body 6 is The center part does not contact the inner wall of the mold 7,
There is no need to worry about scratches or damage.
また、注入された樹脂８は透明体６の表面周縁部の弾性
樹脂層９によって阻止され、透明体６の表面中央部にい
たることもない。封止後、透明体６の表面周縁部に残っ
た弾性樹脂層９は第１．第２実施例と同様の方法で除去
できる。Further, the injected resin 8 is blocked by the elastic resin layer 9 at the peripheral edge of the surface of the transparent body 6, and does not reach the center of the surface of the transparent body 6. After sealing, the elastic resin layer 9 remaining on the surface periphery of the transparent body 6 is the first layer. It can be removed by the same method as in the second embodiment.
発明の効果
本発明によれば素子表面上に透明体を有し、透明体の表
面を露出させて樹脂外囲部が形成される半導体装置の製
造方法において非常に高い寸法精度をもつ材料２部品を
用いたり、厳密な管理を行なうことなく樹脂封止が実施
でき、また樹脂封止後の処理も化学的で、透明体表面に
傷がつけるおそれがないので、低コストでかつ高歩留り
の製造が可能となる。Effects of the Invention According to the present invention, two parts made of materials having extremely high dimensional accuracy are used in a method of manufacturing a semiconductor device in which a transparent body is provided on the element surface and a resin envelope is formed by exposing the surface of the transparent body. Resin sealing can be carried out without using or strict control, and the treatment after resin sealing is chemical, so there is no risk of damaging the surface of the transparent body, allowing for low-cost and high-yield manufacturing. becomes possible.
第１図〜第３図は従来の製造方法を説明した工程順断面
図、第４図〜第８図は本発明第１実施例の製造方法を説
明した工程順断面図、第９図〜第１３図は本発明第２実
施例の製造方法を説明した工程断面図、第１４図〜第１
８図は本発明第３実施例の製造方法を説明した工程順断
面図である。
１・・・・・・光感応素子、２・・・・・・素子載置板
、３・・・・・・リード、４・・・・・・金属細線、６
・・・・・・光透過性樹脂、６・・・・・・透明体（窓
材）、７・・・・・・封止金型、８・・・・・・封止樹
脂（外囲部）、９・・・・・・弾性樹脂。
代理人の氏名 弁理士 中 尾 敏 男 はが１名第１
図
第 ２ 図
第４図
第８図
？
第９図
第１１図
第１２１７１
第１３図
第１４図
第１５図1 to 3 are step-by-step sectional views explaining the conventional manufacturing method, FIGS. 4 to 8 are step-by-step sectional views explaining the manufacturing method of the first embodiment of the present invention, and FIGS. Figure 13 is a process cross-sectional view explaining the manufacturing method of the second embodiment of the present invention, and Figures 14 to 1
FIG. 8 is a step-by-step sectional view illustrating the manufacturing method of the third embodiment of the present invention. 1...Photosensitive element, 2...Element mounting plate, 3...Lead, 4...Thin metal wire, 6
......Light-transmitting resin, 6...Transparent body (window material), 7... Sealing mold, 8... Sealing resin (outer enclosure) Part), 9...Elastic resin. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 Figure 4 Figure 8? Figure 9 Figure 11 Figure 12171 Figure 13 Figure 14 Figure 15
Claims (2)
前記透明体表面に弾性樹脂層を設け、同弾性樹脂層を金
型内壁に押し当てた状態で樹脂封止すべき構造体を前記
金型に固定し、封止用樹脂を注入した後、前記弾性樹脂
層を除去し、前記透明体表面を露出させる工程をそなえ
た半導体装置の製造方法。(1) A structure in which a transparent body is provided on the surface of a semiconductor element, an elastic resin layer is provided on the surface of the transparent body before resin sealing, and the elastic resin layer is pressed against the inner wall of the mold and then resin-sealed. A method for manufacturing a semiconductor device, comprising the steps of: fixing the transparent body to the mold, injecting a sealing resin, and then removing the elastic resin layer to expose the surface of the transparent body.
として室温硫酸中での超音波処理を用いる特許請求の範
囲第１項に記載の半導体装置の製造方法・(2) The method for manufacturing a semiconductor device according to claim 1, wherein the elastic resin is a silicone resin, and the method for removing it is ultrasonic treatment in room temperature sulfuric acid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59049646A JPS60193345A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59049646A JPS60193345A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60193345A true JPS60193345A (en) | 1985-10-01 |
Family
ID=12836967
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59049646A Pending JPS60193345A (en) | 1984-03-15 | 1984-03-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60193345A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4812420A (en) * | 1986-09-30 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor device having a light transparent window |
| EP0682374A1 (en) * | 1994-05-09 | 1995-11-15 | Euratec B.V. | Method for encapsulating an integrated circuit |
| WO1998008251A1 (en) * | 1996-08-20 | 1998-02-26 | Hitachi, Ltd. | Semiconductor and method for manufacturing the same |
| EP0936683A1 (en) * | 1997-06-27 | 1999-08-18 | Iwasaki Electric Co., Ltd. | Reflection type light emitting diode |
| EP1246235A1 (en) * | 2001-03-26 | 2002-10-02 | European Semiconductor Assembly (Eurasem) B.V. | Method for encapsulating a chip having a sensitive surface |
| WO2003069670A1 (en) * | 2002-02-18 | 2003-08-21 | Shinko Electric Industries Co., Ltd. | Semiconductor device and method for manufacturing same |
| WO2006092725A1 (en) * | 2005-03-03 | 2006-09-08 | Melexis Nv | Packaging integrated circuits |
-
1984
- 1984-03-15 JP JP59049646A patent/JPS60193345A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4812420A (en) * | 1986-09-30 | 1989-03-14 | Mitsubishi Denki Kabushiki Kaisha | Method of producing a semiconductor device having a light transparent window |
| EP0682374A1 (en) * | 1994-05-09 | 1995-11-15 | Euratec B.V. | Method for encapsulating an integrated circuit |
| NL9400766A (en) * | 1994-05-09 | 1995-12-01 | Euratec Bv | Method for encapsulating an integrated semiconductor circuit. |
| US5863810A (en) * | 1994-05-09 | 1999-01-26 | Euratec B.V. | Method for encapsulating an integrated circuit having a window |
| WO1998008251A1 (en) * | 1996-08-20 | 1998-02-26 | Hitachi, Ltd. | Semiconductor and method for manufacturing the same |
| EP0936683A1 (en) * | 1997-06-27 | 1999-08-18 | Iwasaki Electric Co., Ltd. | Reflection type light emitting diode |
| EP0936683A4 (en) * | 1997-06-27 | 2000-11-22 | Iwasaki Electric Co Ltd | Reflection type light emitting diode |
| EP1246235A1 (en) * | 2001-03-26 | 2002-10-02 | European Semiconductor Assembly (Eurasem) B.V. | Method for encapsulating a chip having a sensitive surface |
| WO2002078077A1 (en) * | 2001-03-26 | 2002-10-03 | European Semiconductor Assembly (Eurasem) B.V. | Method for encapsulating a chip having a sensitive surface |
| US7312106B2 (en) | 2001-03-26 | 2007-12-25 | Elmos Advanced Packaging B.V. | Method for encapsulating a chip having a sensitive surface |
| WO2003069670A1 (en) * | 2002-02-18 | 2003-08-21 | Shinko Electric Industries Co., Ltd. | Semiconductor device and method for manufacturing same |
| WO2006092725A1 (en) * | 2005-03-03 | 2006-09-08 | Melexis Nv | Packaging integrated circuits |
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