JPS6019314A - Pulse delay circuit - Google Patents

Abstract

PURPOSE:To allow the circuit characteristics to be heardly affected by the variance of an element value by charging/discharging a capacitor in response to a potential of an input pulse signal so as to generate a triangle wave signal and comparing the said potential with a prescribed value so as to generate a square wave for a prescribed period. CONSTITUTION:An input pulse as shown in Fig. (a) is applied to a base of a transistor (TR) 11, and the TR11 is turned on only for a period T' of the pulse V11. A base potential of a TR12 is lower than a base potential E12 of a TR13 and the TR12 is turned on in this case. A constant current I11 flows to the TR12 and a capacitor 22 is charged by the current I11 in this case. Further, when the TR11 is turned off, a TR13 is turned on and the capacitor 22 is discharged by a constant current I11XR12/R11. When the potential at a terminal B of one TR17 constituting a differential comparator is higher than a base potential E13 of a TR18, the TR18 is turned on and a current I12 of a constant current source 21 flows to a collector of the TR18. Thus, a TR19 is turned off when the input pulse signal is logical ''H'' (period T'), a collector output of the TR18 is a potential I12.R13, and the pulse width TG' is decided by a resistance ratio R11/R12 obtained with high accuracy even if the circuit is integrated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a pulse delay circuit, and more particularly to a pulse delay circuit suitable for shaping gate pulses of a color vision receiver.

[Technical background of the invention and its problems]

In color television broadcasting, % 1iil -r
Color subcarriers with a phase difference of 90 degrees at the rrrl wave number are balanced-modulated with 2 color difference signals (color information is transmitted by 12 color signals. This carrier color signal does not have +?2 transmit components. Therefore, the color subcarrier itself is not transmitted, but only the sideband containing color information is transmitted.Therefore, on the image transmission side, a color burst containing information on the same wave number and phase of the subcarrier along with the carrier color signal is transmitted. A signal is sent so that a color television receiver can demodulate the color difference 411 from the carrier color signal.

The above color burst signal is transmitted during the horizontal retrace period and inserted into the back porch following the horizontal synchronization signal (i).In order to use this color burst signal for demodulating the above-mentioned wrapped signal, generally A method is used in which the horizontal synchronizing signal is delayed to the temporal position of the color burst signal, and the delayed signal is used as a gate pulse to separate the color burst signal.

Conventionally, a positive horizontal synchronizing signal has been delayed by a pulse delay circuit shown in FIG. 1 and used as a gate pulse of a color burst signal. In FIG. 1, transistor 1 is turned on by the polarity of the horizontal synchronization signal as an input pulse signal to its base.

Turn off. Further, the transistor 2.3 constitutes a differential comparator and shapes the waveform of the base of the transistor 2. Transistor 4 forcibly sets the collector output of transistor 3 to O level (hereinafter referred to as mask) for a predetermined period.

The operation of the conventional pulse delay circuit configured as described above will now be described. It is assumed that the voltage between the base and emitter of each transistor is all VBB.

An input pulse signal as shown in FIG. 2a is applied to the base of the transistor 1. When the input pulse signal is H'' (Vl) (period T), the transistor 1 is turned on, and when the input pulse signal power is 1L'' (0), the transistor 1 is turned off.

When transistor J is in the on state, the potential VA of terminal A
(FIG. 2b), where VBE is the voltage between the base and emitter of the transistor 1, it is given by VA: V, -VBE .

When transistor 1 is off, capacitor 5
The electric charge charged in is discharged by the constant current source 6. In this case, 1 second after transistor 1 turns off, terminal A
The potential vA of is given by 1. However, Ii flowing through the constant current source 6, the current is ■h Capacity % of the capacitor 5 ``Ic C+ + Vt =
V+ VIIE.

In the transistors 2 and 3 constituting the differential comparator, when the base of the transistor 20 is at a potential υ higher than the base of the transistor 3, the transistor 2 is in an off state and the transistor 3 is in an off state. When the potential is reversed, the state is also reversed. At this time, the base of the transistor 3 is biased to the potential E by the constant voltage source 8, so the potential of the terminal A, which is the base potential of the transistor 2, is vA.
When is higher than the base potential E of the transistor 3, the transistor 3 is turned on and the current I from the constant current source 7 flows through the collector of the transistor 3.
masks the collector output of the transistor 3 when the input pulse signal is "Hu" (period T). Therefore, assuming that the resistance value of the resistor 9 is R1°, the output signal has the potential I, ,
R, as shown in FIG. 2C.

From the above, the pulse width To of the output signal is calculated from equation (1) to
=(VP −E+) C+/It・・・・・・
... is given by (2).

Here, since the circuit can be configured such that the potential E1 of the constant voltage source 8 has a resistance ratio of the reference potential Vco, even if this delay circuit is integrated into an integrated circuit, there is almost no influence from variations in the element values of the elements. However, since the six constant current sources are basically constructed as shown in FIG. 3, the current I is given by H.multidot.2, where the forward voltage drop tDp of the diode 6J is taken as tDp. However, 几 is the resistance of resistor 62]
It is.

From equations (2) and (3), the pulse width TG is affected by C1 and R52, so the pulse width TO varies significantly due to variations in the element density of each element due to integrated circuits. for example,
If the variation in the tree value of each element is 200/'o, the pulse width TG will vary by about 40%. Therefore, when gating a color burst signal, there may be a problem that signals other than the color burst signal can be gated or only a part of the color burst signals can be gated.

In addition, in order to gate the above color burst signal,
The pulse width TG is required to be approximately 5 μsec. At this time, the capacitance CI of the capacitor 5 must be reduced in order to integrate the circuit. However, when considering the stray capacitance between the base and emitter of transistor 1, the current I is several hundred
Since it is difficult to reduce the capacitance to less than μA, the capacitance CI of the capacitor 5 ends up being on the order of 1001)F. Therefore, it is impossible to integrate the circuit, and the capacitor must be removed externally.

Further, when a negative noise pulse is mixed into the input pulse signal shown in FIG. 4a, that is, the horizontal synchronizing signal, the waveform shown in FIG. 4C is outputted due to the influence of this noise pulse. This means that the potential of terminal A (Fig. 4b) is the potential E of constant voltage 8.
, the transistor 3 will be in an on state during the period when the potential of the terminal A exceeds El, regardless of the width of the input pulse signal.

When the signal shown in FIG. 4C is transmitted to the next stage as a gate pulse of a color burst signal, signals other than the color burst signal are gated, making it impossible to demodulate an accurate color difference signal. This caused problems with color synchronization, causing variations in the colors of the image.

[Purpose of the invention]

The present invention does not malfunction even when noise pulses are mixed in, and is not affected by fluctuations in the element values of the elements.

An object of the present invention is to provide a pulse delay circuit having a short delay time.

[Summary of the invention]

In this invention, a triangular wave signal is generated by charging and discharging a capacitor with a constant current according to the potential of an input pulse signal. The input pulse signal is delayed by comparing the potential of the triangular wave signal with a predetermined potential, and shaping the comparison waveform to generate a rectangular pulse signal for a predetermined period.

[Embodiments of the invention]

Below, with reference to FIG. 5, an embodiment of region 7 in which the present invention is applied to a gate pulse shaping circuit for color burst signals will be described.

The transistor 11 is turned on or off depending on the level of the input pulse signal applied to its base, and selectively turns on or off the transistors 1, 2, and 13 forming the differential comparator. When the transistor 12 is on, the constant current source 20 charges the capacitor n. The transistor 14 and the diode 15 constitute a current mirror circuit, and a current equal to the current flowing through the diode 15 flows through the transistor 14. Therefore, when transistor 13 is on, capacitor 22 is discharged with a constant current through transistor 14.

The pace of the transistor 16 is set to Ett by the constant voltage source 26.
Therefore, this transistor 16 changes the potential of capacitor 4 (potential of terminal B) to (Eu VBFi
) and performs clamping operation. Further, transistors 1, 7, and 18 constitute a differential comparator and shape the waveform of the pace of transistor 17. Transistor 19 masks the output of the collector of transistor 18 for a predetermined period.

The operation of this embodiment configured as described above will now be described.

An input pulse signal shown in FIG. 6a is applied to the base of the transistor 11. Input pulse signal is “H” (Vll)
When (period 1'), the transistor 11 is turned on, and when the input signal is L'' (0), the transistor 11 is turned off.

When transistor 1 is in the on state, the differential comparator.

The pace of one transistor 12 constituting it';
1.1', the base of the other transistor 130 biased by the constant voltage source 5, ttF'l! becomes lower and transistor 12 turns on. At this time, a current I from the constant current source 20 is applied to the collector of the transistor 12.
II charges the capacitor 22 with the current f1. Furthermore, when the transistor 11 is off, the base potential of the transistor 12 becomes the reference potential You, so the transistor 13 is turned on. At this time, a current III flows through the collector of the transistor 13, and one diode 15 forming the current mirror circuit is driven by a box current III.

Therefore, transistor 14 has 1. Ix ”u/B, 1(
The resistance values of the resistors 11 and 12 are "It", and a constant current (R111) flows first, and the capacitor 22 is discharged by this constant current.

The potential of the capacitor n (potential of terminal B) is changed by the transistor 16 as described above to V+t = Ett VB
Clamped above E.

From the above, the potential vB of the terminal B (FIG. 6b) t seconds after the transistor 11 is turned on is .

The potential VB at point B t seconds after the transistor 11 is turned off after the transistor 11 is turned on for one second is given by.

- Also, it is connected to the base terminal B of one transistor 17 constituting the differential comparator, and the base of the other transistor 180 is biased to potential Els by a constant voltage source υ. Therefore, when the potential of the terminal B, which is the pace potential of the transistor 17, is higher than the base potential HIII of the transistor 180, the transistor 18 is turned on, so that the current Lt of the constant current source 21 flows to the collector of the transistor 18. Therefore, when the input pulse signal is "H" (period "J"), the transistor 18
Since the collector output of the resistor is masked, the output signal becomes
・1 also becomes Ill, as shown in FIG. 6C.

From the above, the pulse width '1'0 of the output signal is given by equation (5). Here, (Els-VI2) is sufficient to be 111, which is necessary for switching of the differential comparator constituted by transistors 17 and 18. (6)
From the equation, it is possible to determine the pulse width TO' with high accuracy even when integrated circuits are used. In this case, in order to set the above formula to 005, “Is V12 == old V, i, .
== 1 (1 μA, T = 5 μscc, then Co =
25 p, 1! ', and the town became a guest lease of the town. Furthermore, each element is set to the above-mentioned value, and the constant current source 20 is set to the third
When using the same configuration as shown in the figure, the variation of each element is reduced by 20%.
Even so, the pulse width 'rG varies by only a few percent. Therefore, a delayed pulse with optical precision can be provided to gate the color burst signal.

Even if a noise pulse is mixed into the input pulse signal shown in Figure 7a, the width of the noise pulse (period T+) is sufficiently small (T+< (Els V+t)・Co/In
).

and does not appear in the output signal. In addition, even when the width of the noise pulse (period T) is somewhat large, the output signal is output for a period that depends on the width of the noise pulse, as shown in equation (6), and is not unrelated to the width of the noise pulse. Therefore, Even if the horizontal synchronization signal, which is easily affected by pulse noise, is a human pulse signal, this embodiment has a characteristic that it is hardly affected by the noise.

Next, a part of another embodiment of the present invention is shown in FIG. 8 and will be explained. Note that in the figure, parts having the same functions as those in FIG. 5 are given the same numbers, and explanations thereof will be omitted.

In this embodiment, when the input signal is H'', the base of one transistor J8 constituting the differential comparator is high, and when the input signal is
'', a low bias is applied to change the level at which the triangular wave signal generated at terminal B is compared.Furthermore, the base of the transistor 31 is connected to the 4th place LI by a constant voltage source 32.
Therefore, the emitter of the transistor 30, 3] is maintained above (Et+ -VBE). At this time, it is set higher than E, $(JJ, (the potential of the constant voltage source section in Fig. 5)).

In the above embodiment, the input pulse signal shown in FIG. 9a is applied to terminal C. When the input signal is ``H'' (Vo) (period T), the base potential V21 of the transistor blade becomes higher than the pace potential E21 of the transistor 31, and the transistor 3o is turned on. (
0), the transistor 31 is turned on. Therefore,
The potential of the terminal F, that is, the pace potential of the transistor 18 (dotted chain line in FIG. 9) is V2t=V2+VHE when the transistor is on, and 'b!' when the transistor 31 is on. ”” becomes E2I-VIIE.

On the other hand, the pace potential of the transistor 17 is the 9th [iQl
The result is as shown by the solid line b.

One of the 18 transistors constituting the differential comparator is turned on when the potential at terminal B is higher than the 214th point at terminal F, so the output signal becomes a potential of 112.1 (.18), as shown in Figure 9C. It will be as shown.

In this embodiment, as in the previous embodiment, the pulse width TG' of the output signal is given by replacing E13 in equation (6) with ■23. The width 'I'() has the advantage that it does not fluctuate tl due to variations in each element and is not easily affected by pulse noise.

As described above, the present invention is suitable for shaping a gate pulse such as a clock φ run-in signal in color burst signal single character multiplex broadcasting, which requires a highly accurate delay time. Furthermore, when integrated circuits are integrated, capacitors that were conventionally attached externally can be built-in, eliminating the need for external capacitors.

In addition, in the above-mentioned embodiment, the input cabling signal is H''
In the above case, the pulse period is used, but there is no need to be limited to this (the circuit may be configured with the "L" period as the pulse period).

〔Effect of the invention〕

As described above, according to the present invention, it is possible to obtain a pulse delay circuit that is not easily affected by pulse noise and is suitable for integration into an integrated circuit. Furthermore, when integrated into an integrated circuit, it is possible to extremely minimize fluctuations in the speaking time due to variations in each element.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional pulse delay circuit, Figs. 2 and 4 are waveform diagrams showing waveforms of each part in Fig. 1, and Fig. 3 shows a detailed explanation 1 of a part of Fig. 1. 5 is a circuit diagram showing one embodiment of the pulse delay circuit according to the present invention, FIGS. 6 and 7 are waveform diagrams showing waveforms of each part of FIG. 5, and FIG. 8 is a circuit diagram showing an embodiment of the pulse delay circuit according to the present invention. A circuit diagram showing a part of another embodiment, FIG.
FIG. 3 is a waveform diagram showing waveforms at various parts in the figure. 11, 12.13.14.16.17.1'8.19
．． 30.31... Transistor 15... Diode 20.21... Constant current source 22... Capacitor B, 24.28... Resistor 25.26, 27.32... Constant voltage Minamoto (7317) Agent Patent attorney Yu Noriuchika (and 1 other person) Fig. 1 Fig. 2 Fig. 3 V cc Fig. 4 Hiroshi, j1j Fig. 5 Fig. 6 Fig. 7

Claims (1)

[Claims] A differential switch in which a pulse voltage of a pulse to be delayed applied to an input terminal is applied to the base side of a first transistor, and the base of a second transistor is biased to a constant voltage; Connected to the common emitter connection end side of the differential switch,
a first constant current source that drives the differential switch; a capacitor connected between the collector current path of the first transistor and a reference potential and charged by the first constant current source; a second transistor that is energized when the first transistor is off and discharges the charge on the capacitor;
a constant current source, and a waveform that switches the sawtooth wave generated in the capacitor according to the voltage level and converts it into a rectangular wave, masks the original pulse to be delayed from this rectangular wave, and outputs a delayed pulse. 1. A pulse delay circuit comprising at least shaping means.